1 // SPDX-License-Identifier: GPL-2.0+
3 * K2G EVM : Board initialization
6 * Texas Instruments Incorporated, <www.ti.com>
14 #include <asm/arch/clock.h>
15 #include <asm/ti-common/keystone_net.h>
16 #include <asm/arch/psc_defs.h>
17 #include <asm/arch/mmc_host_def.h>
20 #include <remoteproc.h>
21 #include <linux/bitops.h>
22 #include <linux/delay.h>
24 #include "../common/board_detect.h"
26 #define K2G_GP_AUDIO_CODEC_ADDRESS 0x1B
28 const unsigned int sysclk_array[MAX_SYSCLK] = {
35 unsigned int get_external_clk(u32 clk)
37 unsigned int clk_freq;
38 u8 sysclk_index = get_sysclk_index();
42 clk_freq = sysclk_array[sysclk_index];
45 clk_freq = sysclk_array[sysclk_index];
48 clk_freq = sysclk_array[sysclk_index];
51 clk_freq = sysclk_array[sysclk_index];
54 clk_freq = sysclk_array[sysclk_index];
64 int speeds[DEVSPEED_NUMSPDS] = {
77 static int dev_speeds[DEVSPEED_NUMSPDS] = {
88 static struct pll_init_data main_pll_config[MAX_SYSCLK][NUM_SPDS] = {
90 [SPD400] = {MAIN_PLL, 125, 3, 2},
91 [SPD600] = {MAIN_PLL, 125, 2, 2},
92 [SPD800] = {MAIN_PLL, 250, 3, 2},
93 [SPD900] = {MAIN_PLL, 187, 2, 2},
94 [SPD1000] = {MAIN_PLL, 104, 1, 2},
97 [SPD400] = {MAIN_PLL, 100, 3, 2},
98 [SPD600] = {MAIN_PLL, 300, 6, 2},
99 [SPD800] = {MAIN_PLL, 200, 3, 2},
100 [SPD900] = {MAIN_PLL, 75, 1, 2},
101 [SPD1000] = {MAIN_PLL, 250, 3, 2},
104 [SPD400] = {MAIN_PLL, 32, 1, 2},
105 [SPD600] = {MAIN_PLL, 48, 1, 2},
106 [SPD800] = {MAIN_PLL, 64, 1, 2},
107 [SPD900] = {MAIN_PLL, 72, 1, 2},
108 [SPD1000] = {MAIN_PLL, 80, 1, 2},
111 [SPD400] = {MAIN_PLL, 400, 13, 2},
112 [SPD600] = {MAIN_PLL, 230, 5, 2},
113 [SPD800] = {MAIN_PLL, 123, 2, 2},
114 [SPD900] = {MAIN_PLL, 69, 1, 2},
115 [SPD1000] = {MAIN_PLL, 384, 5, 2},
119 static struct pll_init_data tetris_pll_config[MAX_SYSCLK][NUM_SPDS] = {
121 [SPD200] = {TETRIS_PLL, 625, 6, 10},
122 [SPD400] = {TETRIS_PLL, 125, 1, 6},
123 [SPD600] = {TETRIS_PLL, 125, 1, 4},
124 [SPD800] = {TETRIS_PLL, 333, 2, 4},
125 [SPD900] = {TETRIS_PLL, 187, 2, 2},
126 [SPD1000] = {TETRIS_PLL, 104, 1, 2},
129 [SPD200] = {TETRIS_PLL, 250, 3, 10},
130 [SPD400] = {TETRIS_PLL, 100, 1, 6},
131 [SPD600] = {TETRIS_PLL, 100, 1, 4},
132 [SPD800] = {TETRIS_PLL, 400, 3, 4},
133 [SPD900] = {TETRIS_PLL, 75, 1, 2},
134 [SPD1000] = {TETRIS_PLL, 250, 3, 2},
137 [SPD200] = {TETRIS_PLL, 80, 1, 10},
138 [SPD400] = {TETRIS_PLL, 96, 1, 6},
139 [SPD600] = {TETRIS_PLL, 96, 1, 4},
140 [SPD800] = {TETRIS_PLL, 128, 1, 4},
141 [SPD900] = {TETRIS_PLL, 72, 1, 2},
142 [SPD1000] = {TETRIS_PLL, 80, 1, 2},
145 [SPD200] = {TETRIS_PLL, 307, 4, 10},
146 [SPD400] = {TETRIS_PLL, 369, 4, 6},
147 [SPD600] = {TETRIS_PLL, 369, 4, 4},
148 [SPD800] = {TETRIS_PLL, 123, 1, 4},
149 [SPD900] = {TETRIS_PLL, 69, 1, 2},
150 [SPD1000] = {TETRIS_PLL, 384, 5, 2},
154 static struct pll_init_data uart_pll_config[MAX_SYSCLK] = {
155 [SYSCLK_19MHz] = {UART_PLL, 160, 1, 8},
156 [SYSCLK_24MHz] = {UART_PLL, 128, 1, 8},
157 [SYSCLK_25MHz] = {UART_PLL, 768, 5, 10},
158 [SYSCLK_26MHz] = {UART_PLL, 384, 13, 2},
161 static struct pll_init_data nss_pll_config[MAX_SYSCLK] = {
162 [SYSCLK_19MHz] = {NSS_PLL, 625, 6, 2},
163 [SYSCLK_24MHz] = {NSS_PLL, 250, 3, 2},
164 [SYSCLK_25MHz] = {NSS_PLL, 80, 1, 2},
165 [SYSCLK_26MHz] = {NSS_PLL, 1000, 13, 2},
168 static struct pll_init_data ddr3_pll_config_800[MAX_SYSCLK] = {
169 [SYSCLK_19MHz] = {DDR3A_PLL, 167, 1, 16},
170 [SYSCLK_24MHz] = {DDR3A_PLL, 133, 1, 16},
171 [SYSCLK_25MHz] = {DDR3A_PLL, 128, 1, 16},
172 [SYSCLK_26MHz] = {DDR3A_PLL, 123, 1, 16},
175 static struct pll_init_data ddr3_pll_config_1066[MAX_SYSCLK] = {
176 [SYSCLK_19MHz] = {DDR3A_PLL, 194, 1, 14},
177 [SYSCLK_24MHz] = {DDR3A_PLL, 156, 1, 14},
178 [SYSCLK_25MHz] = {DDR3A_PLL, 149, 1, 14},
179 [SYSCLK_26MHz] = {DDR3A_PLL, 144, 1, 14},
182 struct pll_init_data *get_pll_init_data(int pll)
185 struct pll_init_data *data = NULL;
186 u8 sysclk_index = get_sysclk_index();
190 speed = get_max_dev_speed(dev_speeds);
191 data = &main_pll_config[sysclk_index][speed];
194 speed = get_max_arm_speed(speeds);
195 data = &tetris_pll_config[sysclk_index][speed];
198 data = &nss_pll_config[sysclk_index];
201 data = &uart_pll_config[sysclk_index];
204 if (cpu_revision() & CPU_66AK2G1x) {
205 speed = get_max_arm_speed(speeds);
206 if (speed == SPD1000)
207 data = &ddr3_pll_config_1066[sysclk_index];
209 data = &ddr3_pll_config_800[sysclk_index];
211 data = &ddr3_pll_config_800[sysclk_index];
222 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
225 #if defined(CONFIG_MMC)
226 int board_mmc_init(bd_t *bis)
228 if (psc_enable_module(KS2_LPSC_MMC)) {
229 printf("%s module enabled failed\n", __func__);
233 if (board_is_k2g_gp() || board_is_k2g_g1())
234 omap_mmc_init(0, 0, 0, -1, -1);
236 omap_mmc_init(1, 0, 0, -1, -1);
241 #if defined(CONFIG_MULTI_DTB_FIT)
242 int board_fit_config_name_match(const char *name)
244 bool eeprom_read = board_ti_was_eeprom_read();
246 if (!strcmp(name, "keystone-k2g-generic") && !eeprom_read)
248 else if (!strcmp(name, "keystone-k2g-evm") &&
249 (board_ti_is("66AK2GGP") || board_ti_is("66AK2GG1")))
251 else if (!strcmp(name, "keystone-k2g-ice") && board_ti_is("66AK2GIC"))
258 #if defined(CONFIG_DTB_RESELECT)
259 static int k2g_alt_board_detect(void)
261 #ifndef CONFIG_DM_I2C
264 rc = i2c_set_bus_num(1);
268 rc = i2c_probe(K2G_GP_AUDIO_CODEC_ADDRESS);
272 struct udevice *bus, *dev;
275 rc = uclass_get_device_by_seq(UCLASS_I2C, 1, &bus);
278 rc = dm_i2c_probe(bus, K2G_GP_AUDIO_CODEC_ADDRESS, 0, &dev);
282 ti_i2c_eeprom_am_set("66AK2GGP", "1.0X");
287 static void k2g_reset_mux_config(void)
289 /* Unlock the reset mux register */
290 clrbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
292 /* Configure BOOTCFG_RSTMUX8 for WDT event to cause a device reset */
293 clrsetbits_le32(KS2_RSTMUX8, RSTMUX_OMODE8_MASK,
294 RSTMUX_OMODE8_DEV_RESET << RSTMUX_OMODE8_SHIFT);
296 /* lock the reset mux register to prevent any spurious writes. */
297 setbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
300 int embedded_dtb_select(void)
303 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
304 CONFIG_EEPROM_CHIP_ADDRESS);
306 rc = k2g_alt_board_detect();
308 printf("Unable to do board detection\n");
317 k2g_reset_mux_config();
319 if (board_is_k2g_gp() || board_is_k2g_g1()) {
320 /* deassert FLASH_HOLD */
321 clrbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_DIR_OFFSET,
323 setbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_SETDATA_OFFSET,
325 } else if (board_is_k2g_ice()) {
326 /* GBE Phy workaround. For Phy to latch the input
327 * configuration, a GPIO reset is asserted at the
328 * Phy reset pin to latch configuration correctly after SoC
329 * reset. GPIO0 Pin 10 (Ball AA20) is used for this on ICE
330 * board. Just do a low to high transition.
332 clrbits_le32(K2G_GPIO0_BANK0_BASE + K2G_GPIO_DIR_OFFSET,
334 setbits_le32(K2G_GPIO0_BANK0_BASE + K2G_GPIO_CLRDATA_OFFSET,
336 /* Delay just to get a transition to high */
338 setbits_le32(K2G_GPIO0_BANK0_BASE + K2G_GPIO_SETDATA_OFFSET,
346 #ifdef CONFIG_BOARD_LATE_INIT
347 int board_late_init(void)
349 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_TI_I2C_BOARD_DETECT)
352 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
353 CONFIG_EEPROM_CHIP_ADDRESS);
355 printf("ti_i2c_eeprom_init failed %d\n", rc);
357 board_ti_set_ethaddr(1);
360 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
361 if (board_is_k2g_gp())
362 env_set("board_name", "66AK2GGP\0");
363 else if (board_is_k2g_g1())
364 env_set("board_name", "66AK2GG1\0");
365 else if (board_is_k2g_ice())
366 env_set("board_name", "66AK2GIC\0");
372 #ifdef CONFIG_BOARD_EARLY_INIT_F
373 int board_early_init_f(void)
383 #ifdef CONFIG_SPL_BUILD
384 void spl_init_keystone_plls(void)
390 #ifdef CONFIG_TI_SECURE_DEVICE
391 void board_pmmc_image_process(ulong pmmc_image, size_t pmmc_size)
393 int id = env_get_ulong("dev_pmmc", 10, 0);
396 if (!rproc_is_initialized())
399 ret = rproc_load(id, pmmc_image, pmmc_size);
400 printf("Load Remote Processor %d with data@addr=0x%08lx %u bytes:%s\n",
401 id, pmmc_image, pmmc_size, ret ? " Failed!" : " Success!");
407 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_PMMC, board_pmmc_image_process);