board/ti/ks2_evm/board_k2g.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * K2G EVM : Board initialization
   4  *
   5  * (C) Copyright 2015
   6  *     Texas Instruments Incorporated, <www.ti.com>
   7  */
   8 #include <common.h>
   9 #include <eeprom.h>
  10 #include <env.h>
  11 #include <init.h>
  12 #include <asm/arch/clock.h>
  13 #include <asm/ti-common/keystone_net.h>
  14 #include <asm/arch/psc_defs.h>
  15 #include <asm/arch/mmc_host_def.h>
  16 #include <fdtdec.h>
  17 #include <i2c.h>
  18 #include <remoteproc.h>
  19 #include "mux-k2g.h"
  20 #include "../common/board_detect.h"
  21
  22 #define K2G_GP_AUDIO_CODEC_ADDRESS      0x1B
  23
  24 const unsigned int sysclk_array[MAX_SYSCLK] = {
  25         19200000,
  26         24000000,
  27         25000000,
  28         26000000,
  29 };
  30
  31 unsigned int get_external_clk(u32 clk)
  32 {
  33         unsigned int clk_freq;
  34         u8 sysclk_index = get_sysclk_index();
  35
  36         switch (clk) {
  37         case sys_clk:
  38                 clk_freq = sysclk_array[sysclk_index];
  39                 break;
  40         case pa_clk:
  41                 clk_freq = sysclk_array[sysclk_index];
  42                 break;
  43         case tetris_clk:
  44                 clk_freq = sysclk_array[sysclk_index];
  45                 break;
  46         case ddr3a_clk:
  47                 clk_freq = sysclk_array[sysclk_index];
  48                 break;
  49         case uart_clk:
  50                 clk_freq = sysclk_array[sysclk_index];
  51                 break;
  52         default:
  53                 clk_freq = 0;
  54                 break;
  55         }
  56
  57         return clk_freq;
  58 }
  59
  60 int speeds[DEVSPEED_NUMSPDS] = {
  61         SPD400,
  62         SPD600,
  63         SPD800,
  64         SPD900,
  65         SPD1000,
  66         SPD900,
  67         SPD800,
  68         SPD600,
  69         SPD400,
  70         SPD200,
  71 };
  72
  73 static int dev_speeds[DEVSPEED_NUMSPDS] = {
  74         SPD600,
  75         SPD800,
  76         SPD900,
  77         SPD1000,
  78         SPD900,
  79         SPD800,
  80         SPD600,
  81         SPD400,
  82 };
  83
  84 static struct pll_init_data main_pll_config[MAX_SYSCLK][NUM_SPDS] = {
  85         [SYSCLK_19MHz] = {
  86                 [SPD400]        = {MAIN_PLL, 125, 3, 2},
  87                 [SPD600]        = {MAIN_PLL, 125, 2, 2},
  88                 [SPD800]        = {MAIN_PLL, 250, 3, 2},
  89                 [SPD900]        = {MAIN_PLL, 187, 2, 2},
  90                 [SPD1000]       = {MAIN_PLL, 104, 1, 2},
  91         },
  92         [SYSCLK_24MHz] = {
  93                 [SPD400]        = {MAIN_PLL, 100, 3, 2},
  94                 [SPD600]        = {MAIN_PLL, 300, 6, 2},
  95                 [SPD800]        = {MAIN_PLL, 200, 3, 2},
  96                 [SPD900]        = {MAIN_PLL, 75, 1, 2},
  97                 [SPD1000]       = {MAIN_PLL, 250, 3, 2},
  98         },
  99         [SYSCLK_25MHz] = {
 100                 [SPD400]        = {MAIN_PLL, 32, 1, 2},
 101                 [SPD600]        = {MAIN_PLL, 48, 1, 2},
 102                 [SPD800]        = {MAIN_PLL, 64, 1, 2},
 103                 [SPD900]        = {MAIN_PLL, 72, 1, 2},
 104                 [SPD1000]       = {MAIN_PLL, 80, 1, 2},
 105         },
 106         [SYSCLK_26MHz] = {
 107                 [SPD400]        = {MAIN_PLL, 400, 13, 2},
 108                 [SPD600]        = {MAIN_PLL, 230, 5, 2},
 109                 [SPD800]        = {MAIN_PLL, 123, 2, 2},
 110                 [SPD900]        = {MAIN_PLL, 69, 1, 2},
 111                 [SPD1000]       = {MAIN_PLL, 384, 5, 2},
 112         },
 113 };
 114
 115 static struct pll_init_data tetris_pll_config[MAX_SYSCLK][NUM_SPDS] = {
 116         [SYSCLK_19MHz] = {
 117                 [SPD200]        = {TETRIS_PLL, 625, 6, 10},
 118                 [SPD400]        = {TETRIS_PLL, 125, 1, 6},
 119                 [SPD600]        = {TETRIS_PLL, 125, 1, 4},
 120                 [SPD800]        = {TETRIS_PLL, 333, 2, 4},
 121                 [SPD900]        = {TETRIS_PLL, 187, 2, 2},
 122                 [SPD1000]       = {TETRIS_PLL, 104, 1, 2},
 123         },
 124         [SYSCLK_24MHz] = {
 125                 [SPD200]        = {TETRIS_PLL, 250, 3, 10},
 126                 [SPD400]        = {TETRIS_PLL, 100, 1, 6},
 127                 [SPD600]        = {TETRIS_PLL, 100, 1, 4},
 128                 [SPD800]        = {TETRIS_PLL, 400, 3, 4},
 129                 [SPD900]        = {TETRIS_PLL, 75, 1, 2},
 130                 [SPD1000]       = {TETRIS_PLL, 250, 3, 2},
 131         },
 132         [SYSCLK_25MHz] = {
 133                 [SPD200]        = {TETRIS_PLL, 80, 1, 10},
 134                 [SPD400]        = {TETRIS_PLL, 96, 1, 6},
 135                 [SPD600]        = {TETRIS_PLL, 96, 1, 4},
 136                 [SPD800]        = {TETRIS_PLL, 128, 1, 4},
 137                 [SPD900]        = {TETRIS_PLL, 72, 1, 2},
 138                 [SPD1000]       = {TETRIS_PLL, 80, 1, 2},
 139         },
 140         [SYSCLK_26MHz] = {
 141                 [SPD200]        = {TETRIS_PLL, 307, 4, 10},
 142                 [SPD400]        = {TETRIS_PLL, 369, 4, 6},
 143                 [SPD600]        = {TETRIS_PLL, 369, 4, 4},
 144                 [SPD800]        = {TETRIS_PLL, 123, 1, 4},
 145                 [SPD900]        = {TETRIS_PLL, 69, 1, 2},
 146                 [SPD1000]       = {TETRIS_PLL, 384, 5, 2},
 147         },
 148 };
 149
 150 static struct pll_init_data uart_pll_config[MAX_SYSCLK] = {
 151         [SYSCLK_19MHz] = {UART_PLL, 160, 1, 8},
 152         [SYSCLK_24MHz] = {UART_PLL, 128, 1, 8},
 153         [SYSCLK_25MHz] = {UART_PLL, 768, 5, 10},
 154         [SYSCLK_26MHz] = {UART_PLL, 384, 13, 2},
 155 };
 156
 157 static struct pll_init_data nss_pll_config[MAX_SYSCLK] = {
 158         [SYSCLK_19MHz] = {NSS_PLL, 625, 6, 2},
 159         [SYSCLK_24MHz] = {NSS_PLL, 250, 3, 2},
 160         [SYSCLK_25MHz] = {NSS_PLL, 80, 1, 2},
 161         [SYSCLK_26MHz] = {NSS_PLL, 1000, 13, 2},
 162 };
 163
 164 static struct pll_init_data ddr3_pll_config_800[MAX_SYSCLK] = {
 165         [SYSCLK_19MHz] = {DDR3A_PLL, 167, 1, 16},
 166         [SYSCLK_24MHz] = {DDR3A_PLL, 133, 1, 16},
 167         [SYSCLK_25MHz] = {DDR3A_PLL, 128, 1, 16},
 168         [SYSCLK_26MHz] = {DDR3A_PLL, 123, 1, 16},
 169 };
 170
 171 static struct pll_init_data ddr3_pll_config_1066[MAX_SYSCLK] = {
 172         [SYSCLK_19MHz] = {DDR3A_PLL, 194, 1, 14},
 173         [SYSCLK_24MHz] = {DDR3A_PLL, 156, 1, 14},
 174         [SYSCLK_25MHz] = {DDR3A_PLL, 149, 1, 14},
 175         [SYSCLK_26MHz] = {DDR3A_PLL, 144, 1, 14},
 176 };
 177
 178 struct pll_init_data *get_pll_init_data(int pll)
 179 {
 180         int speed;
 181         struct pll_init_data *data = NULL;
 182         u8 sysclk_index = get_sysclk_index();
 183
 184         switch (pll) {
 185         case MAIN_PLL:
 186                 speed = get_max_dev_speed(dev_speeds);
 187                 data = &main_pll_config[sysclk_index][speed];
 188                 break;
 189         case TETRIS_PLL:
 190                 speed = get_max_arm_speed(speeds);
 191                 data = &tetris_pll_config[sysclk_index][speed];
 192                 break;
 193         case NSS_PLL:
 194                 data = &nss_pll_config[sysclk_index];
 195                 break;
 196         case UART_PLL:
 197                 data = &uart_pll_config[sysclk_index];
 198                 break;
 199         case DDR3_PLL:
 200                 if (cpu_revision() & CPU_66AK2G1x) {
 201                         speed = get_max_arm_speed(speeds);
 202                         if (speed == SPD1000)
 203                                 data = &ddr3_pll_config_1066[sysclk_index];
 204                         else
 205                                 data = &ddr3_pll_config_800[sysclk_index];
 206                 } else {
 207                         data = &ddr3_pll_config_800[sysclk_index];
 208                 }
 209                 break;
 210         default:
 211                 data = NULL;
 212         }
 213
 214         return data;
 215 }
 216
 217 s16 divn_val[16] = {
 218         -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
 219 };
 220
 221 #if defined(CONFIG_MMC)
 222 int board_mmc_init(bd_t *bis)
 223 {
 224         if (psc_enable_module(KS2_LPSC_MMC)) {
 225                 printf("%s module enabled failed\n", __func__);
 226                 return -1;
 227         }
 228
 229         if (board_is_k2g_gp() || board_is_k2g_g1())
 230                 omap_mmc_init(0, 0, 0, -1, -1);
 231
 232         omap_mmc_init(1, 0, 0, -1, -1);
 233         return 0;
 234 }
 235 #endif
 236
 237 #if defined(CONFIG_MULTI_DTB_FIT)
 238 int board_fit_config_name_match(const char *name)
 239 {
 240         bool eeprom_read = board_ti_was_eeprom_read();
 241
 242         if (!strcmp(name, "keystone-k2g-generic") && !eeprom_read)
 243                 return 0;
 244         else if (!strcmp(name, "keystone-k2g-evm") &&
 245                 (board_ti_is("66AK2GGP") || board_ti_is("66AK2GG1")))
 246                 return 0;
 247         else if (!strcmp(name, "keystone-k2g-ice") && board_ti_is("66AK2GIC"))
 248                 return 0;
 249         else
 250                 return -1;
 251 }
 252 #endif
 253
 254 #if defined(CONFIG_DTB_RESELECT)
 255 static int k2g_alt_board_detect(void)
 256 {
 257 #ifndef CONFIG_DM_I2C
 258         int rc;
 259
 260         rc = i2c_set_bus_num(1);
 261         if (rc)
 262                 return rc;
 263
 264         rc = i2c_probe(K2G_GP_AUDIO_CODEC_ADDRESS);
 265         if (rc)
 266                 return rc;
 267 #else
 268         struct udevice *bus, *dev;
 269         int rc;
 270
 271         rc = uclass_get_device_by_seq(UCLASS_I2C, 1, &bus);
 272         if (rc)
 273                 return rc;
 274         rc = dm_i2c_probe(bus, K2G_GP_AUDIO_CODEC_ADDRESS, 0, &dev);
 275         if (rc)
 276                 return rc;
 277 #endif
 278         ti_i2c_eeprom_am_set("66AK2GGP", "1.0X");
 279
 280         return 0;
 281 }
 282
 283 static void k2g_reset_mux_config(void)
 284 {
 285         /* Unlock the reset mux register */
 286         clrbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
 287
 288         /* Configure BOOTCFG_RSTMUX8 for WDT event to cause a device reset */
 289         clrsetbits_le32(KS2_RSTMUX8, RSTMUX_OMODE8_MASK,
 290                         RSTMUX_OMODE8_DEV_RESET << RSTMUX_OMODE8_SHIFT);
 291
 292         /* lock the reset mux register to prevent any spurious writes. */
 293         setbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
 294 }
 295
 296 int embedded_dtb_select(void)
 297 {
 298         int rc;
 299         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 300                         CONFIG_EEPROM_CHIP_ADDRESS);
 301         if (rc) {
 302                 rc = k2g_alt_board_detect();
 303                 if (rc) {
 304                         printf("Unable to do board detection\n");
 305                         return -1;
 306                 }
 307         }
 308
 309         fdtdec_setup();
 310
 311         k2g_mux_config();
 312
 313         k2g_reset_mux_config();
 314
 315         if (board_is_k2g_gp() || board_is_k2g_g1()) {
 316                 /* deassert FLASH_HOLD */
 317                 clrbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_DIR_OFFSET,
 318                              BIT(9));
 319                 setbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_SETDATA_OFFSET,
 320                              BIT(9));
 321         } else if (board_is_k2g_ice()) {
 322                 /* GBE Phy workaround. For Phy to latch the input
 323                  * configuration, a GPIO reset is asserted at the
 324                  * Phy reset pin to latch configuration correctly after SoC
 325                  * reset. GPIO0 Pin 10 (Ball AA20) is used for this on ICE
 326                  * board. Just do a low to high transition.
 327                  */
 328                 clrbits_le32(K2G_GPIO0_BANK0_BASE + K2G_GPIO_DIR_OFFSET,
 329                              BIT(10));
 330                 setbits_le32(K2G_GPIO0_BANK0_BASE + K2G_GPIO_CLRDATA_OFFSET,
 331                              BIT(10));
 332                 /* Delay just to get a transition to high */
 333                 udelay(100);
 334                 setbits_le32(K2G_GPIO0_BANK0_BASE + K2G_GPIO_SETDATA_OFFSET,
 335                              BIT(10));
 336         }
 337
 338         return 0;
 339 }
 340 #endif
 341
 342 #ifdef CONFIG_BOARD_LATE_INIT
 343 int board_late_init(void)
 344 {
 345 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_TI_I2C_BOARD_DETECT)
 346         int rc;
 347
 348         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 349                         CONFIG_EEPROM_CHIP_ADDRESS);
 350         if (rc)
 351                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 352
 353         board_ti_set_ethaddr(1);
 354 #endif
 355
 356 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 357         if (board_is_k2g_gp())
 358                 env_set("board_name", "66AK2GGP\0");
 359         else if (board_is_k2g_g1())
 360                 env_set("board_name", "66AK2GG1\0");
 361         else if (board_is_k2g_ice())
 362                 env_set("board_name", "66AK2GIC\0");
 363 #endif
 364         return 0;
 365 }
 366 #endif
 367
 368 #ifdef CONFIG_BOARD_EARLY_INIT_F
 369 int board_early_init_f(void)
 370 {
 371         init_plls();
 372
 373         k2g_mux_config();
 374
 375         return 0;
 376 }
 377 #endif
 378
 379 #ifdef CONFIG_SPL_BUILD
 380 void spl_init_keystone_plls(void)
 381 {
 382         init_plls();
 383 }
 384 #endif
 385
 386 #ifdef CONFIG_TI_SECURE_DEVICE
 387 void board_pmmc_image_process(ulong pmmc_image, size_t pmmc_size)
 388 {
 389         int id = env_get_ulong("dev_pmmc", 10, 0);
 390         int ret;
 391
 392         if (!rproc_is_initialized())
 393                 rproc_init();
 394
 395         ret = rproc_load(id, pmmc_image, pmmc_size);
 396         printf("Load Remote Processor %d with data@addr=0x%08lx %u bytes:%s\n",
 397                id, pmmc_image, pmmc_size, ret ? " Failed!" : " Success!");
 398
 399         if (!ret)
 400                 rproc_start(id);
 401 }
 402
 403 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_PMMC, board_pmmc_image_process);
 404 #endif