board/ti/ks2_evm/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Keystone : Board initialization
   4  *
   5  * (C) Copyright 2014
   6  *     Texas Instruments Incorporated, <www.ti.com>
   7  */
   8
   9 #include <common.h>
  10 #include "board.h"
  11 #include <spl.h>
  12 #include <exports.h>
  13 #include <fdt_support.h>
  14 #include <asm/arch/ddr3.h>
  15 #include <asm/arch/psc_defs.h>
  16 #include <asm/arch/clock.h>
  17 #include <asm/ti-common/ti-aemif.h>
  18 #include <asm/ti-common/keystone_net.h>
  19
  20 DECLARE_GLOBAL_DATA_PTR;
  21
  22 #if defined(CONFIG_TI_AEMIF)
  23 static struct aemif_config aemif_configs[] = {
  24         {                       /* CS0 */
  25                 .mode           = AEMIF_MODE_NAND,
  26                 .wr_setup       = 0xf,
  27                 .wr_strobe      = 0x3f,
  28                 .wr_hold        = 7,
  29                 .rd_setup       = 0xf,
  30                 .rd_strobe      = 0x3f,
  31                 .rd_hold        = 7,
  32                 .turn_around    = 3,
  33                 .width          = AEMIF_WIDTH_8,
  34         },
  35 };
  36 #endif
  37
  38 int dram_init(void)
  39 {
  40         u32 ddr3_size;
  41
  42         ddr3_size = ddr3_init();
  43
  44         gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
  45                                     CONFIG_MAX_RAM_BANK_SIZE);
  46 #if defined(CONFIG_TI_AEMIF)
  47         if (!board_is_k2g_ice())
  48                 aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);
  49 #endif
  50
  51         if (!board_is_k2g_ice()) {
  52                 if (ddr3_size)
  53                         ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size);
  54                 else
  55                         ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE,
  56                                       gd->ram_size >> 30);
  57         }
  58
  59         return 0;
  60 }
  61
  62 struct image_header *spl_get_load_buffer(ssize_t offset, size_t size)
  63 {
  64         return (struct image_header *)(CONFIG_SYS_TEXT_BASE);
  65 }
  66
  67 int board_init(void)
  68 {
  69 #if CONFIG_IS_ENABLED(DM_USB)
  70         int rc = psc_enable_module(KS2_LPSC_USB);
  71
  72         if (rc)
  73                 puts("Cannot enable USB0 module");
  74 #ifdef KS2_LPSC_USB_1
  75         rc = psc_enable_module(KS2_LPSC_USB_1);
  76         if (rc)
  77                 puts("Cannot enable USB1 module");
  78 #endif
  79 #endif
  80
  81         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  82
  83         return 0;
  84 }
  85
  86 #ifdef CONFIG_SPL_BUILD
  87 void spl_board_init(void)
  88 {
  89         spl_init_keystone_plls();
  90         preloader_console_init();
  91 }
  92
  93 u32 spl_boot_device(void)
  94 {
  95 #if defined(CONFIG_SPL_SPI_LOAD)
  96         return BOOT_DEVICE_SPI;
  97 #else
  98         puts("Unknown boot device\n");
  99         hang();
 100 #endif
 101 }
 102 #endif
 103
 104 #ifdef CONFIG_OF_BOARD_SETUP
 105 int ft_board_setup(void *blob, bd_t *bd)
 106 {
 107         int lpae;
 108         char *env;
 109         char *endp;
 110         int nbanks;
 111         u64 size[2];
 112         u64 start[2];
 113         u32 ddr3a_size;
 114
 115         env = env_get("mem_lpae");
 116         lpae = env && simple_strtol(env, NULL, 0);
 117
 118         ddr3a_size = 0;
 119         if (lpae) {
 120                 ddr3a_size = ddr3_get_size();
 121                 if ((ddr3a_size != 8) && (ddr3a_size != 4))
 122                         ddr3a_size = 0;
 123         }
 124
 125         nbanks = 1;
 126         start[0] = bd->bi_dram[0].start;
 127         size[0]  = bd->bi_dram[0].size;
 128
 129         /* adjust memory start address for LPAE */
 130         if (lpae) {
 131                 start[0] -= CONFIG_SYS_SDRAM_BASE;
 132                 start[0] += CONFIG_SYS_LPAE_SDRAM_BASE;
 133         }
 134
 135         if ((size[0] == 0x80000000) && (ddr3a_size != 0)) {
 136                 size[1] = ((u64)ddr3a_size - 2) << 30;
 137                 start[1] = 0x880000000;
 138                 nbanks++;
 139         }
 140
 141         /* reserve memory at start of bank */
 142         env = env_get("mem_reserve_head");
 143         if (env) {
 144                 start[0] += ustrtoul(env, &endp, 0);
 145                 size[0] -= ustrtoul(env, &endp, 0);
 146         }
 147
 148         env = env_get("mem_reserve");
 149         if (env)
 150                 size[0] -= ustrtoul(env, &endp, 0);
 151
 152         fdt_fixup_memory_banks(blob, start, size, nbanks);
 153
 154         return 0;
 155 }
 156
 157 void ft_board_setup_ex(void *blob, bd_t *bd)
 158 {
 159         int lpae;
 160         u64 size;
 161         char *env;
 162         u64 *reserve_start;
 163         int unitrd_fixup = 0;
 164
 165         env = env_get("mem_lpae");
 166         lpae = env && simple_strtol(env, NULL, 0);
 167         env = env_get("uinitrd_fixup");
 168         unitrd_fixup = env && simple_strtol(env, NULL, 0);
 169
 170         /* Fix up the initrd */
 171         if (lpae && unitrd_fixup) {
 172                 int nodeoffset;
 173                 int err;
 174                 u64 *prop1, *prop2;
 175                 u64 initrd_start, initrd_end;
 176
 177                 nodeoffset = fdt_path_offset(blob, "/chosen");
 178                 if (nodeoffset >= 0) {
 179                         prop1 = (u64 *)fdt_getprop(blob, nodeoffset,
 180                                             "linux,initrd-start", NULL);
 181                         prop2 = (u64 *)fdt_getprop(blob, nodeoffset,
 182                                             "linux,initrd-end", NULL);
 183                         if (prop1 && prop2) {
 184                                 initrd_start = __be64_to_cpu(*prop1);
 185                                 initrd_start -= CONFIG_SYS_SDRAM_BASE;
 186                                 initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE;
 187                                 initrd_start = __cpu_to_be64(initrd_start);
 188                                 initrd_end = __be64_to_cpu(*prop2);
 189                                 initrd_end -= CONFIG_SYS_SDRAM_BASE;
 190                                 initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE;
 191                                 initrd_end = __cpu_to_be64(initrd_end);
 192
 193                                 err = fdt_delprop(blob, nodeoffset,
 194                                                   "linux,initrd-start");
 195                                 if (err < 0)
 196                                         puts("error deleting initrd-start\n");
 197
 198                                 err = fdt_delprop(blob, nodeoffset,
 199                                                   "linux,initrd-end");
 200                                 if (err < 0)
 201                                         puts("error deleting initrd-end\n");
 202
 203                                 err = fdt_setprop(blob, nodeoffset,
 204                                                   "linux,initrd-start",
 205                                                   &initrd_start,
 206                                                   sizeof(initrd_start));
 207                                 if (err < 0)
 208                                         puts("error adding initrd-start\n");
 209
 210                                 err = fdt_setprop(blob, nodeoffset,
 211                                                   "linux,initrd-end",
 212                                                   &initrd_end,
 213                                                   sizeof(initrd_end));
 214                                 if (err < 0)
 215                                         puts("error adding linux,initrd-end\n");
 216                         }
 217                 }
 218         }
 219
 220         if (lpae) {
 221                 /*
 222                  * the initrd and other reserved memory areas are
 223                  * embedded in in the DTB itslef. fix up these addresses
 224                  * to 36 bit format
 225                  */
 226                 reserve_start = (u64 *)((char *)blob +
 227                                        fdt_off_mem_rsvmap(blob));
 228                 while (1) {
 229                         *reserve_start = __cpu_to_be64(*reserve_start);
 230                         size = __cpu_to_be64(*(reserve_start + 1));
 231                         if (size) {
 232                                 *reserve_start -= CONFIG_SYS_SDRAM_BASE;
 233                                 *reserve_start +=
 234                                         CONFIG_SYS_LPAE_SDRAM_BASE;
 235                                 *reserve_start =
 236                                         __cpu_to_be64(*reserve_start);
 237                         } else {
 238                                 break;
 239                         }
 240                         reserve_start += 2;
 241                 }
 242         }
 243
 244         ddr3_check_ecc_int(KS2_DDR3A_EMIF_CTRL_BASE);
 245 }
 246 #endif /* CONFIG_OF_BOARD_SETUP */
 247
 248 #if defined(CONFIG_DTB_RESELECT)
 249 int __weak embedded_dtb_select(void)
 250 {
 251         return 0;
 252 }
 253 #endif