1 // SPDX-License-Identifier: GPL-2.0+
3 * Keystone : Board initialization
6 * Texas Instruments Incorporated, <www.ti.com>
16 #include <fdt_support.h>
17 #include <asm/arch/ddr3.h>
18 #include <asm/arch/psc_defs.h>
19 #include <asm/arch/clock.h>
20 #include <asm/ti-common/ti-aemif.h>
21 #include <asm/ti-common/keystone_net.h>
23 DECLARE_GLOBAL_DATA_PTR;
25 #if defined(CONFIG_TI_AEMIF)
26 static struct aemif_config aemif_configs[] = {
28 .mode = AEMIF_MODE_NAND,
36 .width = AEMIF_WIDTH_8,
45 ddr3_size = ddr3_init();
47 gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
48 CONFIG_MAX_RAM_BANK_SIZE);
49 #if defined(CONFIG_TI_AEMIF)
50 if (!board_is_k2g_ice())
51 aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);
54 if (!board_is_k2g_ice()) {
56 ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size);
58 ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE,
65 struct image_header *spl_get_load_buffer(ssize_t offset, size_t size)
67 return (struct image_header *)(CONFIG_SYS_TEXT_BASE);
72 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
76 #ifdef CONFIG_SPL_BUILD
77 void spl_board_init(void)
79 spl_init_keystone_plls();
80 preloader_console_init();
83 u32 spl_boot_device(void)
85 #if defined(CONFIG_SPL_SPI_LOAD)
86 return BOOT_DEVICE_SPI;
88 puts("Unknown boot device\n");
94 #ifdef CONFIG_OF_BOARD_SETUP
95 int ft_board_setup(void *blob, bd_t *bd)
105 env = env_get("mem_lpae");
106 lpae = env && simple_strtol(env, NULL, 0);
110 ddr3a_size = ddr3_get_size();
111 if ((ddr3a_size != 8) && (ddr3a_size != 4))
116 start[0] = bd->bi_dram[0].start;
117 size[0] = bd->bi_dram[0].size;
119 /* adjust memory start address for LPAE */
121 start[0] -= CONFIG_SYS_SDRAM_BASE;
122 start[0] += CONFIG_SYS_LPAE_SDRAM_BASE;
125 if ((size[0] == 0x80000000) && (ddr3a_size != 0)) {
126 size[1] = ((u64)ddr3a_size - 2) << 30;
127 start[1] = 0x880000000;
131 /* reserve memory at start of bank */
132 env = env_get("mem_reserve_head");
134 start[0] += ustrtoul(env, &endp, 0);
135 size[0] -= ustrtoul(env, &endp, 0);
138 env = env_get("mem_reserve");
140 size[0] -= ustrtoul(env, &endp, 0);
142 fdt_fixup_memory_banks(blob, start, size, nbanks);
147 void ft_board_setup_ex(void *blob, bd_t *bd)
153 int unitrd_fixup = 0;
155 env = env_get("mem_lpae");
156 lpae = env && simple_strtol(env, NULL, 0);
157 env = env_get("uinitrd_fixup");
158 unitrd_fixup = env && simple_strtol(env, NULL, 0);
160 /* Fix up the initrd */
161 if (lpae && unitrd_fixup) {
165 u64 initrd_start, initrd_end;
167 nodeoffset = fdt_path_offset(blob, "/chosen");
168 if (nodeoffset >= 0) {
169 prop1 = (u64 *)fdt_getprop(blob, nodeoffset,
170 "linux,initrd-start", NULL);
171 prop2 = (u64 *)fdt_getprop(blob, nodeoffset,
172 "linux,initrd-end", NULL);
173 if (prop1 && prop2) {
174 initrd_start = __be64_to_cpu(*prop1);
175 initrd_start -= CONFIG_SYS_SDRAM_BASE;
176 initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE;
177 initrd_start = __cpu_to_be64(initrd_start);
178 initrd_end = __be64_to_cpu(*prop2);
179 initrd_end -= CONFIG_SYS_SDRAM_BASE;
180 initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE;
181 initrd_end = __cpu_to_be64(initrd_end);
183 err = fdt_delprop(blob, nodeoffset,
184 "linux,initrd-start");
186 puts("error deleting initrd-start\n");
188 err = fdt_delprop(blob, nodeoffset,
191 puts("error deleting initrd-end\n");
193 err = fdt_setprop(blob, nodeoffset,
194 "linux,initrd-start",
196 sizeof(initrd_start));
198 puts("error adding initrd-start\n");
200 err = fdt_setprop(blob, nodeoffset,
205 puts("error adding linux,initrd-end\n");
212 * the initrd and other reserved memory areas are
213 * embedded in in the DTB itslef. fix up these addresses
216 reserve_start = (u64 *)((char *)blob +
217 fdt_off_mem_rsvmap(blob));
219 *reserve_start = __cpu_to_be64(*reserve_start);
220 size = __cpu_to_be64(*(reserve_start + 1));
222 *reserve_start -= CONFIG_SYS_SDRAM_BASE;
224 CONFIG_SYS_LPAE_SDRAM_BASE;
226 __cpu_to_be64(*reserve_start);
234 ddr3_check_ecc_int(KS2_DDR3A_EMIF_CTRL_BASE);
236 #endif /* CONFIG_OF_BOARD_SETUP */
238 #if defined(CONFIG_DTB_RESELECT)
239 int __weak embedded_dtb_select(void)