2 * Keystone2: DDR3 initialization
4 * (C) Copyright 2012-2014
5 * Texas Instruments Incorporated, <www.ti.com>
7 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/hardware.h>
15 /************************* *****************************/
16 static struct ddr3_phy_config ddr3phy_1600_64A = {
17 .pllcr = 0x0001C000ul,
18 .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
19 .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
22 .ptr2 = 0, /* not set in gel */
25 .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK),
26 .dcr_val = ((1 << 10) | (1 << 27)),
27 .dtpr0 = 0xA19DBB66ul,
28 .dtpr1 = 0x12868300ul,
29 .dtpr2 = 0x50035200ul,
34 .pgcr2 = 0x00F07A12ul,
35 .zq0cr1 = 0x0000005Dul,
36 .zq1cr1 = 0x0000005Bul,
37 .zq2cr1 = 0x0000005Bul,
38 .pir_v1 = 0x00000033ul,
39 .pir_v2 = 0x0000FF81ul,
42 static struct ddr3_emif_config ddr3_1600_64 = {
43 .sdcfg = 0x6200CE6aul,
44 .sdtim1 = 0x16709C55ul,
45 .sdtim2 = 0x00001D4Aul,
46 .sdtim3 = 0x435DFF54ul,
47 .sdtim4 = 0x553F0CFFul,
48 .zqcfg = 0xF0073200ul,
49 .sdrfc = 0x00001869ul,
52 static struct ddr3_phy_config ddr3phy_1600_32 = {
53 .pllcr = 0x0001C000ul,
54 .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
55 .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
58 .ptr2 = 0, /* not set in gel */
61 .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK),
62 .dcr_val = ((1 << 10) | (1 << 27)),
63 .dtpr0 = 0xA19DBB66ul,
64 .dtpr1 = 0x12868300ul,
65 .dtpr2 = 0x50035200ul,
70 .pgcr2 = 0x00F07A12ul,
71 .zq0cr1 = 0x0000005Dul,
72 .zq1cr1 = 0x0000005Bul,
73 .zq2cr1 = 0x0000005Bul,
74 .pir_v1 = 0x00000033ul,
75 .pir_v2 = 0x0000FF81ul,
78 static struct ddr3_emif_config ddr3_1600_32 = {
79 .sdcfg = 0x6200DE6aul,
80 .sdtim1 = 0x16709C55ul,
81 .sdtim2 = 0x00001D4Aul,
82 .sdtim3 = 0x435DFF54ul,
83 .sdtim4 = 0x553F0CFFul,
84 .zqcfg = 0x70073200ul,
85 .sdrfc = 0x00001869ul,
88 /************************* *****************************/
89 static struct ddr3_phy_config ddr3phy_1333_64A = {
90 .pllcr = 0x0005C000ul,
91 .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
92 .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
95 .ptr2 = 0, /* not set in gel */
98 .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK |
99 NOSRA_MASK | UDIMM_MASK),
100 .dcr_val = ((1 << 10) | (1 << 27) | (1 << 29)),
101 .dtpr0 = 0x8558AA55ul,
102 .dtpr1 = 0x12857280ul,
103 .dtpr2 = 0x5002C200ul,
107 .dtcr = 0x710035C7ul,
108 .pgcr2 = 0x00F065B8ul,
109 .zq0cr1 = 0x0000005Dul,
110 .zq1cr1 = 0x0000005Bul,
111 .zq2cr1 = 0x0000005Bul,
112 .pir_v1 = 0x00000033ul,
113 .pir_v2 = 0x0000FF81ul,
116 static struct ddr3_emif_config ddr3_1333_64 = {
117 .sdcfg = 0x62008C62ul,
118 .sdtim1 = 0x125C8044ul,
119 .sdtim2 = 0x00001D29ul,
120 .sdtim3 = 0x32CDFF43ul,
121 .sdtim4 = 0x543F0ADFul,
122 .zqcfg = 0xF0073200ul,
123 .sdrfc = 0x00001457ul,
126 static struct ddr3_phy_config ddr3phy_1333_32 = {
127 .pllcr = 0x0005C000ul,
128 .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
129 .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
130 .ptr0 = 0x42C21590ul,
131 .ptr1 = 0xD05612C0ul,
132 .ptr2 = 0, /* not set in gel */
133 .ptr3 = 0x0B4515C2ul,
134 .ptr4 = 0x0A6E08B4ul,
135 .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK |
136 NOSRA_MASK | UDIMM_MASK),
137 .dcr_val = ((1 << 10) | (1 << 27) | (1 << 29)),
138 .dtpr0 = 0x8558AA55ul,
139 .dtpr1 = 0x12857280ul,
140 .dtpr2 = 0x5002C200ul,
144 .dtcr = 0x710035C7ul,
145 .pgcr2 = 0x00F065B8ul,
146 .zq0cr1 = 0x0000005Dul,
147 .zq1cr1 = 0x0000005Bul,
148 .zq2cr1 = 0x0000005Bul,
149 .pir_v1 = 0x00000033ul,
150 .pir_v2 = 0x0000FF81ul,
153 static struct ddr3_emif_config ddr3_1333_32 = {
154 .sdcfg = 0x62009C62ul,
155 .sdtim1 = 0x125C8044ul,
156 .sdtim2 = 0x00001D29ul,
157 .sdtim3 = 0x32CDFF43ul,
158 .sdtim4 = 0x543F0ADFul,
159 .zqcfg = 0xf0073200ul,
160 .sdrfc = 0x00001457ul,
163 /************************* *****************************/
164 static struct ddr3_phy_config ddr3phy_1333_64 = {
165 .pllcr = 0x0005C000ul,
166 .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
167 .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
168 .ptr0 = 0x42C21590ul,
169 .ptr1 = 0xD05612C0ul,
170 .ptr2 = 0, /* not set in gel */
171 .ptr3 = 0x0B4515C2ul,
172 .ptr4 = 0x0A6E08B4ul,
173 .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK),
174 .dcr_val = ((1 << 10) | (1 << 27)),
175 .dtpr0 = 0x8558AA55ul,
176 .dtpr1 = 0x12857280ul,
177 .dtpr2 = 0x5002C200ul,
181 .dtcr = 0x710035C7ul,
182 .pgcr2 = 0x00F065B8ul,
183 .zq0cr1 = 0x0000005Dul,
184 .zq1cr1 = 0x0000005Bul,
185 .zq2cr1 = 0x0000005Bul,
186 .pir_v1 = 0x00000033ul,
187 .pir_v2 = 0x0000FF81ul,
189 /******************************************************/
190 int get_dimm_params(char *dimm_name)
196 i2c_init(CONFIG_SYS_DAVINCI_I2C_SPEED, CONFIG_SYS_DAVINCI_I2C_SLAVE);
198 old_bus = i2c_get_bus_num();
201 ret = i2c_read(0x53, 0, 1, spd_params, 256);
203 i2c_set_bus_num(old_bus);
208 puts("Cannot read DIMM params\n");
213 * We need to convert spd data to dimm parameters
214 * and to DDR3 EMIF and PHY regirsters values.
215 * For now we just return DIMM type string value.
216 * Caller may use this value to choose appropriate
217 * a pre-set DDR3 configuration
220 strncpy(dimm_name, (char *)&spd_params[0x80], 18);
221 dimm_name[18] = '\0';
226 struct pll_init_data ddr3a_333 = DDR3_PLL_333(A);
227 struct pll_init_data ddr3b_333 = DDR3_PLL_333(B);
228 struct pll_init_data ddr3a_400 = DDR3_PLL_400(A);
229 struct pll_init_data ddr3b_400 = DDR3_PLL_400(B);
235 get_dimm_params(dimm_name);
237 printf("Detected SO-DIMM [%s]\n", dimm_name);
239 if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) {
240 init_pll(&ddr3a_400);
241 if (cpu_revision() > 0) {
242 init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1600_64A);
243 init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_64);
244 printf("DRAM: Capacity 8 GiB (includes reported below)\n");
246 init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1600_32);
247 init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_32);
248 printf("DRAM: Capacity 4 GiB (includes reported below)\n");
250 } else if (!strcmp(dimm_name, "SQR-SD3T-2G1333SED")) {
251 init_pll(&ddr3a_333);
252 if (cpu_revision() > 0) {
253 init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1333_64A);
254 init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, &ddr3_1333_64);
256 init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1333_32);
257 init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, &ddr3_1333_32);
260 printf("Unknown SO-DIMM. Cannot configure DDR3\n");
265 init_pll(&ddr3b_333);
266 init_ddrphy(K2HK_DDR3B_DDRPHYC, &ddr3phy_1333_64);
267 init_ddremif(K2HK_DDR3B_EMIF_CTRL_BASE, &ddr3_1333_64);