3 The J721e family of SoCs are part of K3 Multicore SoC architecture platform
4 targeting automotive applications. They are designed as a low power, high
5 performance and highly integrated device architecture, adding significant
6 enhancement on processing power, graphics capability, video and imaging
7 processing, virtualization and coherent memory support.
9 The device is partitioned into three functional domains, each containing
10 specific processing cores and peripherals:
11 1. Wake-up (WKUP) domain:
12 - Device Management and Security Controller (DMSC)
13 2. Microcontroller (MCU) domain:
14 - Dual Core ARM Cortex-R5F processor
16 - Dual core 64-bit ARM Cortex-A72
17 - 2 x Dual cortex ARM Cortex-R5 subsystem
18 - 2 x C66x Digital signal processor sub system
19 - C71x Digital signal processor sub-system with MMA.
21 More info can be found in TRM: http://www.ti.com/lit/pdf/spruil1
25 Boot flow is similar to that of AM65x SoC and extending it with remoteproc
26 support. Below is the pictorial representation of boot flow:
28 +------------------------------------------------------------------------+-----------------------+
29 | DMSC | MCU R5 | A72 | MAIN R5/C66x/C7x |
30 +------------------------------------------------------------------------+-----------------------+
35 | +--------+ | +-----------+ | | |
36 | | *ROM* |----------|-->| Reset rls | | | |
37 | +--------+ | +-----------+ | | |
40 | |services| | : | | |
41 | | | | +-------------+ | | |
42 | | | | | *R5 ROM* | | | |
43 | | | | +-------------+ | | |
44 | | |<---------|---|Load and auth| | | |
45 | | | | | tiboot3.bin | | | |
46 | | | | +-------------+ | | |
50 | | | | +-------------+ | | |
51 | | | | | *R5 SPL* | | | |
52 | | | | +-------------+ | | |
53 | | | | | Load | | | |
54 | | | | | sysfw.itb | | | |
55 | | Start | | +-------------+ | | |
56 | | System |<---------|---| Start | | | |
57 | |Firmware| | | SYSFW | | | |
58 | +--------+ | +-------------+ | | |
60 | +---------+ | | Load | | | |
61 | | *SYSFW* | | | system | | | |
62 | +---------+ | | Config data | | | |
63 | | |<--------|---| | | | |
64 | | | | +-------------+ | | |
66 | | | | | config | | | |
67 | | | | +-------------+ | | |
68 | | | | | Load | | | |
69 | | | | | tispl.bin | | | |
70 | | | | +-------------+ | | |
71 | | | | | Load R5 | | | |
72 | | | | | firmware | | | |
73 | | | | +-------------+ | | |
74 | | |<--------|---| Start A72 | | | |
75 | | | | | and jump to | | | |
76 | | | | | next image | | | |
77 | | | | +-------------+ | | |
78 | | | | | +-----------+ | |
79 | | |---------|-----------------------|---->| Reset rls | | |
80 | | | | | +-----------+ | |
82 | |Services | | | +-----------+ | |
83 | | |<--------|-----------------------|---->|*ATF/OPTEE*| | |
84 | | | | | +-----------+ | |
86 | | | | | +-----------+ | |
87 | | |<--------|-----------------------|---->| *A72 SPL* | | |
88 | | | | | +-----------+ | |
89 | | | | | | Load | | |
90 | | | | | | u-boot.img| | |
91 | | | | | +-----------+ | |
93 | | | | | +-----------+ | |
94 | | |<--------|-----------------------|---->| *U-Boot* | | |
95 | | | | | +-----------+ | |
96 | | | | | | prompt | | |
97 | | | | | +-----------+ | |
98 | | | | | | Load R5 | | |
99 | | | | | | Firmware | | |
100 | | | | | +-----------+ | |
101 | | |<--------|-----------------------|-----| Start R5 | | +-----------+ |
102 | | |---------|-----------------------|-----+-----------+-----|----->| R5 starts | |
103 | | | | | | Load C6 | | +-----------+ |
104 | | | | | | Firmware | | |
105 | | | | | +-----------+ | |
106 | | |<--------|-----------------------|-----| Start C6 | | +-----------+ |
107 | | |---------|-----------------------|-----+-----------+-----|----->| C6 starts | |
108 | | | | | | Load C7 | | +-----------+ |
109 | | | | | | Firmware | | |
110 | | | | | +-----------+ | |
111 | | |<--------|-----------------------|-----| Start C7 | | +-----------+ |
112 | | |---------|-----------------------|-----+-----------+-----|----->| C7 starts | |
113 | +---------+ | | | +-----------+ |
115 +------------------------------------------------------------------------+-----------------------+
117 - Here DMSC acts as master and provides all the critical services. R5/A72
118 requests DMSC to get these services done as shown in the above diagram.
123 Tree: git://git.ti.com/processor-firmware/system-firmware-image-gen.git
127 Tree: https://github.com/ARM-software/arm-trusted-firmware.git
131 Tree: https://github.com/OP-TEE/optee_os.git
135 Tree: https://gitlab.denx.de/u-boot/u-boot
141 $ make CROSS_COMPILE=arm-linux-gnueabihf-
144 $ make CROSS_COMPILE=aarch64-linux-gnu- ARCH=aarch64 PLAT=k3 TARGET_BOARD=generic SPD=opteed
147 $ make PLATFORM=k3-j721e CFG_ARM64_core=y
152 $ make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- j721e_evm_r5_defconfig O=/tmp/r5
153 $ make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- O=/tmp/r5
156 $ make ARCH=arm CROSS_COMPILE=aarch64-linux-gnu- j721e_evm_a72_defconfig O=/tmp/a72
157 $ make ARCH=arm CROSS_COMPILE=aarch64-linux-gnu- ATF=<path to ATF dir>/build/k3/generic/release/bl31.bin TEE=<path to OPTEE OS dir>/out/arm-plat-k3/core/tee-pager.bin O=/tmp/a72
161 Copy the below images to an SD card and boot:
162 - sysfw.itb from step 1
163 - tiboot3.bin from step 4.1
164 - tispl.bin, u-boot.img from 4.2
170 +-----------------------+
173 | +-------------------+ |
176 | | u-boot-spl.bin | |
178 | +-------------------+ |
181 | | +---------------+ | |
183 | | | DTB 1...N | | |
184 | | +---------------+ | |
185 | +-------------------+ |
186 +-----------------------+
189 +-----------------------+
192 | +-------------------+ |
195 | +-------------------+ |
198 | +-------------------+ |
201 | +-------------------+ |
203 | | SPL DTB 1...N | |
204 | +-------------------+ |
205 +-----------------------+
208 +-----------------------+
211 | +-------------------+ |
214 | +-------------------+ |
217 | +-------------------+ |
220 | +-------------------+ |
223 | +-------------------+ |
225 | | Secure config | |
226 | +-------------------+ |
227 +-----------------------+