2 * (C) Copyright 2004-2008
3 * Texas Instruments, <www.ti.com>
6 * Manikandan Pillai <mani.pillai@ti.com>
8 * Derived from Beagle Board and 3430 SDP code by
9 * Richard Woodruff <r-woodruff2@ti.com>
10 * Syed Mohammed Khasim <khasim@ti.com>
12 * See file CREDITS for list of people who contributed to this
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 #include <asm/arch/mem.h>
34 #include <asm/arch/mux.h>
35 #include <asm/arch/sys_proto.h>
37 #include <asm/mach-types.h>
40 static u8 omap3_evm_version;
42 u8 get_omap3_evm_rev(void)
44 return omap3_evm_version;
47 static void omap3_evm_get_revision(void)
51 /* Ethernet PHY ID is stored at ID_REV register */
52 smsc_id = readl(CONFIG_SMC911X_BASE + 0x50) & 0xFFFF0000;
53 printf("Read back SMSC id 0x%x\n", smsc_id);
56 /* SMSC9115 chipset */
58 omap3_evm_version = OMAP3EVM_BOARD_GEN_1;
60 /* SMSC 9220 chipset */
63 omap3_evm_version = OMAP3EVM_BOARD_GEN_2;
69 * Description: Early hardware init.
73 DECLARE_GLOBAL_DATA_PTR;
75 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
76 /* board id for Linux */
77 gd->bd->bi_arch_number = MACH_TYPE_OMAP3EVM;
79 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
85 * Routine: misc_init_r
86 * Description: Init ethernet (done here so udelay works)
91 #ifdef CONFIG_DRIVER_OMAP34XX_I2C
92 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
95 #if defined(CONFIG_CMD_NET)
105 * Routine: set_muxconf_regs
106 * Description: Setting up the configuration Mux registers specific to the
107 * hardware. Many pins need to be moved from protect to primary
110 void set_muxconf_regs(void)
116 * Routine: setup_net_chip
117 * Description: Setting up the configuration GPMC registers specific to the
120 static void setup_net_chip(void)
122 struct gpio *gpio3_base = (struct gpio *)OMAP34XX_GPIO3_BASE;
123 struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
125 /* Configure GPMC registers */
126 writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[5].config1);
127 writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[5].config2);
128 writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[5].config3);
129 writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[5].config4);
130 writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[5].config5);
131 writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[5].config6);
132 writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[5].config7);
134 /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
135 writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
136 /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
137 writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
138 /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
139 writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
140 &ctrl_base->gpmc_nadv_ale);
142 /* Make GPIO 64 as output pin */
143 writel(readl(&gpio3_base->oe) & ~(GPIO0), &gpio3_base->oe);
145 /* Now send a pulse on the GPIO pin */
146 writel(GPIO0, &gpio3_base->setdataout);
148 writel(GPIO0, &gpio3_base->cleardataout);
150 writel(GPIO0, &gpio3_base->setdataout);
152 /* determine omap3evm revision */
153 omap3_evm_get_revision();
156 int board_eth_init(bd_t *bis)
159 #ifdef CONFIG_SMC911X
160 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);