board/ti/dra7xx/evm.c

   1 /*
   2  * (C) Copyright 2013
   3  * Texas Instruments Incorporated, <www.ti.com>
   4  *
   5  * Lokesh Vutla <lokeshvutla@ti.com>
   6  *
   7  * Based on previous work by:
   8  * Aneesh V       <aneesh@ti.com>
   9  * Steve Sakoman  <steve@sakoman.com>
  10  *
  11  * SPDX-License-Identifier:     GPL-2.0+
  12  */
  13 #include <common.h>
  14 #include <palmas.h>
  15 #include <sata.h>
  16 #include <linux/string.h>
  17 #include <asm/gpio.h>
  18 #include <usb.h>
  19 #include <linux/usb/gadget.h>
  20 #include <asm/arch/gpio.h>
  21 #include <asm/arch/dra7xx_iodelay.h>
  22 #include <asm/emif.h>
  23 #include <asm/arch/sys_proto.h>
  24 #include <asm/arch/mmc_host_def.h>
  25 #include <asm/arch/sata.h>
  26 #include <environment.h>
  27 #include <dwc3-uboot.h>
  28 #include <dwc3-omap-uboot.h>
  29 #include <ti-usb-phy-uboot.h>
  30
  31 #include "mux_data.h"
  32 #include "../common/board_detect.h"
  33
  34 #define board_is_dra74x_evm()           board_ti_is("5777xCPU")
  35 #define board_is_dra74x_revh_or_later() board_is_dra74x_evm() &&        \
  36                                 (strncmp("H", board_ti_get_rev(), 1) <= 0)
  37
  38 #ifdef CONFIG_DRIVER_TI_CPSW
  39 #include <cpsw.h>
  40 #endif
  41
  42 DECLARE_GLOBAL_DATA_PTR;
  43
  44 /* GPIO 7_11 */
  45 #define GPIO_DDR_VTT_EN 203
  46
  47 #define SYSINFO_BOARD_NAME_MAX_LEN      37
  48
  49 const struct omap_sysinfo sysinfo = {
  50         "Board: UNKNOWN(DRA7 EVM) REV UNKNOWN\n"
  51 };
  52
  53 static const struct emif_regs emif1_ddr3_532_mhz_1cs = {
  54         .sdram_config_init              = 0x61851ab2,
  55         .sdram_config                   = 0x61851ab2,
  56         .sdram_config2                  = 0x08000000,
  57         .ref_ctrl                       = 0x000040F1,
  58         .ref_ctrl_final                 = 0x00001035,
  59         .sdram_tim1                     = 0xCCCF36B3,
  60         .sdram_tim2                     = 0x308F7FDA,
  61         .sdram_tim3                     = 0x427F88A8,
  62         .read_idle_ctrl                 = 0x00050000,
  63         .zq_config                      = 0x0007190B,
  64         .temp_alert_config              = 0x00000000,
  65         .emif_ddr_phy_ctlr_1_init       = 0x0024400B,
  66         .emif_ddr_phy_ctlr_1            = 0x0E24400B,
  67         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
  68         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
  69         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
  70         .emif_ddr_ext_phy_ctrl_4        = 0x009B009B,
  71         .emif_ddr_ext_phy_ctrl_5        = 0x009E009E,
  72         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
  73         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
  74         .emif_rd_wr_lvl_ctl             = 0x00000000,
  75         .emif_rd_wr_exec_thresh         = 0x00000305
  76 };
  77
  78 static const struct emif_regs emif2_ddr3_532_mhz_1cs = {
  79         .sdram_config_init              = 0x61851B32,
  80         .sdram_config                   = 0x61851B32,
  81         .sdram_config2                  = 0x08000000,
  82         .ref_ctrl                       = 0x000040F1,
  83         .ref_ctrl_final                 = 0x00001035,
  84         .sdram_tim1                     = 0xCCCF36B3,
  85         .sdram_tim2                     = 0x308F7FDA,
  86         .sdram_tim3                     = 0x427F88A8,
  87         .read_idle_ctrl                 = 0x00050000,
  88         .zq_config                      = 0x0007190B,
  89         .temp_alert_config              = 0x00000000,
  90         .emif_ddr_phy_ctlr_1_init       = 0x0024400B,
  91         .emif_ddr_phy_ctlr_1            = 0x0E24400B,
  92         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
  93         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
  94         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
  95         .emif_ddr_ext_phy_ctrl_4        = 0x009B009B,
  96         .emif_ddr_ext_phy_ctrl_5        = 0x009E009E,
  97         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
  98         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
  99         .emif_rd_wr_lvl_ctl             = 0x00000000,
 100         .emif_rd_wr_exec_thresh         = 0x00000305
 101 };
 102
 103 static const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
 104         .sdram_config_init              = 0x61862B32,
 105         .sdram_config                   = 0x61862B32,
 106         .sdram_config2                  = 0x08000000,
 107         .ref_ctrl                       = 0x0000514C,
 108         .ref_ctrl_final                 = 0x0000144A,
 109         .sdram_tim1                     = 0xD113781C,
 110         .sdram_tim2                     = 0x30717FE3,
 111         .sdram_tim3                     = 0x409F86A8,
 112         .read_idle_ctrl                 = 0x00050000,
 113         .zq_config                      = 0x5007190B,
 114         .temp_alert_config              = 0x00000000,
 115         .emif_ddr_phy_ctlr_1_init       = 0x0024400D,
 116         .emif_ddr_phy_ctlr_1            = 0x0E24400D,
 117         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 118         .emif_ddr_ext_phy_ctrl_2        = 0x00A400A4,
 119         .emif_ddr_ext_phy_ctrl_3        = 0x00A900A9,
 120         .emif_ddr_ext_phy_ctrl_4        = 0x00B000B0,
 121         .emif_ddr_ext_phy_ctrl_5        = 0x00B000B0,
 122         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 123         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 124         .emif_rd_wr_lvl_ctl             = 0x00000000,
 125         .emif_rd_wr_exec_thresh         = 0x00000305
 126 };
 127
 128 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 129 {
 130         switch (omap_revision()) {
 131         case DRA752_ES1_0:
 132         case DRA752_ES1_1:
 133         case DRA752_ES2_0:
 134                 switch (emif_nr) {
 135                 case 1:
 136                         *regs = &emif1_ddr3_532_mhz_1cs;
 137                         break;
 138                 case 2:
 139                         *regs = &emif2_ddr3_532_mhz_1cs;
 140                         break;
 141                 }
 142                 break;
 143         case DRA722_ES1_0:
 144                 *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1;
 145                 break;
 146         default:
 147                 *regs = &emif1_ddr3_532_mhz_1cs;
 148         }
 149 }
 150
 151 static const struct dmm_lisa_map_regs lisa_map_dra7_1536MB = {
 152         .dmm_lisa_map_0 = 0x0,
 153         .dmm_lisa_map_1 = 0x80640300,
 154         .dmm_lisa_map_2 = 0xC0500220,
 155         .dmm_lisa_map_3 = 0xFF020100,
 156         .is_ma_present  = 0x1
 157 };
 158
 159 static const struct dmm_lisa_map_regs lisa_map_2G_x_2 = {
 160         .dmm_lisa_map_0 = 0x0,
 161         .dmm_lisa_map_1 = 0x0,
 162         .dmm_lisa_map_2 = 0x80600100,
 163         .dmm_lisa_map_3 = 0xFF020100,
 164         .is_ma_present  = 0x1
 165 };
 166
 167 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
 168 {
 169         switch (omap_revision()) {
 170         case DRA752_ES1_0:
 171         case DRA752_ES1_1:
 172         case DRA752_ES2_0:
 173                 *dmm_lisa_regs = &lisa_map_dra7_1536MB;
 174                 break;
 175         case DRA722_ES1_0:
 176         default:
 177                 *dmm_lisa_regs = &lisa_map_2G_x_2;
 178         }
 179 }
 180
 181 /**
 182  * @brief board_init
 183  *
 184  * @return 0
 185  */
 186 int board_init(void)
 187 {
 188         gpmc_init();
 189         gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
 190
 191         return 0;
 192 }
 193
 194 int board_late_init(void)
 195 {
 196 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 197         char *name = "unknown";
 198
 199         if (is_dra72x())
 200                 name = "dra72x";
 201         else
 202                 name = "dra7xx";
 203
 204         set_board_info_env(name);
 205
 206         omap_die_id_serial();
 207 #endif
 208         return 0;
 209 }
 210
 211 #ifdef CONFIG_SPL_BUILD
 212 void do_board_detect(void)
 213 {
 214         int rc;
 215
 216         rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
 217                                     CONFIG_EEPROM_CHIP_ADDRESS);
 218         if (rc)
 219                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 220 }
 221
 222 #else
 223
 224 void do_board_detect(void)
 225 {
 226         char *bname = NULL;
 227         int rc;
 228
 229         rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
 230                                     CONFIG_EEPROM_CHIP_ADDRESS);
 231         if (rc)
 232                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 233
 234         if (board_is_dra74x_evm()) {
 235                 bname = "DRA74x EVM";
 236         /* If EEPROM is not populated */
 237         } else {
 238                 if (is_dra72x())
 239                         bname = "DRA72x EVM";
 240                 else
 241                         bname = "DRA74x EVM";
 242         }
 243
 244         if (bname)
 245                 snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
 246                          "Board: %s REV %s\n", bname, board_ti_get_rev());
 247 }
 248 #endif  /* CONFIG_SPL_BUILD */
 249
 250 void set_muxconf_regs_essential(void)
 251 {
 252         do_set_mux32((*ctrl)->control_padconf_core_base,
 253                      early_padconf, ARRAY_SIZE(early_padconf));
 254 }
 255
 256 #ifdef CONFIG_IODELAY_RECALIBRATION
 257 void recalibrate_iodelay(void)
 258 {
 259         struct pad_conf_entry const *pads;
 260         struct iodelay_cfg_entry const *iodelay;
 261         int npads, niodelays;
 262
 263         switch (omap_revision()) {
 264         case DRA722_ES1_0:
 265                 pads = core_padconf_array_essential;
 266                 npads = ARRAY_SIZE(core_padconf_array_essential);
 267                 iodelay = iodelay_cfg_array;
 268                 niodelays = ARRAY_SIZE(iodelay_cfg_array);
 269                 break;
 270         case DRA752_ES1_0:
 271         case DRA752_ES1_1:
 272                 pads = dra74x_core_padconf_array;
 273                 npads = ARRAY_SIZE(dra74x_core_padconf_array);
 274                 iodelay = dra742_es1_1_iodelay_cfg_array;
 275                 niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array);
 276                 break;
 277         default:
 278         case DRA752_ES2_0:
 279                 pads = dra74x_core_padconf_array;
 280                 npads = ARRAY_SIZE(dra74x_core_padconf_array);
 281                 iodelay = dra742_es2_0_iodelay_cfg_array;
 282                 niodelays = ARRAY_SIZE(dra742_es2_0_iodelay_cfg_array);
 283                 /* Setup port1 and port2 for rgmii with 'no-id' mode */
 284                 clrset_spare_register(1, 0, RGMII2_ID_MODE_N_MASK |
 285                                       RGMII1_ID_MODE_N_MASK);
 286                 break;
 287         }
 288         __recalibrate_iodelay(pads, npads, iodelay, niodelays);
 289 }
 290 #endif
 291
 292 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
 293 int board_mmc_init(bd_t *bis)
 294 {
 295         omap_mmc_init(0, 0, 0, -1, -1);
 296         omap_mmc_init(1, 0, 0, -1, -1);
 297         return 0;
 298 }
 299 #endif
 300
 301 #ifdef CONFIG_USB_DWC3
 302 static struct dwc3_device usb_otg_ss1 = {
 303         .maximum_speed = USB_SPEED_SUPER,
 304         .base = DRA7_USB_OTG_SS1_BASE,
 305         .tx_fifo_resize = false,
 306         .index = 0,
 307 };
 308
 309 static struct dwc3_omap_device usb_otg_ss1_glue = {
 310         .base = (void *)DRA7_USB_OTG_SS1_GLUE_BASE,
 311         .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
 312         .index = 0,
 313 };
 314
 315 static struct ti_usb_phy_device usb_phy1_device = {
 316         .pll_ctrl_base = (void *)DRA7_USB3_PHY1_PLL_CTRL,
 317         .usb2_phy_power = (void *)DRA7_USB2_PHY1_POWER,
 318         .usb3_phy_power = (void *)DRA7_USB3_PHY1_POWER,
 319         .index = 0,
 320 };
 321
 322 static struct dwc3_device usb_otg_ss2 = {
 323         .maximum_speed = USB_SPEED_SUPER,
 324         .base = DRA7_USB_OTG_SS2_BASE,
 325         .tx_fifo_resize = false,
 326         .index = 1,
 327 };
 328
 329 static struct dwc3_omap_device usb_otg_ss2_glue = {
 330         .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE,
 331         .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
 332         .index = 1,
 333 };
 334
 335 static struct ti_usb_phy_device usb_phy2_device = {
 336         .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER,
 337         .index = 1,
 338 };
 339
 340 int board_usb_init(int index, enum usb_init_type init)
 341 {
 342         enable_usb_clocks(index);
 343         switch (index) {
 344         case 0:
 345                 if (init == USB_INIT_DEVICE) {
 346                         usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
 347                         usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
 348                 } else {
 349                         usb_otg_ss1.dr_mode = USB_DR_MODE_HOST;
 350                         usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
 351                 }
 352
 353                 ti_usb_phy_uboot_init(&usb_phy1_device);
 354                 dwc3_omap_uboot_init(&usb_otg_ss1_glue);
 355                 dwc3_uboot_init(&usb_otg_ss1);
 356                 break;
 357         case 1:
 358                 if (init == USB_INIT_DEVICE) {
 359                         usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
 360                         usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
 361                 } else {
 362                         usb_otg_ss2.dr_mode = USB_DR_MODE_HOST;
 363                         usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
 364                 }
 365
 366                 ti_usb_phy_uboot_init(&usb_phy2_device);
 367                 dwc3_omap_uboot_init(&usb_otg_ss2_glue);
 368                 dwc3_uboot_init(&usb_otg_ss2);
 369                 break;
 370         default:
 371                 printf("Invalid Controller Index\n");
 372         }
 373
 374         return 0;
 375 }
 376
 377 int board_usb_cleanup(int index, enum usb_init_type init)
 378 {
 379         switch (index) {
 380         case 0:
 381         case 1:
 382                 ti_usb_phy_uboot_exit(index);
 383                 dwc3_uboot_exit(index);
 384                 dwc3_omap_uboot_exit(index);
 385                 break;
 386         default:
 387                 printf("Invalid Controller Index\n");
 388         }
 389         disable_usb_clocks(index);
 390         return 0;
 391 }
 392
 393 int usb_gadget_handle_interrupts(int index)
 394 {
 395         u32 status;
 396
 397         status = dwc3_omap_uboot_interrupt_status(index);
 398         if (status)
 399                 dwc3_uboot_handle_interrupt(index);
 400
 401         return 0;
 402 }
 403 #endif
 404
 405 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
 406 int spl_start_uboot(void)
 407 {
 408         /* break into full u-boot on 'c' */
 409         if (serial_tstc() && serial_getc() == 'c')
 410                 return 1;
 411
 412 #ifdef CONFIG_SPL_ENV_SUPPORT
 413         env_init();
 414         env_relocate_spec();
 415         if (getenv_yesno("boot_os") != 1)
 416                 return 1;
 417 #endif
 418
 419         return 0;
 420 }
 421 #endif
 422
 423 #ifdef CONFIG_DRIVER_TI_CPSW
 424 extern u32 *const omap_si_rev;
 425
 426 static void cpsw_control(int enabled)
 427 {
 428         /* VTP can be added here */
 429
 430         return;
 431 }
 432
 433 static struct cpsw_slave_data cpsw_slaves[] = {
 434         {
 435                 .slave_reg_ofs  = 0x208,
 436                 .sliver_reg_ofs = 0xd80,
 437                 .phy_addr       = 2,
 438         },
 439         {
 440                 .slave_reg_ofs  = 0x308,
 441                 .sliver_reg_ofs = 0xdc0,
 442                 .phy_addr       = 3,
 443         },
 444 };
 445
 446 static struct cpsw_platform_data cpsw_data = {
 447         .mdio_base              = CPSW_MDIO_BASE,
 448         .cpsw_base              = CPSW_BASE,
 449         .mdio_div               = 0xff,
 450         .channels               = 8,
 451         .cpdma_reg_ofs          = 0x800,
 452         .slaves                 = 2,
 453         .slave_data             = cpsw_slaves,
 454         .ale_reg_ofs            = 0xd00,
 455         .ale_entries            = 1024,
 456         .host_port_reg_ofs      = 0x108,
 457         .hw_stats_reg_ofs       = 0x900,
 458         .bd_ram_ofs             = 0x2000,
 459         .mac_control            = (1 << 5),
 460         .control                = cpsw_control,
 461         .host_port_num          = 0,
 462         .version                = CPSW_CTRL_VERSION_2,
 463 };
 464
 465 int board_eth_init(bd_t *bis)
 466 {
 467         int ret;
 468         uint8_t mac_addr[6];
 469         uint32_t mac_hi, mac_lo;
 470         uint32_t ctrl_val;
 471
 472         /* try reading mac address from efuse */
 473         mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
 474         mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
 475         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
 476         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 477         mac_addr[2] = mac_hi & 0xFF;
 478         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
 479         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
 480         mac_addr[5] = mac_lo & 0xFF;
 481
 482         if (!getenv("ethaddr")) {
 483                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
 484
 485                 if (is_valid_ethaddr(mac_addr))
 486                         eth_setenv_enetaddr("ethaddr", mac_addr);
 487         }
 488
 489         mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
 490         mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
 491         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
 492         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 493         mac_addr[2] = mac_hi & 0xFF;
 494         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
 495         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
 496         mac_addr[5] = mac_lo & 0xFF;
 497
 498         if (!getenv("eth1addr")) {
 499                 if (is_valid_ethaddr(mac_addr))
 500                         eth_setenv_enetaddr("eth1addr", mac_addr);
 501         }
 502
 503         ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
 504         ctrl_val |= 0x22;
 505         writel(ctrl_val, (*ctrl)->control_core_control_io1);
 506
 507         if (*omap_si_rev == DRA722_ES1_0)
 508                 cpsw_data.active_slave = 1;
 509
 510         ret = cpsw_register(&cpsw_data);
 511         if (ret < 0)
 512                 printf("Error %d registering CPSW switch\n", ret);
 513
 514         return ret;
 515 }
 516 #endif
 517
 518 #ifdef CONFIG_BOARD_EARLY_INIT_F
 519 /* VTT regulator enable */
 520 static inline void vtt_regulator_enable(void)
 521 {
 522         if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
 523                 return;
 524
 525         /* Do not enable VTT for DRA722 */
 526         if (omap_revision() == DRA722_ES1_0)
 527                 return;
 528
 529         /*
 530          * EVM Rev G and later use gpio7_11 for DDR3 termination.
 531          * This is safe enough to do on older revs.
 532          */
 533         gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
 534         gpio_direction_output(GPIO_DDR_VTT_EN, 1);
 535 }
 536
 537 int board_early_init_f(void)
 538 {
 539         vtt_regulator_enable();
 540         return 0;
 541 }
 542 #endif