3 * Texas Instruments Incorporated, <www.ti.com>
5 * Lokesh Vutla <lokeshvutla@ti.com>
7 * Based on previous work by:
8 * Aneesh V <aneesh@ti.com>
9 * Steve Sakoman <steve@sakoman.com>
11 * SPDX-License-Identifier: GPL-2.0+
18 #include <linux/usb/gadget.h>
19 #include <asm/arch/gpio.h>
20 #include <asm/arch/dra7xx_iodelay.h>
21 #include <asm/arch/sys_proto.h>
22 #include <asm/arch/mmc_host_def.h>
23 #include <asm/arch/sata.h>
24 #include <environment.h>
25 #include <dwc3-uboot.h>
26 #include <dwc3-omap-uboot.h>
27 #include <ti-usb-phy-uboot.h>
31 #ifdef CONFIG_DRIVER_TI_CPSW
35 DECLARE_GLOBAL_DATA_PTR;
38 #define GPIO_DDR_VTT_EN 203
40 const struct omap_sysinfo sysinfo = {
45 * Adjust I/O delays on the Tx control and data lines of each MAC port. This
46 * is a workaround in order to work properly with the DP83865 PHYs on the EVM.
47 * In 3COM RGMII mode this PHY applies it's own internal clock delay, so we
48 * essentially need to counteract the DRA7xx internal delay, and we do this
49 * by delaying the control and data lines. If not using this PHY, you probably
50 * don't need to do this stuff!
52 static void dra7xx_adj_io_delay(const struct io_delay *io_dly)
60 writel(CFG_IO_DELAY_UNLOCK_KEY, CFG_IO_DELAY_LOCK);
62 while(io_dly[i].addr) {
63 writel(CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK,
65 delta = io_dly[i].dly;
66 reg_val = readl(io_dly[i].addr) & 0x3ff;
67 coarse = ((reg_val >> 5) & 0x1F) + ((delta >> 5) & 0x1F);
68 coarse = (coarse > 0x1F) ? (0x1F) : (coarse);
69 fine = (reg_val & 0x1F) + (delta & 0x1F);
70 fine = (fine > 0x1F) ? (0x1F) : (fine);
71 reg_val = CFG_IO_DELAY_ACCESS_PATTERN |
72 CFG_IO_DELAY_LOCK_MASK |
73 ((coarse << 5) | (fine));
74 writel(reg_val, io_dly[i].addr);
78 writel(CFG_IO_DELAY_LOCK_KEY, CFG_IO_DELAY_LOCK);
89 gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
94 int board_late_init(void)
96 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
99 if (omap_revision() == DRA722_ES1_0)
100 setenv("board_name", "dra72x");
102 setenv("board_name", "dra7xx");
104 id[0] = readl((*ctrl)->control_std_fuse_die_id_0);
105 id[1] = readl((*ctrl)->control_std_fuse_die_id_1);
106 usb_set_serial_num_from_die_id(id);
111 void set_muxconf_regs_essential(void)
113 do_set_mux32((*ctrl)->control_padconf_core_base,
114 early_padconf, ARRAY_SIZE(early_padconf));
117 #ifdef CONFIG_IODELAY_RECALIBRATION
118 void recalibrate_iodelay(void)
121 __recalibrate_iodelay(core_padconf_array_essential,
122 ARRAY_SIZE(core_padconf_array_essential),
124 ARRAY_SIZE(iodelay_cfg_array));
126 __recalibrate_iodelay(dra74x_core_padconf_array,
127 ARRAY_SIZE(dra74x_core_padconf_array),
128 dra742_iodelay_cfg_array,
129 ARRAY_SIZE(dra742_iodelay_cfg_array));
134 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
135 int board_mmc_init(bd_t *bis)
137 omap_mmc_init(0, 0, 0, -1, -1);
138 omap_mmc_init(1, 0, 0, -1, -1);
143 #ifdef CONFIG_USB_DWC3
144 static struct dwc3_device usb_otg_ss1 = {
145 .maximum_speed = USB_SPEED_SUPER,
146 .base = DRA7_USB_OTG_SS1_BASE,
147 .tx_fifo_resize = false,
151 static struct dwc3_omap_device usb_otg_ss1_glue = {
152 .base = (void *)DRA7_USB_OTG_SS1_GLUE_BASE,
153 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
154 .vbus_id_status = OMAP_DWC3_VBUS_VALID,
158 static struct ti_usb_phy_device usb_phy1_device = {
159 .pll_ctrl_base = (void *)DRA7_USB3_PHY1_PLL_CTRL,
160 .usb2_phy_power = (void *)DRA7_USB2_PHY1_POWER,
161 .usb3_phy_power = (void *)DRA7_USB3_PHY1_POWER,
165 static struct dwc3_device usb_otg_ss2 = {
166 .maximum_speed = USB_SPEED_SUPER,
167 .base = DRA7_USB_OTG_SS2_BASE,
168 .tx_fifo_resize = false,
172 static struct dwc3_omap_device usb_otg_ss2_glue = {
173 .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE,
174 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
175 .vbus_id_status = OMAP_DWC3_VBUS_VALID,
179 static struct ti_usb_phy_device usb_phy2_device = {
180 .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER,
184 int board_usb_init(int index, enum usb_init_type init)
188 if (init == USB_INIT_DEVICE) {
189 usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
190 usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
192 usb_otg_ss1.dr_mode = USB_DR_MODE_HOST;
193 usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
196 ti_usb_phy_uboot_init(&usb_phy1_device);
197 dwc3_omap_uboot_init(&usb_otg_ss1_glue);
198 dwc3_uboot_init(&usb_otg_ss1);
201 if (init == USB_INIT_DEVICE) {
202 usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
203 usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
205 usb_otg_ss2.dr_mode = USB_DR_MODE_HOST;
206 usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
209 ti_usb_phy_uboot_init(&usb_phy2_device);
210 dwc3_omap_uboot_init(&usb_otg_ss2_glue);
211 dwc3_uboot_init(&usb_otg_ss2);
214 printf("Invalid Controller Index\n");
220 int board_usb_cleanup(int index, enum usb_init_type init)
225 ti_usb_phy_uboot_exit(index);
226 dwc3_uboot_exit(index);
227 dwc3_omap_uboot_exit(index);
230 printf("Invalid Controller Index\n");
235 int usb_gadget_handle_interrupts(int index)
239 status = dwc3_omap_uboot_interrupt_status(index);
241 dwc3_uboot_handle_interrupt(index);
247 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
248 int spl_start_uboot(void)
250 /* break into full u-boot on 'c' */
251 if (serial_tstc() && serial_getc() == 'c')
254 #ifdef CONFIG_SPL_ENV_SUPPORT
257 if (getenv_yesno("boot_os") != 1)
265 #ifdef CONFIG_DRIVER_TI_CPSW
267 /* Delay value to add to calibrated value */
268 #define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8)
269 #define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8)
270 #define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2)
271 #define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0)
272 #define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0)
273 #define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8)
274 #define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8)
275 #define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2)
276 #define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0)
277 #define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0)
279 extern u32 *const omap_si_rev;
281 static void cpsw_control(int enabled)
283 /* VTP can be added here */
288 static struct cpsw_slave_data cpsw_slaves[] = {
290 .slave_reg_ofs = 0x208,
291 .sliver_reg_ofs = 0xd80,
295 .slave_reg_ofs = 0x308,
296 .sliver_reg_ofs = 0xdc0,
301 static struct cpsw_platform_data cpsw_data = {
302 .mdio_base = CPSW_MDIO_BASE,
303 .cpsw_base = CPSW_BASE,
306 .cpdma_reg_ofs = 0x800,
308 .slave_data = cpsw_slaves,
309 .ale_reg_ofs = 0xd00,
311 .host_port_reg_ofs = 0x108,
312 .hw_stats_reg_ofs = 0x900,
313 .bd_ram_ofs = 0x2000,
314 .mac_control = (1 << 5),
315 .control = cpsw_control,
317 .version = CPSW_CTRL_VERSION_2,
320 int board_eth_init(bd_t *bis)
324 uint32_t mac_hi, mac_lo;
326 const struct io_delay io_dly[] = {
327 {CFG_RGMII0_TXCTL, RGMII0_TXCTL_DLY_VAL},
328 {CFG_RGMII0_TXD0, RGMII0_TXD0_DLY_VAL},
329 {CFG_RGMII0_TXD1, RGMII0_TXD1_DLY_VAL},
330 {CFG_RGMII0_TXD2, RGMII0_TXD2_DLY_VAL},
331 {CFG_RGMII0_TXD3, RGMII0_TXD3_DLY_VAL},
332 {CFG_VIN2A_D13, VIN2A_D13_DLY_VAL},
333 {CFG_VIN2A_D17, VIN2A_D17_DLY_VAL},
334 {CFG_VIN2A_D16, VIN2A_D16_DLY_VAL},
335 {CFG_VIN2A_D15, VIN2A_D15_DLY_VAL},
336 {CFG_VIN2A_D14, VIN2A_D14_DLY_VAL},
340 /* Adjust IO delay for RGMII tx path */
341 dra7xx_adj_io_delay(io_dly);
343 /* try reading mac address from efuse */
344 mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
345 mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
346 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
347 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
348 mac_addr[2] = mac_hi & 0xFF;
349 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
350 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
351 mac_addr[5] = mac_lo & 0xFF;
353 if (!getenv("ethaddr")) {
354 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
356 if (is_valid_ethaddr(mac_addr))
357 eth_setenv_enetaddr("ethaddr", mac_addr);
360 mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
361 mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
362 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
363 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
364 mac_addr[2] = mac_hi & 0xFF;
365 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
366 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
367 mac_addr[5] = mac_lo & 0xFF;
369 if (!getenv("eth1addr")) {
370 if (is_valid_ethaddr(mac_addr))
371 eth_setenv_enetaddr("eth1addr", mac_addr);
374 ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
376 writel(ctrl_val, (*ctrl)->control_core_control_io1);
378 if (*omap_si_rev == DRA722_ES1_0)
379 cpsw_data.active_slave = 1;
381 ret = cpsw_register(&cpsw_data);
383 printf("Error %d registering CPSW switch\n", ret);
389 #ifdef CONFIG_BOARD_EARLY_INIT_F
390 /* VTT regulator enable */
391 static inline void vtt_regulator_enable(void)
393 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
396 /* Do not enable VTT for DRA722 */
397 if (omap_revision() == DRA722_ES1_0)
401 * EVM Rev G and later use gpio7_11 for DDR3 termination.
402 * This is safe enough to do on older revs.
404 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
405 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
408 int board_early_init_f(void)
410 vtt_regulator_enable();