board/ti/dra7xx/evm.c

   1 /*
   2  * (C) Copyright 2013
   3  * Texas Instruments Incorporated, <www.ti.com>
   4  *
   5  * Lokesh Vutla <lokeshvutla@ti.com>
   6  *
   7  * Based on previous work by:
   8  * Aneesh V       <aneesh@ti.com>
   9  * Steve Sakoman  <steve@sakoman.com>
  10  *
  11  * SPDX-License-Identifier:     GPL-2.0+
  12  */
  13 #include <common.h>
  14 #include <palmas.h>
  15 #include <sata.h>
  16 #include <linux/string.h>
  17 #include <asm/gpio.h>
  18 #include <usb.h>
  19 #include <linux/usb/gadget.h>
  20 #include <asm/arch/gpio.h>
  21 #include <asm/arch/dra7xx_iodelay.h>
  22 #include <asm/emif.h>
  23 #include <asm/arch/sys_proto.h>
  24 #include <asm/arch/mmc_host_def.h>
  25 #include <asm/arch/sata.h>
  26 #include <environment.h>
  27 #include <dwc3-uboot.h>
  28 #include <dwc3-omap-uboot.h>
  29 #include <ti-usb-phy-uboot.h>
  30
  31 #include "mux_data.h"
  32 #include "../common/board_detect.h"
  33
  34 #define board_is_dra74x_evm()           board_ti_is("5777xCPU")
  35 #define board_is_dra72x_evm()           board_ti_is("DRA72x-T")
  36 #define board_is_dra74x_revh_or_later() board_is_dra74x_evm() &&        \
  37                                 (strncmp("H", board_ti_get_rev(), 1) <= 0)
  38 #define board_is_dra72x_revc_or_later() board_is_dra72x_evm() &&        \
  39                                 (strncmp("C", board_ti_get_rev(), 1) <= 0)
  40 #define board_ti_get_emif_size()        board_ti_get_emif1_size() +     \
  41                                         board_ti_get_emif2_size()
  42
  43 #ifdef CONFIG_DRIVER_TI_CPSW
  44 #include <cpsw.h>
  45 #endif
  46
  47 DECLARE_GLOBAL_DATA_PTR;
  48
  49 /* GPIO 7_11 */
  50 #define GPIO_DDR_VTT_EN 203
  51
  52 #define SYSINFO_BOARD_NAME_MAX_LEN      37
  53
  54 const struct omap_sysinfo sysinfo = {
  55         "Board: UNKNOWN(DRA7 EVM) REV UNKNOWN\n"
  56 };
  57
  58 static const struct emif_regs emif1_ddr3_532_mhz_1cs = {
  59         .sdram_config_init              = 0x61851ab2,
  60         .sdram_config                   = 0x61851ab2,
  61         .sdram_config2                  = 0x08000000,
  62         .ref_ctrl                       = 0x000040F1,
  63         .ref_ctrl_final                 = 0x00001035,
  64         .sdram_tim1                     = 0xCCCF36B3,
  65         .sdram_tim2                     = 0x308F7FDA,
  66         .sdram_tim3                     = 0x427F88A8,
  67         .read_idle_ctrl                 = 0x00050000,
  68         .zq_config                      = 0x0007190B,
  69         .temp_alert_config              = 0x00000000,
  70         .emif_ddr_phy_ctlr_1_init       = 0x0024400B,
  71         .emif_ddr_phy_ctlr_1            = 0x0E24400B,
  72         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
  73         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
  74         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
  75         .emif_ddr_ext_phy_ctrl_4        = 0x009B009B,
  76         .emif_ddr_ext_phy_ctrl_5        = 0x009E009E,
  77         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
  78         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
  79         .emif_rd_wr_lvl_ctl             = 0x00000000,
  80         .emif_rd_wr_exec_thresh         = 0x00000305
  81 };
  82
  83 static const struct emif_regs emif2_ddr3_532_mhz_1cs = {
  84         .sdram_config_init              = 0x61851B32,
  85         .sdram_config                   = 0x61851B32,
  86         .sdram_config2                  = 0x08000000,
  87         .ref_ctrl                       = 0x000040F1,
  88         .ref_ctrl_final                 = 0x00001035,
  89         .sdram_tim1                     = 0xCCCF36B3,
  90         .sdram_tim2                     = 0x308F7FDA,
  91         .sdram_tim3                     = 0x427F88A8,
  92         .read_idle_ctrl                 = 0x00050000,
  93         .zq_config                      = 0x0007190B,
  94         .temp_alert_config              = 0x00000000,
  95         .emif_ddr_phy_ctlr_1_init       = 0x0024400B,
  96         .emif_ddr_phy_ctlr_1            = 0x0E24400B,
  97         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
  98         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
  99         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 100         .emif_ddr_ext_phy_ctrl_4        = 0x009B009B,
 101         .emif_ddr_ext_phy_ctrl_5        = 0x009E009E,
 102         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 103         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 104         .emif_rd_wr_lvl_ctl             = 0x00000000,
 105         .emif_rd_wr_exec_thresh         = 0x00000305
 106 };
 107
 108 static const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
 109         .sdram_config_init              = 0x61862B32,
 110         .sdram_config                   = 0x61862B32,
 111         .sdram_config2                  = 0x08000000,
 112         .ref_ctrl                       = 0x0000514C,
 113         .ref_ctrl_final                 = 0x0000144A,
 114         .sdram_tim1                     = 0xD113781C,
 115         .sdram_tim2                     = 0x30717FE3,
 116         .sdram_tim3                     = 0x409F86A8,
 117         .read_idle_ctrl                 = 0x00050000,
 118         .zq_config                      = 0x5007190B,
 119         .temp_alert_config              = 0x00000000,
 120         .emif_ddr_phy_ctlr_1_init       = 0x0024400D,
 121         .emif_ddr_phy_ctlr_1            = 0x0E24400D,
 122         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 123         .emif_ddr_ext_phy_ctrl_2        = 0x00A400A4,
 124         .emif_ddr_ext_phy_ctrl_3        = 0x00A900A9,
 125         .emif_ddr_ext_phy_ctrl_4        = 0x00B000B0,
 126         .emif_ddr_ext_phy_ctrl_5        = 0x00B000B0,
 127         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 128         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 129         .emif_rd_wr_lvl_ctl             = 0x00000000,
 130         .emif_rd_wr_exec_thresh         = 0x00000305
 131 };
 132
 133 const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es2 = {
 134         .sdram_config_init              = 0x61862BB2,
 135         .sdram_config                   = 0x61862BB2,
 136         .sdram_config2                  = 0x00000000,
 137         .ref_ctrl                       = 0x0000514D,
 138         .ref_ctrl_final                 = 0x0000144A,
 139         .sdram_tim1                     = 0xD1137824,
 140         .sdram_tim2                     = 0x30B37FE3,
 141         .sdram_tim3                     = 0x409F8AD8,
 142         .read_idle_ctrl                 = 0x00050000,
 143         .zq_config                      = 0x5007190B,
 144         .temp_alert_config              = 0x00000000,
 145         .emif_ddr_phy_ctlr_1_init       = 0x0824400E,
 146         .emif_ddr_phy_ctlr_1            = 0x0E24400E,
 147         .emif_ddr_ext_phy_ctrl_1        = 0x04040100,
 148         .emif_ddr_ext_phy_ctrl_2        = 0x006B009F,
 149         .emif_ddr_ext_phy_ctrl_3        = 0x006B00A2,
 150         .emif_ddr_ext_phy_ctrl_4        = 0x006B00A8,
 151         .emif_ddr_ext_phy_ctrl_5        = 0x006B00A8,
 152         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 153         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 154         .emif_rd_wr_lvl_ctl             = 0x00000000,
 155         .emif_rd_wr_exec_thresh         = 0x00000305
 156 };
 157
 158 const struct emif_regs emif1_ddr3_532_mhz_1cs_2G = {
 159         .sdram_config_init              = 0x61851ab2,
 160         .sdram_config                   = 0x61851ab2,
 161         .sdram_config2                  = 0x08000000,
 162         .ref_ctrl                       = 0x000040F1,
 163         .ref_ctrl_final                 = 0x00001035,
 164         .sdram_tim1                     = 0xCCCF36B3,
 165         .sdram_tim2                     = 0x30BF7FDA,
 166         .sdram_tim3                     = 0x427F8BA8,
 167         .read_idle_ctrl                 = 0x00050000,
 168         .zq_config                      = 0x0007190B,
 169         .temp_alert_config              = 0x00000000,
 170         .emif_ddr_phy_ctlr_1_init       = 0x0024400B,
 171         .emif_ddr_phy_ctlr_1            = 0x0E24400B,
 172         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 173         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 174         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 175         .emif_ddr_ext_phy_ctrl_4        = 0x009B009B,
 176         .emif_ddr_ext_phy_ctrl_5        = 0x009E009E,
 177         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 178         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 179         .emif_rd_wr_lvl_ctl             = 0x00000000,
 180         .emif_rd_wr_exec_thresh         = 0x00000305
 181 };
 182
 183 const struct emif_regs emif2_ddr3_532_mhz_1cs_2G = {
 184         .sdram_config_init              = 0x61851B32,
 185         .sdram_config                   = 0x61851B32,
 186         .sdram_config2                  = 0x08000000,
 187         .ref_ctrl                       = 0x000040F1,
 188         .ref_ctrl_final                 = 0x00001035,
 189         .sdram_tim1                     = 0xCCCF36B3,
 190         .sdram_tim2                     = 0x308F7FDA,
 191         .sdram_tim3                     = 0x427F88A8,
 192         .read_idle_ctrl                 = 0x00050000,
 193         .zq_config                      = 0x0007190B,
 194         .temp_alert_config              = 0x00000000,
 195         .emif_ddr_phy_ctlr_1_init       = 0x0024400B,
 196         .emif_ddr_phy_ctlr_1            = 0x0E24400B,
 197         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 198         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 199         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 200         .emif_ddr_ext_phy_ctrl_4        = 0x009B009B,
 201         .emif_ddr_ext_phy_ctrl_5        = 0x009E009E,
 202         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 203         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 204         .emif_rd_wr_lvl_ctl             = 0x00000000,
 205         .emif_rd_wr_exec_thresh         = 0x00000305
 206 };
 207
 208 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 209 {
 210         u64 ram_size;
 211
 212         ram_size = board_ti_get_emif_size();
 213
 214         switch (omap_revision()) {
 215         case DRA752_ES1_0:
 216         case DRA752_ES1_1:
 217         case DRA752_ES2_0:
 218                 switch (emif_nr) {
 219                 case 1:
 220                         if (ram_size > CONFIG_MAX_MEM_MAPPED)
 221                                 *regs = &emif1_ddr3_532_mhz_1cs_2G;
 222                         else
 223                                 *regs = &emif1_ddr3_532_mhz_1cs;
 224                         break;
 225                 case 2:
 226                         if (ram_size > CONFIG_MAX_MEM_MAPPED)
 227                                 *regs = &emif2_ddr3_532_mhz_1cs_2G;
 228                         else
 229                                 *regs = &emif2_ddr3_532_mhz_1cs;
 230                         break;
 231                 }
 232                 break;
 233         case DRA722_ES1_0:
 234         case DRA722_ES2_0:
 235                 if (ram_size < CONFIG_MAX_MEM_MAPPED)
 236                         *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1;
 237                 else
 238                         *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es2;
 239                 break;
 240         default:
 241                 *regs = &emif1_ddr3_532_mhz_1cs;
 242         }
 243 }
 244
 245 static const struct dmm_lisa_map_regs lisa_map_dra7_1536MB = {
 246         .dmm_lisa_map_0 = 0x0,
 247         .dmm_lisa_map_1 = 0x80640300,
 248         .dmm_lisa_map_2 = 0xC0500220,
 249         .dmm_lisa_map_3 = 0xFF020100,
 250         .is_ma_present  = 0x1
 251 };
 252
 253 static const struct dmm_lisa_map_regs lisa_map_2G_x_2 = {
 254         .dmm_lisa_map_0 = 0x0,
 255         .dmm_lisa_map_1 = 0x0,
 256         .dmm_lisa_map_2 = 0x80600100,
 257         .dmm_lisa_map_3 = 0xFF020100,
 258         .is_ma_present  = 0x1
 259 };
 260
 261 const struct dmm_lisa_map_regs lisa_map_dra7_2GB = {
 262         .dmm_lisa_map_0 = 0x0,
 263         .dmm_lisa_map_1 = 0x0,
 264         .dmm_lisa_map_2 = 0x80740300,
 265         .dmm_lisa_map_3 = 0xFF020100,
 266         .is_ma_present  = 0x1
 267 };
 268
 269 /*
 270  * DRA722 EVM EMIF1 2GB CONFIGURATION
 271  * EMIF1 4 devices of 512Mb x 8 Micron
 272  */
 273 const struct dmm_lisa_map_regs lisa_map_2G_x_4 = {
 274         .dmm_lisa_map_0 = 0x0,
 275         .dmm_lisa_map_1 = 0x0,
 276         .dmm_lisa_map_2 = 0x80700100,
 277         .dmm_lisa_map_3 = 0xFF020100,
 278         .is_ma_present  = 0x1
 279 };
 280
 281 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
 282 {
 283         u64 ram_size;
 284
 285         ram_size = board_ti_get_emif_size();
 286
 287         switch (omap_revision()) {
 288         case DRA752_ES1_0:
 289         case DRA752_ES1_1:
 290         case DRA752_ES2_0:
 291                 if (ram_size > CONFIG_MAX_MEM_MAPPED)
 292                         *dmm_lisa_regs = &lisa_map_dra7_2GB;
 293                 else
 294                         *dmm_lisa_regs = &lisa_map_dra7_1536MB;
 295                 break;
 296         case DRA722_ES1_0:
 297         case DRA722_ES2_0:
 298         default:
 299                 if (ram_size < CONFIG_MAX_MEM_MAPPED)
 300                         *dmm_lisa_regs = &lisa_map_2G_x_2;
 301                 else
 302                         *dmm_lisa_regs = &lisa_map_2G_x_4;
 303                 break;
 304         }
 305 }
 306
 307 /**
 308  * @brief board_init
 309  *
 310  * @return 0
 311  */
 312 int board_init(void)
 313 {
 314         gpmc_init();
 315         gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
 316
 317         return 0;
 318 }
 319
 320 void dram_init_banksize(void)
 321 {
 322         u64 ram_size;
 323
 324         ram_size = board_ti_get_emif_size();
 325
 326         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 327         gd->bd->bi_dram[0].size = get_effective_memsize();
 328         if (ram_size > CONFIG_MAX_MEM_MAPPED) {
 329                 gd->bd->bi_dram[1].start = 0x200000000;
 330                 gd->bd->bi_dram[1].size = ram_size - CONFIG_MAX_MEM_MAPPED;
 331         }
 332 }
 333
 334 int board_late_init(void)
 335 {
 336 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 337         char *name = "unknown";
 338
 339         if (is_dra72x())
 340                 name = "dra72x";
 341         else
 342                 name = "dra7xx";
 343
 344         set_board_info_env(name);
 345
 346         omap_die_id_serial();
 347 #endif
 348         return 0;
 349 }
 350
 351 #ifdef CONFIG_SPL_BUILD
 352 void do_board_detect(void)
 353 {
 354         int rc;
 355
 356         rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
 357                                     CONFIG_EEPROM_CHIP_ADDRESS);
 358         if (rc)
 359                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 360 }
 361
 362 #else
 363
 364 void do_board_detect(void)
 365 {
 366         char *bname = NULL;
 367         int rc;
 368
 369         rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
 370                                     CONFIG_EEPROM_CHIP_ADDRESS);
 371         if (rc)
 372                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 373
 374         if (board_is_dra74x_evm()) {
 375                 bname = "DRA74x EVM";
 376         } else if (board_is_dra72x_evm()) {
 377                 bname = "DRA72x EVM";
 378         } else {
 379                 /* If EEPROM is not populated */
 380                 if (is_dra72x())
 381                         bname = "DRA72x EVM";
 382                 else
 383                         bname = "DRA74x EVM";
 384         }
 385
 386         if (bname)
 387                 snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
 388                          "Board: %s REV %s\n", bname, board_ti_get_rev());
 389 }
 390 #endif  /* CONFIG_SPL_BUILD */
 391
 392 void set_muxconf_regs(void)
 393 {
 394         do_set_mux32((*ctrl)->control_padconf_core_base,
 395                      early_padconf, ARRAY_SIZE(early_padconf));
 396 }
 397
 398 #ifdef CONFIG_IODELAY_RECALIBRATION
 399 void recalibrate_iodelay(void)
 400 {
 401         struct pad_conf_entry const *pads, *delta_pads = NULL;
 402         struct iodelay_cfg_entry const *iodelay;
 403         int npads, niodelays, delta_npads = 0;
 404         int ret;
 405
 406         switch (omap_revision()) {
 407         case DRA722_ES1_0:
 408         case DRA722_ES2_0:
 409                 pads = dra72x_core_padconf_array_common;
 410                 npads = ARRAY_SIZE(dra72x_core_padconf_array_common);
 411                 if (board_is_dra72x_revc_or_later()) {
 412                         delta_pads = dra72x_rgmii_padconf_array_revc;
 413                         delta_npads =
 414                                 ARRAY_SIZE(dra72x_rgmii_padconf_array_revc);
 415                         iodelay = dra72_iodelay_cfg_array_revc;
 416                         niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revc);
 417                 } else {
 418                         delta_pads = dra72x_rgmii_padconf_array_revb;
 419                         delta_npads =
 420                                 ARRAY_SIZE(dra72x_rgmii_padconf_array_revb);
 421                         iodelay = dra72_iodelay_cfg_array_revb;
 422                         niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revb);
 423                 }
 424                 break;
 425         case DRA752_ES1_0:
 426         case DRA752_ES1_1:
 427                 pads = dra74x_core_padconf_array;
 428                 npads = ARRAY_SIZE(dra74x_core_padconf_array);
 429                 iodelay = dra742_es1_1_iodelay_cfg_array;
 430                 niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array);
 431                 break;
 432         default:
 433         case DRA752_ES2_0:
 434                 pads = dra74x_core_padconf_array;
 435                 npads = ARRAY_SIZE(dra74x_core_padconf_array);
 436                 iodelay = dra742_es2_0_iodelay_cfg_array;
 437                 niodelays = ARRAY_SIZE(dra742_es2_0_iodelay_cfg_array);
 438                 /* Setup port1 and port2 for rgmii with 'no-id' mode */
 439                 clrset_spare_register(1, 0, RGMII2_ID_MODE_N_MASK |
 440                                       RGMII1_ID_MODE_N_MASK);
 441                 break;
 442         }
 443         /* Setup I/O isolation */
 444         ret = __recalibrate_iodelay_start();
 445         if (ret)
 446                 goto err;
 447
 448         /* Do the muxing here */
 449         do_set_mux32((*ctrl)->control_padconf_core_base, pads, npads);
 450
 451         /* Now do the weird minor deltas that should be safe */
 452         if (delta_npads)
 453                 do_set_mux32((*ctrl)->control_padconf_core_base,
 454                              delta_pads, delta_npads);
 455
 456         /* Setup IOdelay configuration */
 457         ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays);
 458 err:
 459         /* Closeup.. remove isolation */
 460         __recalibrate_iodelay_end(ret);
 461 }
 462 #endif
 463
 464 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
 465 int board_mmc_init(bd_t *bis)
 466 {
 467         omap_mmc_init(0, 0, 0, -1, -1);
 468         omap_mmc_init(1, 0, 0, -1, -1);
 469         return 0;
 470 }
 471 #endif
 472
 473 #ifdef CONFIG_USB_DWC3
 474 static struct dwc3_device usb_otg_ss1 = {
 475         .maximum_speed = USB_SPEED_SUPER,
 476         .base = DRA7_USB_OTG_SS1_BASE,
 477         .tx_fifo_resize = false,
 478         .index = 0,
 479 };
 480
 481 static struct dwc3_omap_device usb_otg_ss1_glue = {
 482         .base = (void *)DRA7_USB_OTG_SS1_GLUE_BASE,
 483         .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
 484         .index = 0,
 485 };
 486
 487 static struct ti_usb_phy_device usb_phy1_device = {
 488         .pll_ctrl_base = (void *)DRA7_USB3_PHY1_PLL_CTRL,
 489         .usb2_phy_power = (void *)DRA7_USB2_PHY1_POWER,
 490         .usb3_phy_power = (void *)DRA7_USB3_PHY1_POWER,
 491         .index = 0,
 492 };
 493
 494 static struct dwc3_device usb_otg_ss2 = {
 495         .maximum_speed = USB_SPEED_SUPER,
 496         .base = DRA7_USB_OTG_SS2_BASE,
 497         .tx_fifo_resize = false,
 498         .index = 1,
 499 };
 500
 501 static struct dwc3_omap_device usb_otg_ss2_glue = {
 502         .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE,
 503         .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
 504         .index = 1,
 505 };
 506
 507 static struct ti_usb_phy_device usb_phy2_device = {
 508         .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER,
 509         .index = 1,
 510 };
 511
 512 int board_usb_init(int index, enum usb_init_type init)
 513 {
 514         enable_usb_clocks(index);
 515         switch (index) {
 516         case 0:
 517                 if (init == USB_INIT_DEVICE) {
 518                         usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
 519                         usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
 520                 } else {
 521                         usb_otg_ss1.dr_mode = USB_DR_MODE_HOST;
 522                         usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
 523                 }
 524
 525                 ti_usb_phy_uboot_init(&usb_phy1_device);
 526                 dwc3_omap_uboot_init(&usb_otg_ss1_glue);
 527                 dwc3_uboot_init(&usb_otg_ss1);
 528                 break;
 529         case 1:
 530                 if (init == USB_INIT_DEVICE) {
 531                         usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
 532                         usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
 533                 } else {
 534                         usb_otg_ss2.dr_mode = USB_DR_MODE_HOST;
 535                         usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
 536                 }
 537
 538                 ti_usb_phy_uboot_init(&usb_phy2_device);
 539                 dwc3_omap_uboot_init(&usb_otg_ss2_glue);
 540                 dwc3_uboot_init(&usb_otg_ss2);
 541                 break;
 542         default:
 543                 printf("Invalid Controller Index\n");
 544         }
 545
 546         return 0;
 547 }
 548
 549 int board_usb_cleanup(int index, enum usb_init_type init)
 550 {
 551         switch (index) {
 552         case 0:
 553         case 1:
 554                 ti_usb_phy_uboot_exit(index);
 555                 dwc3_uboot_exit(index);
 556                 dwc3_omap_uboot_exit(index);
 557                 break;
 558         default:
 559                 printf("Invalid Controller Index\n");
 560         }
 561         disable_usb_clocks(index);
 562         return 0;
 563 }
 564
 565 int usb_gadget_handle_interrupts(int index)
 566 {
 567         u32 status;
 568
 569         status = dwc3_omap_uboot_interrupt_status(index);
 570         if (status)
 571                 dwc3_uboot_handle_interrupt(index);
 572
 573         return 0;
 574 }
 575 #endif
 576
 577 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
 578 int spl_start_uboot(void)
 579 {
 580         /* break into full u-boot on 'c' */
 581         if (serial_tstc() && serial_getc() == 'c')
 582                 return 1;
 583
 584 #ifdef CONFIG_SPL_ENV_SUPPORT
 585         env_init();
 586         env_relocate_spec();
 587         if (getenv_yesno("boot_os") != 1)
 588                 return 1;
 589 #endif
 590
 591         return 0;
 592 }
 593 #endif
 594
 595 #ifdef CONFIG_DRIVER_TI_CPSW
 596 extern u32 *const omap_si_rev;
 597
 598 static void cpsw_control(int enabled)
 599 {
 600         /* VTP can be added here */
 601
 602         return;
 603 }
 604
 605 static struct cpsw_slave_data cpsw_slaves[] = {
 606         {
 607                 .slave_reg_ofs  = 0x208,
 608                 .sliver_reg_ofs = 0xd80,
 609                 .phy_addr       = 2,
 610         },
 611         {
 612                 .slave_reg_ofs  = 0x308,
 613                 .sliver_reg_ofs = 0xdc0,
 614                 .phy_addr       = 3,
 615         },
 616 };
 617
 618 static struct cpsw_platform_data cpsw_data = {
 619         .mdio_base              = CPSW_MDIO_BASE,
 620         .cpsw_base              = CPSW_BASE,
 621         .mdio_div               = 0xff,
 622         .channels               = 8,
 623         .cpdma_reg_ofs          = 0x800,
 624         .slaves                 = 2,
 625         .slave_data             = cpsw_slaves,
 626         .ale_reg_ofs            = 0xd00,
 627         .ale_entries            = 1024,
 628         .host_port_reg_ofs      = 0x108,
 629         .hw_stats_reg_ofs       = 0x900,
 630         .bd_ram_ofs             = 0x2000,
 631         .mac_control            = (1 << 5),
 632         .control                = cpsw_control,
 633         .host_port_num          = 0,
 634         .version                = CPSW_CTRL_VERSION_2,
 635 };
 636
 637 int board_eth_init(bd_t *bis)
 638 {
 639         int ret;
 640         uint8_t mac_addr[6];
 641         uint32_t mac_hi, mac_lo;
 642         uint32_t ctrl_val;
 643
 644         /* try reading mac address from efuse */
 645         mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
 646         mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
 647         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
 648         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 649         mac_addr[2] = mac_hi & 0xFF;
 650         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
 651         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
 652         mac_addr[5] = mac_lo & 0xFF;
 653
 654         if (!getenv("ethaddr")) {
 655                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
 656
 657                 if (is_valid_ethaddr(mac_addr))
 658                         eth_setenv_enetaddr("ethaddr", mac_addr);
 659         }
 660
 661         mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
 662         mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
 663         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
 664         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 665         mac_addr[2] = mac_hi & 0xFF;
 666         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
 667         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
 668         mac_addr[5] = mac_lo & 0xFF;
 669
 670         if (!getenv("eth1addr")) {
 671                 if (is_valid_ethaddr(mac_addr))
 672                         eth_setenv_enetaddr("eth1addr", mac_addr);
 673         }
 674
 675         ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
 676         ctrl_val |= 0x22;
 677         writel(ctrl_val, (*ctrl)->control_core_control_io1);
 678
 679         if (*omap_si_rev == DRA722_ES1_0)
 680                 cpsw_data.active_slave = 1;
 681
 682         ret = cpsw_register(&cpsw_data);
 683         if (ret < 0)
 684                 printf("Error %d registering CPSW switch\n", ret);
 685
 686         return ret;
 687 }
 688 #endif
 689
 690 #ifdef CONFIG_BOARD_EARLY_INIT_F
 691 /* VTT regulator enable */
 692 static inline void vtt_regulator_enable(void)
 693 {
 694         if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
 695                 return;
 696
 697         /* Do not enable VTT for DRA722 */
 698         if (is_dra72x())
 699                 return;
 700
 701         /*
 702          * EVM Rev G and later use gpio7_11 for DDR3 termination.
 703          * This is safe enough to do on older revs.
 704          */
 705         gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
 706         gpio_direction_output(GPIO_DDR_VTT_EN, 1);
 707 }
 708
 709 int board_early_init_f(void)
 710 {
 711         vtt_regulator_enable();
 712         return 0;
 713 }
 714 #endif