board/ti/dra7xx/evm.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2013
   4  * Texas Instruments Incorporated, <www.ti.com>
   5  *
   6  * Lokesh Vutla <lokeshvutla@ti.com>
   7  *
   8  * Based on previous work by:
   9  * Aneesh V       <aneesh@ti.com>
  10  * Steve Sakoman  <steve@sakoman.com>
  11  */
  12 #include <common.h>
  13 #include <env.h>
  14 #include <fdt_support.h>
  15 #include <init.h>
  16 #include <spl.h>
  17 #include <palmas.h>
  18 #include <sata.h>
  19 #include <serial.h>
  20 #include <linux/string.h>
  21 #include <asm/gpio.h>
  22 #include <usb.h>
  23 #include <linux/usb/gadget.h>
  24 #include <asm/omap_common.h>
  25 #include <asm/omap_sec_common.h>
  26 #include <asm/arch/gpio.h>
  27 #include <asm/arch/dra7xx_iodelay.h>
  28 #include <asm/emif.h>
  29 #include <asm/arch/sys_proto.h>
  30 #include <asm/arch/mmc_host_def.h>
  31 #include <asm/arch/sata.h>
  32 #include <dwc3-uboot.h>
  33 #include <dwc3-omap-uboot.h>
  34 #include <i2c.h>
  35 #include <ti-usb-phy-uboot.h>
  36
  37 #include "mux_data.h"
  38 #include "../common/board_detect.h"
  39
  40 #define board_is_dra76x_evm()           board_ti_is("DRA76/7x")
  41 #define board_is_dra74x_evm()           board_ti_is("5777xCPU")
  42 #define board_is_dra72x_evm()           board_ti_is("DRA72x-T")
  43 #define board_is_dra71x_evm()           board_ti_is("DRA79x,D")
  44 #define board_is_dra74x_revh_or_later() (board_is_dra74x_evm() &&       \
  45                                 (strncmp("H", board_ti_get_rev(), 1) <= 0))
  46 #define board_is_dra72x_revc_or_later() (board_is_dra72x_evm() &&       \
  47                                 (strncmp("C", board_ti_get_rev(), 1) <= 0))
  48 #define board_ti_get_emif_size()        board_ti_get_emif1_size() +     \
  49                                         board_ti_get_emif2_size()
  50
  51 DECLARE_GLOBAL_DATA_PTR;
  52
  53 /* GPIO 7_11 */
  54 #define GPIO_DDR_VTT_EN 203
  55
  56 #define SYSINFO_BOARD_NAME_MAX_LEN      37
  57
  58 /* I2C I/O Expander */
  59 #define NAND_PCF8575_ADDR       0x21
  60 #define NAND_PCF8575_I2C_BUS_NUM        0
  61
  62 const struct omap_sysinfo sysinfo = {
  63         "Board: UNKNOWN(DRA7 EVM) REV UNKNOWN\n"
  64 };
  65
  66 static const struct emif_regs emif1_ddr3_532_mhz_1cs = {
  67         .sdram_config_init              = 0x61851ab2,
  68         .sdram_config                   = 0x61851ab2,
  69         .sdram_config2                  = 0x08000000,
  70         .ref_ctrl                       = 0x000040F1,
  71         .ref_ctrl_final                 = 0x00001035,
  72         .sdram_tim1                     = 0xCCCF36B3,
  73         .sdram_tim2                     = 0x308F7FDA,
  74         .sdram_tim3                     = 0x427F88A8,
  75         .read_idle_ctrl                 = 0x00050000,
  76         .zq_config                      = 0x0007190B,
  77         .temp_alert_config              = 0x00000000,
  78         .emif_ddr_phy_ctlr_1_init       = 0x0024400B,
  79         .emif_ddr_phy_ctlr_1            = 0x0E24400B,
  80         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
  81         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
  82         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
  83         .emif_ddr_ext_phy_ctrl_4        = 0x009B009B,
  84         .emif_ddr_ext_phy_ctrl_5        = 0x009E009E,
  85         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
  86         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
  87         .emif_rd_wr_lvl_ctl             = 0x00000000,
  88         .emif_rd_wr_exec_thresh         = 0x00000305
  89 };
  90
  91 static const struct emif_regs emif2_ddr3_532_mhz_1cs = {
  92         .sdram_config_init              = 0x61851B32,
  93         .sdram_config                   = 0x61851B32,
  94         .sdram_config2                  = 0x08000000,
  95         .ref_ctrl                       = 0x000040F1,
  96         .ref_ctrl_final                 = 0x00001035,
  97         .sdram_tim1                     = 0xCCCF36B3,
  98         .sdram_tim2                     = 0x308F7FDA,
  99         .sdram_tim3                     = 0x427F88A8,
 100         .read_idle_ctrl                 = 0x00050000,
 101         .zq_config                      = 0x0007190B,
 102         .temp_alert_config              = 0x00000000,
 103         .emif_ddr_phy_ctlr_1_init       = 0x0024400B,
 104         .emif_ddr_phy_ctlr_1            = 0x0E24400B,
 105         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 106         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 107         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 108         .emif_ddr_ext_phy_ctrl_4        = 0x009B009B,
 109         .emif_ddr_ext_phy_ctrl_5        = 0x009E009E,
 110         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 111         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 112         .emif_rd_wr_lvl_ctl             = 0x00000000,
 113         .emif_rd_wr_exec_thresh         = 0x00000305
 114 };
 115
 116 static const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
 117         .sdram_config_init              = 0x61862B32,
 118         .sdram_config                   = 0x61862B32,
 119         .sdram_config2                  = 0x08000000,
 120         .ref_ctrl                       = 0x0000514C,
 121         .ref_ctrl_final                 = 0x0000144A,
 122         .sdram_tim1                     = 0xD113781C,
 123         .sdram_tim2                     = 0x30717FE3,
 124         .sdram_tim3                     = 0x409F86A8,
 125         .read_idle_ctrl                 = 0x00050000,
 126         .zq_config                      = 0x5007190B,
 127         .temp_alert_config              = 0x00000000,
 128         .emif_ddr_phy_ctlr_1_init       = 0x0024400D,
 129         .emif_ddr_phy_ctlr_1            = 0x0E24400D,
 130         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 131         .emif_ddr_ext_phy_ctrl_2        = 0x00A400A4,
 132         .emif_ddr_ext_phy_ctrl_3        = 0x00A900A9,
 133         .emif_ddr_ext_phy_ctrl_4        = 0x00B000B0,
 134         .emif_ddr_ext_phy_ctrl_5        = 0x00B000B0,
 135         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 136         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 137         .emif_rd_wr_lvl_ctl             = 0x00000000,
 138         .emif_rd_wr_exec_thresh         = 0x00000305
 139 };
 140
 141 const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es2 = {
 142         .sdram_config_init              = 0x61862BB2,
 143         .sdram_config                   = 0x61862BB2,
 144         .sdram_config2                  = 0x00000000,
 145         .ref_ctrl                       = 0x0000514D,
 146         .ref_ctrl_final                 = 0x0000144A,
 147         .sdram_tim1                     = 0xD1137824,
 148         .sdram_tim2                     = 0x30B37FE3,
 149         .sdram_tim3                     = 0x409F8AD8,
 150         .read_idle_ctrl                 = 0x00050000,
 151         .zq_config                      = 0x5007190B,
 152         .temp_alert_config              = 0x00000000,
 153         .emif_ddr_phy_ctlr_1_init       = 0x0824400E,
 154         .emif_ddr_phy_ctlr_1            = 0x0E24400E,
 155         .emif_ddr_ext_phy_ctrl_1        = 0x04040100,
 156         .emif_ddr_ext_phy_ctrl_2        = 0x006B009F,
 157         .emif_ddr_ext_phy_ctrl_3        = 0x006B00A2,
 158         .emif_ddr_ext_phy_ctrl_4        = 0x006B00A8,
 159         .emif_ddr_ext_phy_ctrl_5        = 0x006B00A8,
 160         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 161         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 162         .emif_rd_wr_lvl_ctl             = 0x00000000,
 163         .emif_rd_wr_exec_thresh         = 0x00000305
 164 };
 165
 166 const struct emif_regs emif1_ddr3_532_mhz_1cs_2G = {
 167         .sdram_config_init              = 0x61851ab2,
 168         .sdram_config                   = 0x61851ab2,
 169         .sdram_config2                  = 0x08000000,
 170         .ref_ctrl                       = 0x000040F1,
 171         .ref_ctrl_final                 = 0x00001035,
 172         .sdram_tim1                     = 0xCCCF36B3,
 173         .sdram_tim2                     = 0x30BF7FDA,
 174         .sdram_tim3                     = 0x427F8BA8,
 175         .read_idle_ctrl                 = 0x00050000,
 176         .zq_config                      = 0x0007190B,
 177         .temp_alert_config              = 0x00000000,
 178         .emif_ddr_phy_ctlr_1_init       = 0x0024400B,
 179         .emif_ddr_phy_ctlr_1            = 0x0E24400B,
 180         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 181         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 182         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 183         .emif_ddr_ext_phy_ctrl_4        = 0x009B009B,
 184         .emif_ddr_ext_phy_ctrl_5        = 0x009E009E,
 185         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 186         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 187         .emif_rd_wr_lvl_ctl             = 0x00000000,
 188         .emif_rd_wr_exec_thresh         = 0x00000305
 189 };
 190
 191 const struct emif_regs emif2_ddr3_532_mhz_1cs_2G = {
 192         .sdram_config_init              = 0x61851B32,
 193         .sdram_config                   = 0x61851B32,
 194         .sdram_config2                  = 0x08000000,
 195         .ref_ctrl                       = 0x000040F1,
 196         .ref_ctrl_final                 = 0x00001035,
 197         .sdram_tim1                     = 0xCCCF36B3,
 198         .sdram_tim2                     = 0x308F7FDA,
 199         .sdram_tim3                     = 0x427F88A8,
 200         .read_idle_ctrl                 = 0x00050000,
 201         .zq_config                      = 0x0007190B,
 202         .temp_alert_config              = 0x00000000,
 203         .emif_ddr_phy_ctlr_1_init       = 0x0024400B,
 204         .emif_ddr_phy_ctlr_1            = 0x0E24400B,
 205         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 206         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 207         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 208         .emif_ddr_ext_phy_ctrl_4        = 0x009B009B,
 209         .emif_ddr_ext_phy_ctrl_5        = 0x009E009E,
 210         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 211         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 212         .emif_rd_wr_lvl_ctl             = 0x00000000,
 213         .emif_rd_wr_exec_thresh         = 0x00000305
 214 };
 215
 216 const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra76 = {
 217         .sdram_config_init              = 0x61862B32,
 218         .sdram_config                   = 0x61862B32,
 219         .sdram_config2                  = 0x00000000,
 220         .ref_ctrl                       = 0x0000514C,
 221         .ref_ctrl_final                 = 0x0000144A,
 222         .sdram_tim1                     = 0xD113783C,
 223         .sdram_tim2                     = 0x30B47FE3,
 224         .sdram_tim3                     = 0x409F8AD8,
 225         .read_idle_ctrl                 = 0x00050000,
 226         .zq_config                      = 0x5007190B,
 227         .temp_alert_config              = 0x00000000,
 228         .emif_ddr_phy_ctlr_1_init       = 0x0824400D,
 229         .emif_ddr_phy_ctlr_1            = 0x0E24400D,
 230         .emif_ddr_ext_phy_ctrl_1        = 0x04040100,
 231         .emif_ddr_ext_phy_ctrl_2        = 0x006B009F,
 232         .emif_ddr_ext_phy_ctrl_3        = 0x006B00A2,
 233         .emif_ddr_ext_phy_ctrl_4        = 0x006B00A8,
 234         .emif_ddr_ext_phy_ctrl_5        = 0x006B00A8,
 235         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 236         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 237         .emif_rd_wr_lvl_ctl             = 0x00000000,
 238         .emif_rd_wr_exec_thresh         = 0x00000305
 239 };
 240
 241 const struct emif_regs emif_2_regs_ddr3_666_mhz_1cs_dra76 = {
 242         .sdram_config_init              = 0x61862B32,
 243         .sdram_config                   = 0x61862B32,
 244         .sdram_config2                  = 0x00000000,
 245         .ref_ctrl                       = 0x0000514C,
 246         .ref_ctrl_final                 = 0x0000144A,
 247         .sdram_tim1                     = 0xD113781C,
 248         .sdram_tim2                     = 0x30B47FE3,
 249         .sdram_tim3                     = 0x409F8AD8,
 250         .read_idle_ctrl                 = 0x00050000,
 251         .zq_config                      = 0x5007190B,
 252         .temp_alert_config              = 0x00000000,
 253         .emif_ddr_phy_ctlr_1_init       = 0x0824400D,
 254         .emif_ddr_phy_ctlr_1            = 0x0E24400D,
 255         .emif_ddr_ext_phy_ctrl_1        = 0x04040100,
 256         .emif_ddr_ext_phy_ctrl_2        = 0x006B009F,
 257         .emif_ddr_ext_phy_ctrl_3        = 0x006B00A2,
 258         .emif_ddr_ext_phy_ctrl_4        = 0x006B00A8,
 259         .emif_ddr_ext_phy_ctrl_5        = 0x006B00A8,
 260         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 261         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 262         .emif_rd_wr_lvl_ctl             = 0x00000000,
 263         .emif_rd_wr_exec_thresh         = 0x00000305
 264 };
 265
 266 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 267 {
 268         u64 ram_size;
 269
 270         ram_size = board_ti_get_emif_size();
 271
 272         switch (omap_revision()) {
 273         case DRA752_ES1_0:
 274         case DRA752_ES1_1:
 275         case DRA752_ES2_0:
 276                 switch (emif_nr) {
 277                 case 1:
 278                         if (ram_size > CONFIG_MAX_MEM_MAPPED)
 279                                 *regs = &emif1_ddr3_532_mhz_1cs_2G;
 280                         else
 281                                 *regs = &emif1_ddr3_532_mhz_1cs;
 282                         break;
 283                 case 2:
 284                         if (ram_size > CONFIG_MAX_MEM_MAPPED)
 285                                 *regs = &emif2_ddr3_532_mhz_1cs_2G;
 286                         else
 287                                 *regs = &emif2_ddr3_532_mhz_1cs;
 288                         break;
 289                 }
 290                 break;
 291         case DRA762_ABZ_ES1_0:
 292         case DRA762_ACD_ES1_0:
 293         case DRA762_ES1_0:
 294                 if (emif_nr == 1)
 295                         *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra76;
 296                 else
 297                         *regs = &emif_2_regs_ddr3_666_mhz_1cs_dra76;
 298                 break;
 299         case DRA722_ES1_0:
 300         case DRA722_ES2_0:
 301         case DRA722_ES2_1:
 302                 if (ram_size < CONFIG_MAX_MEM_MAPPED)
 303                         *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1;
 304                 else
 305                         *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es2;
 306                 break;
 307         default:
 308                 *regs = &emif1_ddr3_532_mhz_1cs;
 309         }
 310 }
 311
 312 static const struct dmm_lisa_map_regs lisa_map_dra7_1536MB = {
 313         .dmm_lisa_map_0 = 0x0,
 314         .dmm_lisa_map_1 = 0x80640300,
 315         .dmm_lisa_map_2 = 0xC0500220,
 316         .dmm_lisa_map_3 = 0xFF020100,
 317         .is_ma_present  = 0x1
 318 };
 319
 320 static const struct dmm_lisa_map_regs lisa_map_2G_x_2 = {
 321         .dmm_lisa_map_0 = 0x0,
 322         .dmm_lisa_map_1 = 0x0,
 323         .dmm_lisa_map_2 = 0x80600100,
 324         .dmm_lisa_map_3 = 0xFF020100,
 325         .is_ma_present  = 0x1
 326 };
 327
 328 const struct dmm_lisa_map_regs lisa_map_dra7_2GB = {
 329         .dmm_lisa_map_0 = 0x0,
 330         .dmm_lisa_map_1 = 0x0,
 331         .dmm_lisa_map_2 = 0x80740300,
 332         .dmm_lisa_map_3 = 0xFF020100,
 333         .is_ma_present  = 0x1
 334 };
 335
 336 /*
 337  * DRA722 EVM EMIF1 2GB CONFIGURATION
 338  * EMIF1 4 devices of 512Mb x 8 Micron
 339  */
 340 const struct dmm_lisa_map_regs lisa_map_2G_x_4 = {
 341         .dmm_lisa_map_0 = 0x0,
 342         .dmm_lisa_map_1 = 0x0,
 343         .dmm_lisa_map_2 = 0x80700100,
 344         .dmm_lisa_map_3 = 0xFF020100,
 345         .is_ma_present  = 0x1
 346 };
 347
 348 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
 349 {
 350         u64 ram_size;
 351
 352         ram_size = board_ti_get_emif_size();
 353
 354         switch (omap_revision()) {
 355         case DRA762_ABZ_ES1_0:
 356         case DRA762_ACD_ES1_0:
 357         case DRA762_ES1_0:
 358         case DRA752_ES1_0:
 359         case DRA752_ES1_1:
 360         case DRA752_ES2_0:
 361                 if (ram_size > CONFIG_MAX_MEM_MAPPED)
 362                         *dmm_lisa_regs = &lisa_map_dra7_2GB;
 363                 else
 364                         *dmm_lisa_regs = &lisa_map_dra7_1536MB;
 365                 break;
 366         case DRA722_ES1_0:
 367         case DRA722_ES2_0:
 368         case DRA722_ES2_1:
 369         default:
 370                 if (ram_size < CONFIG_MAX_MEM_MAPPED)
 371                         *dmm_lisa_regs = &lisa_map_2G_x_2;
 372                 else
 373                         *dmm_lisa_regs = &lisa_map_2G_x_4;
 374                 break;
 375         }
 376 }
 377
 378 struct vcores_data dra752_volts = {
 379         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 380         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 381         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 382         .mpu.addr       = TPS659038_REG_ADDR_SMPS12,
 383         .mpu.pmic       = &tps659038,
 384         .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
 385
 386         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 387         .eve.value[OPP_OD]      = VDD_EVE_DRA7_OD,
 388         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 389         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 390         .eve.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_DSPEVE_OD,
 391         .eve.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 392         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 393         .eve.addr       = TPS659038_REG_ADDR_SMPS45,
 394         .eve.pmic       = &tps659038,
 395         .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
 396
 397         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 398         .gpu.value[OPP_OD]      = VDD_GPU_DRA7_OD,
 399         .gpu.value[OPP_HIGH]    = VDD_GPU_DRA7_HIGH,
 400         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 401         .gpu.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_GPU_OD,
 402         .gpu.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_GPU_HIGH,
 403         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 404         .gpu.addr       = TPS659038_REG_ADDR_SMPS6,
 405         .gpu.pmic       = &tps659038,
 406         .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
 407
 408         .core.value[OPP_NOM]    = VDD_CORE_DRA7_NOM,
 409         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 410         .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 411         .core.addr      = TPS659038_REG_ADDR_SMPS7,
 412         .core.pmic      = &tps659038,
 413
 414         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 415         .iva.value[OPP_OD]      = VDD_IVA_DRA7_OD,
 416         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 417         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 418         .iva.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_IVA_OD,
 419         .iva.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_IVA_HIGH,
 420         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 421         .iva.addr       = TPS659038_REG_ADDR_SMPS8,
 422         .iva.pmic       = &tps659038,
 423         .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
 424 };
 425
 426 struct vcores_data dra76x_volts = {
 427         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 428         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 429         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 430         .mpu.addr       = LP87565_REG_ADDR_BUCK01,
 431         .mpu.pmic       = &lp87565,
 432         .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
 433
 434         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 435         .eve.value[OPP_OD]      = VDD_EVE_DRA7_OD,
 436         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 437         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 438         .eve.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_DSPEVE_OD,
 439         .eve.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 440         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 441         .eve.addr       = TPS65917_REG_ADDR_SMPS1,
 442         .eve.pmic       = &tps659038,
 443         .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
 444
 445         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 446         .gpu.value[OPP_OD]      = VDD_GPU_DRA7_OD,
 447         .gpu.value[OPP_HIGH]    = VDD_GPU_DRA7_HIGH,
 448         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 449         .gpu.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_GPU_OD,
 450         .gpu.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_GPU_HIGH,
 451         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 452         .gpu.addr       = LP87565_REG_ADDR_BUCK23,
 453         .gpu.pmic       = &lp87565,
 454         .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
 455
 456         .core.value[OPP_NOM]    = VDD_CORE_DRA7_NOM,
 457         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 458         .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 459         .core.addr      = TPS65917_REG_ADDR_SMPS3,
 460         .core.pmic      = &tps659038,
 461
 462         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 463         .iva.value[OPP_OD]      = VDD_IVA_DRA7_OD,
 464         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 465         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 466         .iva.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_IVA_OD,
 467         .iva.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_IVA_HIGH,
 468         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 469         .iva.addr       = TPS65917_REG_ADDR_SMPS4,
 470         .iva.pmic       = &tps659038,
 471         .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
 472 };
 473
 474 struct vcores_data dra722_volts = {
 475         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 476         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 477         .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 478         .mpu.addr       = TPS65917_REG_ADDR_SMPS1,
 479         .mpu.pmic       = &tps659038,
 480         .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
 481
 482         .core.value[OPP_NOM]    = VDD_CORE_DRA7_NOM,
 483         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 484         .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 485         .core.addr      = TPS65917_REG_ADDR_SMPS2,
 486         .core.pmic      = &tps659038,
 487
 488         /*
 489          * The DSPEVE, GPU and IVA rails are usually grouped on DRA72x
 490          * designs and powered by TPS65917 SMPS3, as on the J6Eco EVM.
 491          */
 492         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 493         .gpu.value[OPP_OD]      = VDD_GPU_DRA7_OD,
 494         .gpu.value[OPP_HIGH]    = VDD_GPU_DRA7_HIGH,
 495         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 496         .gpu.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_GPU_OD,
 497         .gpu.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_GPU_HIGH,
 498         .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 499         .gpu.addr       = TPS65917_REG_ADDR_SMPS3,
 500         .gpu.pmic       = &tps659038,
 501         .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
 502
 503         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 504         .eve.value[OPP_OD]      = VDD_EVE_DRA7_OD,
 505         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 506         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 507         .eve.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_DSPEVE_OD,
 508         .eve.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 509         .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 510         .eve.addr       = TPS65917_REG_ADDR_SMPS3,
 511         .eve.pmic       = &tps659038,
 512         .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
 513
 514         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 515         .iva.value[OPP_OD]      = VDD_IVA_DRA7_OD,
 516         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 517         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 518         .iva.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_IVA_OD,
 519         .iva.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_IVA_HIGH,
 520         .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 521         .iva.addr       = TPS65917_REG_ADDR_SMPS3,
 522         .iva.pmic       = &tps659038,
 523         .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
 524 };
 525
 526 struct vcores_data dra718_volts = {
 527         /*
 528          * In the case of dra71x GPU MPU and CORE
 529          * are all powered up by BUCK0 of LP873X PMIC
 530          */
 531         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 532         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 533         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 534         .mpu.addr       = LP873X_REG_ADDR_BUCK0,
 535         .mpu.pmic       = &lp8733,
 536         .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
 537
 538         .core.value[OPP_NOM]            = VDD_CORE_DRA7_NOM,
 539         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 540         .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 541         .core.addr      = LP873X_REG_ADDR_BUCK0,
 542         .core.pmic      = &lp8733,
 543
 544         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 545         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 546         .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 547         .gpu.addr       = LP873X_REG_ADDR_BUCK0,
 548         .gpu.pmic       = &lp8733,
 549         .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
 550
 551         /*
 552          * The DSPEVE and IVA rails are grouped on DRA71x-evm
 553          * and are powered by BUCK1 of LP873X PMIC
 554          */
 555         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 556         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 557         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 558         .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 559         .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 560         .eve.addr       = LP873X_REG_ADDR_BUCK1,
 561         .eve.pmic       = &lp8733,
 562         .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
 563
 564         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 565         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 566         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 567         .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
 568         .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 569         .iva.addr       = LP873X_REG_ADDR_BUCK1,
 570         .iva.pmic       = &lp8733,
 571         .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
 572 };
 573
 574 int get_voltrail_opp(int rail_offset)
 575 {
 576         int opp;
 577
 578         switch (rail_offset) {
 579         case VOLT_MPU:
 580                 opp = DRA7_MPU_OPP;
 581                 /* DRA71x supports only OPP_NOM for MPU */
 582                 if (board_is_dra71x_evm())
 583                         opp = OPP_NOM;
 584                 break;
 585         case VOLT_CORE:
 586                 opp = DRA7_CORE_OPP;
 587                 /* DRA71x supports only OPP_NOM for CORE */
 588                 if (board_is_dra71x_evm())
 589                         opp = OPP_NOM;
 590                 break;
 591         case VOLT_GPU:
 592                 opp = DRA7_GPU_OPP;
 593                 /* DRA71x supports only OPP_NOM for GPU */
 594                 if (board_is_dra71x_evm())
 595                         opp = OPP_NOM;
 596                 break;
 597         case VOLT_EVE:
 598                 opp = DRA7_DSPEVE_OPP;
 599                 /*
 600                  * DRA71x does not support OPP_OD for EVE.
 601                  * If OPP_OD is selected by menuconfig, fallback
 602                  * to OPP_NOM.
 603                  */
 604                 if (board_is_dra71x_evm() && opp == OPP_OD)
 605                         opp = OPP_NOM;
 606                 break;
 607         case VOLT_IVA:
 608                 opp = DRA7_IVA_OPP;
 609                 /*
 610                  * DRA71x does not support OPP_OD for IVA.
 611                  * If OPP_OD is selected by menuconfig, fallback
 612                  * to OPP_NOM.
 613                  */
 614                 if (board_is_dra71x_evm() && opp == OPP_OD)
 615                         opp = OPP_NOM;
 616                 break;
 617         default:
 618                 opp = OPP_NOM;
 619         }
 620
 621         return opp;
 622 }
 623
 624 /**
 625  * @brief board_init
 626  *
 627  * @return 0
 628  */
 629 int board_init(void)
 630 {
 631         gpmc_init();
 632         gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
 633
 634         return 0;
 635 }
 636
 637 int dram_init_banksize(void)
 638 {
 639         u64 ram_size;
 640
 641         ram_size = board_ti_get_emif_size();
 642
 643         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 644         gd->bd->bi_dram[0].size = get_effective_memsize();
 645         if (ram_size > CONFIG_MAX_MEM_MAPPED) {
 646                 gd->bd->bi_dram[1].start = 0x200000000;
 647                 gd->bd->bi_dram[1].size = ram_size - CONFIG_MAX_MEM_MAPPED;
 648         }
 649
 650         return 0;
 651 }
 652
 653 #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
 654 static int device_okay(const char *path)
 655 {
 656         int node;
 657
 658         node = fdt_path_offset(gd->fdt_blob, path);
 659         if (node < 0)
 660                 return 0;
 661
 662         return fdtdec_get_is_enabled(gd->fdt_blob, node);
 663 }
 664 #endif
 665
 666 int board_late_init(void)
 667 {
 668 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 669         char *name = "unknown";
 670
 671         if (is_dra72x()) {
 672                 if (board_is_dra72x_revc_or_later())
 673                         name = "dra72x-revc";
 674                 else if (board_is_dra71x_evm())
 675                         name = "dra71x";
 676                 else
 677                         name = "dra72x";
 678         } else if (is_dra76x_abz()) {
 679                 name = "dra76x_abz";
 680         } else if (is_dra76x_acd()) {
 681                 name = "dra76x_acd";
 682         } else {
 683                 name = "dra7xx";
 684         }
 685
 686         set_board_info_env(name);
 687
 688         /*
 689          * Default FIT boot on HS devices. Non FIT images are not allowed
 690          * on HS devices.
 691          */
 692         if (get_device_type() == HS_DEVICE)
 693                 env_set("boot_fit", "1");
 694
 695         omap_die_id_serial();
 696         omap_set_fastboot_vars();
 697
 698         /*
 699          * Hook the LDO1 regulator to EN pin. This applies only to LP8733
 700          * Rest all regulators are hooked to EN Pin at reset.
 701          */
 702         if (board_is_dra71x_evm())
 703                 palmas_i2c_write_u8(LP873X_I2C_SLAVE_ADDR, 0x9, 0x7);
 704 #endif
 705 #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
 706         if (device_okay("/ocp/omap_dwc3_1@48880000"))
 707                 enable_usb_clocks(0);
 708         if (device_okay("/ocp/omap_dwc3_2@488c0000"))
 709                 enable_usb_clocks(1);
 710 #endif
 711         return 0;
 712 }
 713
 714 #ifdef CONFIG_SPL_BUILD
 715 void do_board_detect(void)
 716 {
 717         int rc;
 718
 719         rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
 720                                     CONFIG_EEPROM_CHIP_ADDRESS);
 721         if (rc)
 722                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 723 }
 724
 725 #else
 726
 727 void do_board_detect(void)
 728 {
 729         char *bname = NULL;
 730         int rc;
 731
 732         rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
 733                                     CONFIG_EEPROM_CHIP_ADDRESS);
 734         if (rc)
 735                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 736
 737         if (board_is_dra74x_evm()) {
 738                 bname = "DRA74x EVM";
 739         } else if (board_is_dra72x_evm()) {
 740                 bname = "DRA72x EVM";
 741         } else if (board_is_dra71x_evm()) {
 742                 bname = "DRA71x EVM";
 743         } else if (board_is_dra76x_evm()) {
 744                 bname = "DRA76x EVM";
 745         } else {
 746                 /* If EEPROM is not populated */
 747                 if (is_dra72x())
 748                         bname = "DRA72x EVM";
 749                 else
 750                         bname = "DRA74x EVM";
 751         }
 752
 753         if (bname)
 754                 snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
 755                          "Board: %s REV %s\n", bname, board_ti_get_rev());
 756 }
 757 #endif  /* CONFIG_SPL_BUILD */
 758
 759 void vcores_init(void)
 760 {
 761         if (board_is_dra74x_evm()) {
 762                 *omap_vcores = &dra752_volts;
 763         } else if (board_is_dra72x_evm()) {
 764                 *omap_vcores = &dra722_volts;
 765         } else if (board_is_dra71x_evm()) {
 766                 *omap_vcores = &dra718_volts;
 767         } else if (board_is_dra76x_evm()) {
 768                 *omap_vcores = &dra76x_volts;
 769         } else {
 770                 /* If EEPROM is not populated */
 771                 if (is_dra72x())
 772                         *omap_vcores = &dra722_volts;
 773                 else
 774                         *omap_vcores = &dra752_volts;
 775         }
 776 }
 777
 778 void set_muxconf_regs(void)
 779 {
 780         do_set_mux32((*ctrl)->control_padconf_core_base,
 781                      early_padconf, ARRAY_SIZE(early_padconf));
 782 }
 783
 784 #if defined(CONFIG_MTD_RAW_NAND)
 785 static int nand_sw_detect(void)
 786 {
 787         int rc;
 788         uchar data[2];
 789         struct udevice *dev;
 790
 791         rc = i2c_get_chip_for_busnum(NAND_PCF8575_I2C_BUS_NUM,
 792                                      NAND_PCF8575_ADDR, 0, &dev);
 793         if (rc)
 794                 return -1;
 795
 796         rc = dm_i2c_read(dev, 0, (uint8_t *)&data, sizeof(data));
 797         if (rc)
 798                 return -1;
 799
 800         /* We are only interested in P10 and P11 on PCF8575 which is equal to
 801          * bits 8 and 9.
 802          */
 803         data[1] = data[1] & 0x3;
 804
 805         /* Ensure only P11 is set and P10 is cleared. This ensures only
 806          * NAND (P10) is configured and not NOR (P11) which are both low
 807          * true signals. NAND and NOR settings should not be enabled at
 808          * the same time.
 809          */
 810         if (data[1] == 0x2)
 811                 return 0;
 812
 813         return -1;
 814 }
 815 #else
 816 int nand_sw_detect(void)
 817 {
 818         return -1;
 819 }
 820 #endif
 821
 822 #ifdef CONFIG_IODELAY_RECALIBRATION
 823 void recalibrate_iodelay(void)
 824 {
 825         struct pad_conf_entry const *pads, *delta_pads = NULL;
 826         struct iodelay_cfg_entry const *iodelay;
 827         int npads, niodelays, delta_npads = 0;
 828         int ret;
 829
 830         switch (omap_revision()) {
 831         case DRA722_ES1_0:
 832         case DRA722_ES2_0:
 833         case DRA722_ES2_1:
 834                 pads = dra72x_core_padconf_array_common;
 835                 npads = ARRAY_SIZE(dra72x_core_padconf_array_common);
 836                 if (board_is_dra71x_evm()) {
 837                         pads = dra71x_core_padconf_array;
 838                         npads = ARRAY_SIZE(dra71x_core_padconf_array);
 839                         iodelay = dra71_iodelay_cfg_array;
 840                         niodelays = ARRAY_SIZE(dra71_iodelay_cfg_array);
 841                         /* If SW8 on the EVM is set to enable NAND then
 842                          * overwrite the pins used by VOUT3 with NAND.
 843                          */
 844                         if (!nand_sw_detect()) {
 845                                 delta_pads = dra71x_nand_padconf_array;
 846                                 delta_npads =
 847                                         ARRAY_SIZE(dra71x_nand_padconf_array);
 848                         } else {
 849                                 delta_pads = dra71x_vout3_padconf_array;
 850                                 delta_npads =
 851                                         ARRAY_SIZE(dra71x_vout3_padconf_array);
 852                         }
 853
 854                 } else if (board_is_dra72x_revc_or_later()) {
 855                         delta_pads = dra72x_rgmii_padconf_array_revc;
 856                         delta_npads =
 857                                 ARRAY_SIZE(dra72x_rgmii_padconf_array_revc);
 858                         iodelay = dra72_iodelay_cfg_array_revc;
 859                         niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revc);
 860                 } else {
 861                         delta_pads = dra72x_rgmii_padconf_array_revb;
 862                         delta_npads =
 863                                 ARRAY_SIZE(dra72x_rgmii_padconf_array_revb);
 864                         iodelay = dra72_iodelay_cfg_array_revb;
 865                         niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revb);
 866                 }
 867                 break;
 868         case DRA752_ES1_0:
 869         case DRA752_ES1_1:
 870                 pads = dra74x_core_padconf_array;
 871                 npads = ARRAY_SIZE(dra74x_core_padconf_array);
 872                 iodelay = dra742_es1_1_iodelay_cfg_array;
 873                 niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array);
 874                 break;
 875         case DRA762_ACD_ES1_0:
 876         case DRA762_ES1_0:
 877                 pads = dra76x_core_padconf_array;
 878                 npads = ARRAY_SIZE(dra76x_core_padconf_array);
 879                 iodelay = dra76x_es1_0_iodelay_cfg_array;
 880                 niodelays = ARRAY_SIZE(dra76x_es1_0_iodelay_cfg_array);
 881                 break;
 882         default:
 883         case DRA752_ES2_0:
 884         case DRA762_ABZ_ES1_0:
 885                 pads = dra74x_core_padconf_array;
 886                 npads = ARRAY_SIZE(dra74x_core_padconf_array);
 887                 iodelay = dra742_es2_0_iodelay_cfg_array;
 888                 niodelays = ARRAY_SIZE(dra742_es2_0_iodelay_cfg_array);
 889                 /* Setup port1 and port2 for rgmii with 'no-id' mode */
 890                 clrset_spare_register(1, 0, RGMII2_ID_MODE_N_MASK |
 891                                       RGMII1_ID_MODE_N_MASK);
 892                 break;
 893         }
 894         /* Setup I/O isolation */
 895         ret = __recalibrate_iodelay_start();
 896         if (ret)
 897                 goto err;
 898
 899         /* Do the muxing here */
 900         do_set_mux32((*ctrl)->control_padconf_core_base, pads, npads);
 901
 902         /* Now do the weird minor deltas that should be safe */
 903         if (delta_npads)
 904                 do_set_mux32((*ctrl)->control_padconf_core_base,
 905                              delta_pads, delta_npads);
 906
 907         if (is_dra76x())
 908                 /* Set mux for MCAN instead of DCAN1 */
 909                 clrsetbits_le32((*ctrl)->control_core_control_spare_rw,
 910                                 MCAN_SEL_ALT_MASK, MCAN_SEL);
 911
 912         /* Setup IOdelay configuration */
 913         ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays);
 914 err:
 915         /* Closeup.. remove isolation */
 916         __recalibrate_iodelay_end(ret);
 917 }
 918 #endif
 919
 920 #if defined(CONFIG_MMC)
 921 int board_mmc_init(bd_t *bis)
 922 {
 923         omap_mmc_init(0, 0, 0, -1, -1);
 924         omap_mmc_init(1, 0, 0, -1, -1);
 925         return 0;
 926 }
 927
 928 void board_mmc_poweron_ldo(uint voltage)
 929 {
 930         if (board_is_dra71x_evm()) {
 931                 if (voltage == LDO_VOLT_3V0)
 932                         voltage = 0x19;
 933                 else if (voltage == LDO_VOLT_1V8)
 934                         voltage = 0xa;
 935                 lp873x_mmc1_poweron_ldo(voltage);
 936         } else if (board_is_dra76x_evm()) {
 937                 palmas_mmc1_poweron_ldo(LDO4_VOLTAGE, LDO4_CTRL, voltage);
 938         } else {
 939                 palmas_mmc1_poweron_ldo(LDO1_VOLTAGE, LDO1_CTRL, voltage);
 940         }
 941 }
 942
 943 static const struct mmc_platform_fixups dra7x_es1_1_mmc1_fixups = {
 944         .hw_rev = "rev11",
 945         .unsupported_caps = MMC_CAP(MMC_HS_200) |
 946                             MMC_CAP(UHS_SDR104),
 947         .max_freq = 96000000,
 948 };
 949
 950 static const struct mmc_platform_fixups dra7x_es1_1_mmc23_fixups = {
 951         .hw_rev = "rev11",
 952         .unsupported_caps = MMC_CAP(MMC_HS_200) |
 953                             MMC_CAP(UHS_SDR104) |
 954                             MMC_CAP(UHS_SDR50),
 955         .max_freq = 48000000,
 956 };
 957
 958 const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
 959 {
 960         switch (omap_revision()) {
 961         case DRA752_ES1_0:
 962         case DRA752_ES1_1:
 963                 if (addr == OMAP_HSMMC1_BASE)
 964                         return &dra7x_es1_1_mmc1_fixups;
 965                 else
 966                         return &dra7x_es1_1_mmc23_fixups;
 967         default:
 968                 return NULL;
 969         }
 970 }
 971 #endif
 972
 973 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
 974 int spl_start_uboot(void)
 975 {
 976         /* break into full u-boot on 'c' */
 977         if (serial_tstc() && serial_getc() == 'c')
 978                 return 1;
 979
 980 #ifdef CONFIG_SPL_ENV_SUPPORT
 981         env_init();
 982         env_load();
 983         if (env_get_yesno("boot_os") != 1)
 984                 return 1;
 985 #endif
 986
 987         return 0;
 988 }
 989 #endif
 990
 991 #ifdef CONFIG_BOARD_EARLY_INIT_F
 992 /* VTT regulator enable */
 993 static inline void vtt_regulator_enable(void)
 994 {
 995         if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
 996                 return;
 997
 998         /* Do not enable VTT for DRA722 or DRA76x */
 999         if (is_dra72x() || is_dra76x())
1000                 return;
1001
1002         /*
1003          * EVM Rev G and later use gpio7_11 for DDR3 termination.
1004          * This is safe enough to do on older revs.
1005          */
1006         gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
1007         gpio_direction_output(GPIO_DDR_VTT_EN, 1);
1008 }
1009
1010 int board_early_init_f(void)
1011 {
1012         vtt_regulator_enable();
1013         return 0;
1014 }
1015 #endif
1016
1017 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
1018 int ft_board_setup(void *blob, bd_t *bd)
1019 {
1020         ft_cpu_setup(blob, bd);
1021
1022         return 0;
1023 }
1024 #endif
1025
1026 #ifdef CONFIG_SPL_LOAD_FIT
1027 int board_fit_config_name_match(const char *name)
1028 {
1029         if (is_dra72x()) {
1030                 if (board_is_dra71x_evm()) {
1031                         if (!strcmp(name, "dra71-evm"))
1032                                 return 0;
1033                 }else if(board_is_dra72x_revc_or_later()) {
1034                         if (!strcmp(name, "dra72-evm-revc"))
1035                                 return 0;
1036                 } else if (!strcmp(name, "dra72-evm")) {
1037                         return 0;
1038                 }
1039         } else if (is_dra76x_acd() && !strcmp(name, "dra76-evm")) {
1040                 return 0;
1041         } else if (!is_dra72x() && !is_dra76x_acd() &&
1042                    !strcmp(name, "dra7-evm")) {
1043                 return 0;
1044         }
1045
1046         return -1;
1047 }
1048 #endif
1049
1050 #if CONFIG_IS_ENABLED(FASTBOOT) && !CONFIG_IS_ENABLED(ENV_IS_NOWHERE)
1051 int fastboot_set_reboot_flag(void)
1052 {
1053         printf("Setting reboot to fastboot flag ...\n");
1054         env_set("dofastboot", "1");
1055         env_save();
1056         return 0;
1057 }
1058 #endif
1059
1060 #ifdef CONFIG_TI_SECURE_DEVICE
1061 void board_fit_image_post_process(void **p_image, size_t *p_size)
1062 {
1063         secure_boot_verify_image(p_image, p_size);
1064 }
1065
1066 void board_tee_image_process(ulong tee_image, size_t tee_size)
1067 {
1068         secure_tee_install((u32)tee_image);
1069 }
1070
1071 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
1072 #endif