board/ti/dra7xx/evm.c

   1 /*
   2  * (C) Copyright 2013
   3  * Texas Instruments Incorporated, <www.ti.com>
   4  *
   5  * Lokesh Vutla <lokeshvutla@ti.com>
   6  *
   7  * Based on previous work by:
   8  * Aneesh V       <aneesh@ti.com>
   9  * Steve Sakoman  <steve@sakoman.com>
  10  *
  11  * SPDX-License-Identifier:     GPL-2.0+
  12  */
  13 #include <common.h>
  14 #include <palmas.h>
  15 #include <sata.h>
  16 #include <linux/string.h>
  17 #include <asm/gpio.h>
  18 #include <usb.h>
  19 #include <linux/usb/gadget.h>
  20 #include <asm/arch/gpio.h>
  21 #include <asm/arch/dra7xx_iodelay.h>
  22 #include <asm/emif.h>
  23 #include <asm/arch/sys_proto.h>
  24 #include <asm/arch/mmc_host_def.h>
  25 #include <asm/arch/sata.h>
  26 #include <environment.h>
  27 #include <dwc3-uboot.h>
  28 #include <dwc3-omap-uboot.h>
  29 #include <ti-usb-phy-uboot.h>
  30 #include <miiphy.h>
  31
  32 #include "mux_data.h"
  33 #include "../common/board_detect.h"
  34
  35 #define board_is_dra74x_evm()           board_ti_is("5777xCPU")
  36 #define board_is_dra72x_evm()           board_ti_is("DRA72x-T")
  37 #define board_is_dra74x_revh_or_later() board_is_dra74x_evm() &&        \
  38                                 (strncmp("H", board_ti_get_rev(), 1) <= 0)
  39 #define board_is_dra72x_revc_or_later() board_is_dra72x_evm() &&        \
  40                                 (strncmp("C", board_ti_get_rev(), 1) <= 0)
  41 #define board_ti_get_emif_size()        board_ti_get_emif1_size() +     \
  42                                         board_ti_get_emif2_size()
  43
  44 #ifdef CONFIG_DRIVER_TI_CPSW
  45 #include <cpsw.h>
  46 #endif
  47
  48 DECLARE_GLOBAL_DATA_PTR;
  49
  50 /* GPIO 7_11 */
  51 #define GPIO_DDR_VTT_EN 203
  52
  53 #define SYSINFO_BOARD_NAME_MAX_LEN      37
  54
  55 const struct omap_sysinfo sysinfo = {
  56         "Board: UNKNOWN(DRA7 EVM) REV UNKNOWN\n"
  57 };
  58
  59 static const struct emif_regs emif1_ddr3_532_mhz_1cs = {
  60         .sdram_config_init              = 0x61851ab2,
  61         .sdram_config                   = 0x61851ab2,
  62         .sdram_config2                  = 0x08000000,
  63         .ref_ctrl                       = 0x000040F1,
  64         .ref_ctrl_final                 = 0x00001035,
  65         .sdram_tim1                     = 0xCCCF36B3,
  66         .sdram_tim2                     = 0x308F7FDA,
  67         .sdram_tim3                     = 0x427F88A8,
  68         .read_idle_ctrl                 = 0x00050000,
  69         .zq_config                      = 0x0007190B,
  70         .temp_alert_config              = 0x00000000,
  71         .emif_ddr_phy_ctlr_1_init       = 0x0024400B,
  72         .emif_ddr_phy_ctlr_1            = 0x0E24400B,
  73         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
  74         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
  75         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
  76         .emif_ddr_ext_phy_ctrl_4        = 0x009B009B,
  77         .emif_ddr_ext_phy_ctrl_5        = 0x009E009E,
  78         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
  79         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
  80         .emif_rd_wr_lvl_ctl             = 0x00000000,
  81         .emif_rd_wr_exec_thresh         = 0x00000305
  82 };
  83
  84 static const struct emif_regs emif2_ddr3_532_mhz_1cs = {
  85         .sdram_config_init              = 0x61851B32,
  86         .sdram_config                   = 0x61851B32,
  87         .sdram_config2                  = 0x08000000,
  88         .ref_ctrl                       = 0x000040F1,
  89         .ref_ctrl_final                 = 0x00001035,
  90         .sdram_tim1                     = 0xCCCF36B3,
  91         .sdram_tim2                     = 0x308F7FDA,
  92         .sdram_tim3                     = 0x427F88A8,
  93         .read_idle_ctrl                 = 0x00050000,
  94         .zq_config                      = 0x0007190B,
  95         .temp_alert_config              = 0x00000000,
  96         .emif_ddr_phy_ctlr_1_init       = 0x0024400B,
  97         .emif_ddr_phy_ctlr_1            = 0x0E24400B,
  98         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
  99         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 100         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 101         .emif_ddr_ext_phy_ctrl_4        = 0x009B009B,
 102         .emif_ddr_ext_phy_ctrl_5        = 0x009E009E,
 103         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 104         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 105         .emif_rd_wr_lvl_ctl             = 0x00000000,
 106         .emif_rd_wr_exec_thresh         = 0x00000305
 107 };
 108
 109 static const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
 110         .sdram_config_init              = 0x61862B32,
 111         .sdram_config                   = 0x61862B32,
 112         .sdram_config2                  = 0x08000000,
 113         .ref_ctrl                       = 0x0000514C,
 114         .ref_ctrl_final                 = 0x0000144A,
 115         .sdram_tim1                     = 0xD113781C,
 116         .sdram_tim2                     = 0x30717FE3,
 117         .sdram_tim3                     = 0x409F86A8,
 118         .read_idle_ctrl                 = 0x00050000,
 119         .zq_config                      = 0x5007190B,
 120         .temp_alert_config              = 0x00000000,
 121         .emif_ddr_phy_ctlr_1_init       = 0x0024400D,
 122         .emif_ddr_phy_ctlr_1            = 0x0E24400D,
 123         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 124         .emif_ddr_ext_phy_ctrl_2        = 0x00A400A4,
 125         .emif_ddr_ext_phy_ctrl_3        = 0x00A900A9,
 126         .emif_ddr_ext_phy_ctrl_4        = 0x00B000B0,
 127         .emif_ddr_ext_phy_ctrl_5        = 0x00B000B0,
 128         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 129         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 130         .emif_rd_wr_lvl_ctl             = 0x00000000,
 131         .emif_rd_wr_exec_thresh         = 0x00000305
 132 };
 133
 134 const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es2 = {
 135         .sdram_config_init              = 0x61862BB2,
 136         .sdram_config                   = 0x61862BB2,
 137         .sdram_config2                  = 0x00000000,
 138         .ref_ctrl                       = 0x0000514D,
 139         .ref_ctrl_final                 = 0x0000144A,
 140         .sdram_tim1                     = 0xD1137824,
 141         .sdram_tim2                     = 0x30B37FE3,
 142         .sdram_tim3                     = 0x409F8AD8,
 143         .read_idle_ctrl                 = 0x00050000,
 144         .zq_config                      = 0x5007190B,
 145         .temp_alert_config              = 0x00000000,
 146         .emif_ddr_phy_ctlr_1_init       = 0x0824400E,
 147         .emif_ddr_phy_ctlr_1            = 0x0E24400E,
 148         .emif_ddr_ext_phy_ctrl_1        = 0x04040100,
 149         .emif_ddr_ext_phy_ctrl_2        = 0x006B009F,
 150         .emif_ddr_ext_phy_ctrl_3        = 0x006B00A2,
 151         .emif_ddr_ext_phy_ctrl_4        = 0x006B00A8,
 152         .emif_ddr_ext_phy_ctrl_5        = 0x006B00A8,
 153         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 154         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 155         .emif_rd_wr_lvl_ctl             = 0x00000000,
 156         .emif_rd_wr_exec_thresh         = 0x00000305
 157 };
 158
 159 const struct emif_regs emif1_ddr3_532_mhz_1cs_2G = {
 160         .sdram_config_init              = 0x61851ab2,
 161         .sdram_config                   = 0x61851ab2,
 162         .sdram_config2                  = 0x08000000,
 163         .ref_ctrl                       = 0x000040F1,
 164         .ref_ctrl_final                 = 0x00001035,
 165         .sdram_tim1                     = 0xCCCF36B3,
 166         .sdram_tim2                     = 0x30BF7FDA,
 167         .sdram_tim3                     = 0x427F8BA8,
 168         .read_idle_ctrl                 = 0x00050000,
 169         .zq_config                      = 0x0007190B,
 170         .temp_alert_config              = 0x00000000,
 171         .emif_ddr_phy_ctlr_1_init       = 0x0024400B,
 172         .emif_ddr_phy_ctlr_1            = 0x0E24400B,
 173         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 174         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 175         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 176         .emif_ddr_ext_phy_ctrl_4        = 0x009B009B,
 177         .emif_ddr_ext_phy_ctrl_5        = 0x009E009E,
 178         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 179         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 180         .emif_rd_wr_lvl_ctl             = 0x00000000,
 181         .emif_rd_wr_exec_thresh         = 0x00000305
 182 };
 183
 184 const struct emif_regs emif2_ddr3_532_mhz_1cs_2G = {
 185         .sdram_config_init              = 0x61851B32,
 186         .sdram_config                   = 0x61851B32,
 187         .sdram_config2                  = 0x08000000,
 188         .ref_ctrl                       = 0x000040F1,
 189         .ref_ctrl_final                 = 0x00001035,
 190         .sdram_tim1                     = 0xCCCF36B3,
 191         .sdram_tim2                     = 0x308F7FDA,
 192         .sdram_tim3                     = 0x427F88A8,
 193         .read_idle_ctrl                 = 0x00050000,
 194         .zq_config                      = 0x0007190B,
 195         .temp_alert_config              = 0x00000000,
 196         .emif_ddr_phy_ctlr_1_init       = 0x0024400B,
 197         .emif_ddr_phy_ctlr_1            = 0x0E24400B,
 198         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 199         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 200         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 201         .emif_ddr_ext_phy_ctrl_4        = 0x009B009B,
 202         .emif_ddr_ext_phy_ctrl_5        = 0x009E009E,
 203         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 204         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 205         .emif_rd_wr_lvl_ctl             = 0x00000000,
 206         .emif_rd_wr_exec_thresh         = 0x00000305
 207 };
 208
 209 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 210 {
 211         u64 ram_size;
 212
 213         ram_size = board_ti_get_emif_size();
 214
 215         switch (omap_revision()) {
 216         case DRA752_ES1_0:
 217         case DRA752_ES1_1:
 218         case DRA752_ES2_0:
 219                 switch (emif_nr) {
 220                 case 1:
 221                         if (ram_size > CONFIG_MAX_MEM_MAPPED)
 222                                 *regs = &emif1_ddr3_532_mhz_1cs_2G;
 223                         else
 224                                 *regs = &emif1_ddr3_532_mhz_1cs;
 225                         break;
 226                 case 2:
 227                         if (ram_size > CONFIG_MAX_MEM_MAPPED)
 228                                 *regs = &emif2_ddr3_532_mhz_1cs_2G;
 229                         else
 230                                 *regs = &emif2_ddr3_532_mhz_1cs;
 231                         break;
 232                 }
 233                 break;
 234         case DRA722_ES1_0:
 235         case DRA722_ES2_0:
 236                 if (ram_size < CONFIG_MAX_MEM_MAPPED)
 237                         *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1;
 238                 else
 239                         *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es2;
 240                 break;
 241         default:
 242                 *regs = &emif1_ddr3_532_mhz_1cs;
 243         }
 244 }
 245
 246 static const struct dmm_lisa_map_regs lisa_map_dra7_1536MB = {
 247         .dmm_lisa_map_0 = 0x0,
 248         .dmm_lisa_map_1 = 0x80640300,
 249         .dmm_lisa_map_2 = 0xC0500220,
 250         .dmm_lisa_map_3 = 0xFF020100,
 251         .is_ma_present  = 0x1
 252 };
 253
 254 static const struct dmm_lisa_map_regs lisa_map_2G_x_2 = {
 255         .dmm_lisa_map_0 = 0x0,
 256         .dmm_lisa_map_1 = 0x0,
 257         .dmm_lisa_map_2 = 0x80600100,
 258         .dmm_lisa_map_3 = 0xFF020100,
 259         .is_ma_present  = 0x1
 260 };
 261
 262 const struct dmm_lisa_map_regs lisa_map_dra7_2GB = {
 263         .dmm_lisa_map_0 = 0x0,
 264         .dmm_lisa_map_1 = 0x0,
 265         .dmm_lisa_map_2 = 0x80740300,
 266         .dmm_lisa_map_3 = 0xFF020100,
 267         .is_ma_present  = 0x1
 268 };
 269
 270 /*
 271  * DRA722 EVM EMIF1 2GB CONFIGURATION
 272  * EMIF1 4 devices of 512Mb x 8 Micron
 273  */
 274 const struct dmm_lisa_map_regs lisa_map_2G_x_4 = {
 275         .dmm_lisa_map_0 = 0x0,
 276         .dmm_lisa_map_1 = 0x0,
 277         .dmm_lisa_map_2 = 0x80700100,
 278         .dmm_lisa_map_3 = 0xFF020100,
 279         .is_ma_present  = 0x1
 280 };
 281
 282 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
 283 {
 284         u64 ram_size;
 285
 286         ram_size = board_ti_get_emif_size();
 287
 288         switch (omap_revision()) {
 289         case DRA752_ES1_0:
 290         case DRA752_ES1_1:
 291         case DRA752_ES2_0:
 292                 if (ram_size > CONFIG_MAX_MEM_MAPPED)
 293                         *dmm_lisa_regs = &lisa_map_dra7_2GB;
 294                 else
 295                         *dmm_lisa_regs = &lisa_map_dra7_1536MB;
 296                 break;
 297         case DRA722_ES1_0:
 298         case DRA722_ES2_0:
 299         default:
 300                 if (ram_size < CONFIG_MAX_MEM_MAPPED)
 301                         *dmm_lisa_regs = &lisa_map_2G_x_2;
 302                 else
 303                         *dmm_lisa_regs = &lisa_map_2G_x_4;
 304                 break;
 305         }
 306 }
 307
 308 /**
 309  * @brief board_init
 310  *
 311  * @return 0
 312  */
 313 int board_init(void)
 314 {
 315         gpmc_init();
 316         gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
 317
 318         return 0;
 319 }
 320
 321 void dram_init_banksize(void)
 322 {
 323         u64 ram_size;
 324
 325         ram_size = board_ti_get_emif_size();
 326
 327         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 328         gd->bd->bi_dram[0].size = get_effective_memsize();
 329         if (ram_size > CONFIG_MAX_MEM_MAPPED) {
 330                 gd->bd->bi_dram[1].start = 0x200000000;
 331                 gd->bd->bi_dram[1].size = ram_size - CONFIG_MAX_MEM_MAPPED;
 332         }
 333 }
 334
 335 int board_late_init(void)
 336 {
 337 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 338         char *name = "unknown";
 339
 340         if (is_dra72x())
 341                 name = "dra72x";
 342         else
 343                 name = "dra7xx";
 344
 345         set_board_info_env(name);
 346
 347         omap_die_id_serial();
 348 #endif
 349         return 0;
 350 }
 351
 352 #ifdef CONFIG_SPL_BUILD
 353 void do_board_detect(void)
 354 {
 355         int rc;
 356
 357         rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
 358                                     CONFIG_EEPROM_CHIP_ADDRESS);
 359         if (rc)
 360                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 361 }
 362
 363 #else
 364
 365 void do_board_detect(void)
 366 {
 367         char *bname = NULL;
 368         int rc;
 369
 370         rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
 371                                     CONFIG_EEPROM_CHIP_ADDRESS);
 372         if (rc)
 373                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 374
 375         if (board_is_dra74x_evm()) {
 376                 bname = "DRA74x EVM";
 377         } else if (board_is_dra72x_evm()) {
 378                 bname = "DRA72x EVM";
 379         } else {
 380                 /* If EEPROM is not populated */
 381                 if (is_dra72x())
 382                         bname = "DRA72x EVM";
 383                 else
 384                         bname = "DRA74x EVM";
 385         }
 386
 387         if (bname)
 388                 snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
 389                          "Board: %s REV %s\n", bname, board_ti_get_rev());
 390 }
 391 #endif  /* CONFIG_SPL_BUILD */
 392
 393 void set_muxconf_regs(void)
 394 {
 395         do_set_mux32((*ctrl)->control_padconf_core_base,
 396                      early_padconf, ARRAY_SIZE(early_padconf));
 397 }
 398
 399 #ifdef CONFIG_IODELAY_RECALIBRATION
 400 void recalibrate_iodelay(void)
 401 {
 402         struct pad_conf_entry const *pads, *delta_pads = NULL;
 403         struct iodelay_cfg_entry const *iodelay;
 404         int npads, niodelays, delta_npads = 0;
 405         int ret;
 406
 407         switch (omap_revision()) {
 408         case DRA722_ES1_0:
 409         case DRA722_ES2_0:
 410                 pads = dra72x_core_padconf_array_common;
 411                 npads = ARRAY_SIZE(dra72x_core_padconf_array_common);
 412                 if (board_is_dra72x_revc_or_later()) {
 413                         delta_pads = dra72x_rgmii_padconf_array_revc;
 414                         delta_npads =
 415                                 ARRAY_SIZE(dra72x_rgmii_padconf_array_revc);
 416                         iodelay = dra72_iodelay_cfg_array_revc;
 417                         niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revc);
 418                 } else {
 419                         delta_pads = dra72x_rgmii_padconf_array_revb;
 420                         delta_npads =
 421                                 ARRAY_SIZE(dra72x_rgmii_padconf_array_revb);
 422                         iodelay = dra72_iodelay_cfg_array_revb;
 423                         niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revb);
 424                 }
 425                 break;
 426         case DRA752_ES1_0:
 427         case DRA752_ES1_1:
 428                 pads = dra74x_core_padconf_array;
 429                 npads = ARRAY_SIZE(dra74x_core_padconf_array);
 430                 iodelay = dra742_es1_1_iodelay_cfg_array;
 431                 niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array);
 432                 break;
 433         default:
 434         case DRA752_ES2_0:
 435                 pads = dra74x_core_padconf_array;
 436                 npads = ARRAY_SIZE(dra74x_core_padconf_array);
 437                 iodelay = dra742_es2_0_iodelay_cfg_array;
 438                 niodelays = ARRAY_SIZE(dra742_es2_0_iodelay_cfg_array);
 439                 /* Setup port1 and port2 for rgmii with 'no-id' mode */
 440                 clrset_spare_register(1, 0, RGMII2_ID_MODE_N_MASK |
 441                                       RGMII1_ID_MODE_N_MASK);
 442                 break;
 443         }
 444         /* Setup I/O isolation */
 445         ret = __recalibrate_iodelay_start();
 446         if (ret)
 447                 goto err;
 448
 449         /* Do the muxing here */
 450         do_set_mux32((*ctrl)->control_padconf_core_base, pads, npads);
 451
 452         /* Now do the weird minor deltas that should be safe */
 453         if (delta_npads)
 454                 do_set_mux32((*ctrl)->control_padconf_core_base,
 455                              delta_pads, delta_npads);
 456
 457         /* Setup IOdelay configuration */
 458         ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays);
 459 err:
 460         /* Closeup.. remove isolation */
 461         __recalibrate_iodelay_end(ret);
 462 }
 463 #endif
 464
 465 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
 466 int board_mmc_init(bd_t *bis)
 467 {
 468         omap_mmc_init(0, 0, 0, -1, -1);
 469         omap_mmc_init(1, 0, 0, -1, -1);
 470         return 0;
 471 }
 472 #endif
 473
 474 #ifdef CONFIG_USB_DWC3
 475 static struct dwc3_device usb_otg_ss1 = {
 476         .maximum_speed = USB_SPEED_SUPER,
 477         .base = DRA7_USB_OTG_SS1_BASE,
 478         .tx_fifo_resize = false,
 479         .index = 0,
 480 };
 481
 482 static struct dwc3_omap_device usb_otg_ss1_glue = {
 483         .base = (void *)DRA7_USB_OTG_SS1_GLUE_BASE,
 484         .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
 485         .index = 0,
 486 };
 487
 488 static struct ti_usb_phy_device usb_phy1_device = {
 489         .pll_ctrl_base = (void *)DRA7_USB3_PHY1_PLL_CTRL,
 490         .usb2_phy_power = (void *)DRA7_USB2_PHY1_POWER,
 491         .usb3_phy_power = (void *)DRA7_USB3_PHY1_POWER,
 492         .index = 0,
 493 };
 494
 495 static struct dwc3_device usb_otg_ss2 = {
 496         .maximum_speed = USB_SPEED_SUPER,
 497         .base = DRA7_USB_OTG_SS2_BASE,
 498         .tx_fifo_resize = false,
 499         .index = 1,
 500 };
 501
 502 static struct dwc3_omap_device usb_otg_ss2_glue = {
 503         .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE,
 504         .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
 505         .index = 1,
 506 };
 507
 508 static struct ti_usb_phy_device usb_phy2_device = {
 509         .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER,
 510         .index = 1,
 511 };
 512
 513 int board_usb_init(int index, enum usb_init_type init)
 514 {
 515         enable_usb_clocks(index);
 516         switch (index) {
 517         case 0:
 518                 if (init == USB_INIT_DEVICE) {
 519                         usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
 520                         usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
 521                 } else {
 522                         usb_otg_ss1.dr_mode = USB_DR_MODE_HOST;
 523                         usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
 524                 }
 525
 526                 ti_usb_phy_uboot_init(&usb_phy1_device);
 527                 dwc3_omap_uboot_init(&usb_otg_ss1_glue);
 528                 dwc3_uboot_init(&usb_otg_ss1);
 529                 break;
 530         case 1:
 531                 if (init == USB_INIT_DEVICE) {
 532                         usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
 533                         usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
 534                 } else {
 535                         usb_otg_ss2.dr_mode = USB_DR_MODE_HOST;
 536                         usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
 537                 }
 538
 539                 ti_usb_phy_uboot_init(&usb_phy2_device);
 540                 dwc3_omap_uboot_init(&usb_otg_ss2_glue);
 541                 dwc3_uboot_init(&usb_otg_ss2);
 542                 break;
 543         default:
 544                 printf("Invalid Controller Index\n");
 545         }
 546
 547         return 0;
 548 }
 549
 550 int board_usb_cleanup(int index, enum usb_init_type init)
 551 {
 552         switch (index) {
 553         case 0:
 554         case 1:
 555                 ti_usb_phy_uboot_exit(index);
 556                 dwc3_uboot_exit(index);
 557                 dwc3_omap_uboot_exit(index);
 558                 break;
 559         default:
 560                 printf("Invalid Controller Index\n");
 561         }
 562         disable_usb_clocks(index);
 563         return 0;
 564 }
 565
 566 int usb_gadget_handle_interrupts(int index)
 567 {
 568         u32 status;
 569
 570         status = dwc3_omap_uboot_interrupt_status(index);
 571         if (status)
 572                 dwc3_uboot_handle_interrupt(index);
 573
 574         return 0;
 575 }
 576 #endif
 577
 578 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
 579 int spl_start_uboot(void)
 580 {
 581         /* break into full u-boot on 'c' */
 582         if (serial_tstc() && serial_getc() == 'c')
 583                 return 1;
 584
 585 #ifdef CONFIG_SPL_ENV_SUPPORT
 586         env_init();
 587         env_relocate_spec();
 588         if (getenv_yesno("boot_os") != 1)
 589                 return 1;
 590 #endif
 591
 592         return 0;
 593 }
 594 #endif
 595
 596 #ifdef CONFIG_DRIVER_TI_CPSW
 597 extern u32 *const omap_si_rev;
 598
 599 static void cpsw_control(int enabled)
 600 {
 601         /* VTP can be added here */
 602
 603         return;
 604 }
 605
 606 static struct cpsw_slave_data cpsw_slaves[] = {
 607         {
 608                 .slave_reg_ofs  = 0x208,
 609                 .sliver_reg_ofs = 0xd80,
 610                 .phy_addr       = 2,
 611         },
 612         {
 613                 .slave_reg_ofs  = 0x308,
 614                 .sliver_reg_ofs = 0xdc0,
 615                 .phy_addr       = 3,
 616         },
 617 };
 618
 619 static struct cpsw_platform_data cpsw_data = {
 620         .mdio_base              = CPSW_MDIO_BASE,
 621         .cpsw_base              = CPSW_BASE,
 622         .mdio_div               = 0xff,
 623         .channels               = 8,
 624         .cpdma_reg_ofs          = 0x800,
 625         .slaves                 = 2,
 626         .slave_data             = cpsw_slaves,
 627         .ale_reg_ofs            = 0xd00,
 628         .ale_entries            = 1024,
 629         .host_port_reg_ofs      = 0x108,
 630         .hw_stats_reg_ofs       = 0x900,
 631         .bd_ram_ofs             = 0x2000,
 632         .mac_control            = (1 << 5),
 633         .control                = cpsw_control,
 634         .host_port_num          = 0,
 635         .version                = CPSW_CTRL_VERSION_2,
 636 };
 637
 638 int board_eth_init(bd_t *bis)
 639 {
 640         int ret;
 641         uint8_t mac_addr[6];
 642         uint32_t mac_hi, mac_lo;
 643         uint32_t ctrl_val;
 644
 645         /* try reading mac address from efuse */
 646         mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
 647         mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
 648         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
 649         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 650         mac_addr[2] = mac_hi & 0xFF;
 651         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
 652         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
 653         mac_addr[5] = mac_lo & 0xFF;
 654
 655         if (!getenv("ethaddr")) {
 656                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
 657
 658                 if (is_valid_ethaddr(mac_addr))
 659                         eth_setenv_enetaddr("ethaddr", mac_addr);
 660         }
 661
 662         mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
 663         mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
 664         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
 665         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 666         mac_addr[2] = mac_hi & 0xFF;
 667         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
 668         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
 669         mac_addr[5] = mac_lo & 0xFF;
 670
 671         if (!getenv("eth1addr")) {
 672                 if (is_valid_ethaddr(mac_addr))
 673                         eth_setenv_enetaddr("eth1addr", mac_addr);
 674         }
 675
 676         ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
 677         ctrl_val |= 0x22;
 678         writel(ctrl_val, (*ctrl)->control_core_control_io1);
 679
 680         if (*omap_si_rev == DRA722_ES1_0)
 681                 cpsw_data.active_slave = 1;
 682
 683         if (board_is_dra72x_revc_or_later()) {
 684                 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII_ID;
 685                 cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII_ID;
 686         }
 687
 688         ret = cpsw_register(&cpsw_data);
 689         if (ret < 0)
 690                 printf("Error %d registering CPSW switch\n", ret);
 691
 692         return ret;
 693 }
 694 #endif
 695
 696 #ifdef CONFIG_BOARD_EARLY_INIT_F
 697 /* VTT regulator enable */
 698 static inline void vtt_regulator_enable(void)
 699 {
 700         if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
 701                 return;
 702
 703         /* Do not enable VTT for DRA722 */
 704         if (is_dra72x())
 705                 return;
 706
 707         /*
 708          * EVM Rev G and later use gpio7_11 for DDR3 termination.
 709          * This is safe enough to do on older revs.
 710          */
 711         gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
 712         gpio_direction_output(GPIO_DDR_VTT_EN, 1);
 713 }
 714
 715 int board_early_init_f(void)
 716 {
 717         vtt_regulator_enable();
 718         return 0;
 719 }
 720 #endif
 721
 722 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 723 int ft_board_setup(void *blob, bd_t *bd)
 724 {
 725         ft_cpu_setup(blob, bd);
 726
 727         return 0;
 728 }
 729 #endif
 730
 731 #ifdef CONFIG_SPL_LOAD_FIT
 732 int board_fit_config_name_match(const char *name)
 733 {
 734         if (is_dra72x() && !strcmp(name, "dra72-evm"))
 735                 return 0;
 736         else if (!is_dra72x() && !strcmp(name, "dra7-evm"))
 737                 return 0;
 738         else
 739                 return -1;
 740 }
 741 #endif