3 * Texas Instruments Incorporated, <www.ti.com>
5 * Lokesh Vutla <lokeshvutla@ti.com>
7 * Based on previous work by:
8 * Aneesh V <aneesh@ti.com>
9 * Steve Sakoman <steve@sakoman.com>
11 * SPDX-License-Identifier: GPL-2.0+
16 #include <linux/string.h>
19 #include <linux/usb/gadget.h>
20 #include <asm/omap_common.h>
21 #include <asm/omap_sec_common.h>
22 #include <asm/arch/gpio.h>
23 #include <asm/arch/dra7xx_iodelay.h>
25 #include <asm/arch/sys_proto.h>
26 #include <asm/arch/mmc_host_def.h>
27 #include <asm/arch/sata.h>
28 #include <environment.h>
29 #include <dwc3-uboot.h>
30 #include <dwc3-omap-uboot.h>
31 #include <ti-usb-phy-uboot.h>
35 #include "../common/board_detect.h"
37 #define board_is_dra74x_evm() board_ti_is("5777xCPU")
38 #define board_is_dra72x_evm() board_ti_is("DRA72x-T")
39 #define board_is_dra74x_revh_or_later() (board_is_dra74x_evm() && \
40 (strncmp("H", board_ti_get_rev(), 1) <= 0))
41 #define board_is_dra72x_revc_or_later() (board_is_dra72x_evm() && \
42 (strncmp("C", board_ti_get_rev(), 1) <= 0))
43 #define board_ti_get_emif_size() board_ti_get_emif1_size() + \
44 board_ti_get_emif2_size()
46 #ifdef CONFIG_DRIVER_TI_CPSW
50 DECLARE_GLOBAL_DATA_PTR;
53 #define GPIO_DDR_VTT_EN 203
55 #define SYSINFO_BOARD_NAME_MAX_LEN 37
57 const struct omap_sysinfo sysinfo = {
58 "Board: UNKNOWN(DRA7 EVM) REV UNKNOWN\n"
61 static const struct emif_regs emif1_ddr3_532_mhz_1cs = {
62 .sdram_config_init = 0x61851ab2,
63 .sdram_config = 0x61851ab2,
64 .sdram_config2 = 0x08000000,
65 .ref_ctrl = 0x000040F1,
66 .ref_ctrl_final = 0x00001035,
67 .sdram_tim1 = 0xCCCF36B3,
68 .sdram_tim2 = 0x308F7FDA,
69 .sdram_tim3 = 0x427F88A8,
70 .read_idle_ctrl = 0x00050000,
71 .zq_config = 0x0007190B,
72 .temp_alert_config = 0x00000000,
73 .emif_ddr_phy_ctlr_1_init = 0x0024400B,
74 .emif_ddr_phy_ctlr_1 = 0x0E24400B,
75 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
76 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
77 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
78 .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
79 .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
80 .emif_rd_wr_lvl_rmp_win = 0x00000000,
81 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
82 .emif_rd_wr_lvl_ctl = 0x00000000,
83 .emif_rd_wr_exec_thresh = 0x00000305
86 static const struct emif_regs emif2_ddr3_532_mhz_1cs = {
87 .sdram_config_init = 0x61851B32,
88 .sdram_config = 0x61851B32,
89 .sdram_config2 = 0x08000000,
90 .ref_ctrl = 0x000040F1,
91 .ref_ctrl_final = 0x00001035,
92 .sdram_tim1 = 0xCCCF36B3,
93 .sdram_tim2 = 0x308F7FDA,
94 .sdram_tim3 = 0x427F88A8,
95 .read_idle_ctrl = 0x00050000,
96 .zq_config = 0x0007190B,
97 .temp_alert_config = 0x00000000,
98 .emif_ddr_phy_ctlr_1_init = 0x0024400B,
99 .emif_ddr_phy_ctlr_1 = 0x0E24400B,
100 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
101 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
102 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
103 .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
104 .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
105 .emif_rd_wr_lvl_rmp_win = 0x00000000,
106 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
107 .emif_rd_wr_lvl_ctl = 0x00000000,
108 .emif_rd_wr_exec_thresh = 0x00000305
111 static const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
112 .sdram_config_init = 0x61862B32,
113 .sdram_config = 0x61862B32,
114 .sdram_config2 = 0x08000000,
115 .ref_ctrl = 0x0000514C,
116 .ref_ctrl_final = 0x0000144A,
117 .sdram_tim1 = 0xD113781C,
118 .sdram_tim2 = 0x30717FE3,
119 .sdram_tim3 = 0x409F86A8,
120 .read_idle_ctrl = 0x00050000,
121 .zq_config = 0x5007190B,
122 .temp_alert_config = 0x00000000,
123 .emif_ddr_phy_ctlr_1_init = 0x0024400D,
124 .emif_ddr_phy_ctlr_1 = 0x0E24400D,
125 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
126 .emif_ddr_ext_phy_ctrl_2 = 0x00A400A4,
127 .emif_ddr_ext_phy_ctrl_3 = 0x00A900A9,
128 .emif_ddr_ext_phy_ctrl_4 = 0x00B000B0,
129 .emif_ddr_ext_phy_ctrl_5 = 0x00B000B0,
130 .emif_rd_wr_lvl_rmp_win = 0x00000000,
131 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
132 .emif_rd_wr_lvl_ctl = 0x00000000,
133 .emif_rd_wr_exec_thresh = 0x00000305
136 const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es2 = {
137 .sdram_config_init = 0x61862BB2,
138 .sdram_config = 0x61862BB2,
139 .sdram_config2 = 0x00000000,
140 .ref_ctrl = 0x0000514D,
141 .ref_ctrl_final = 0x0000144A,
142 .sdram_tim1 = 0xD1137824,
143 .sdram_tim2 = 0x30B37FE3,
144 .sdram_tim3 = 0x409F8AD8,
145 .read_idle_ctrl = 0x00050000,
146 .zq_config = 0x5007190B,
147 .temp_alert_config = 0x00000000,
148 .emif_ddr_phy_ctlr_1_init = 0x0824400E,
149 .emif_ddr_phy_ctlr_1 = 0x0E24400E,
150 .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
151 .emif_ddr_ext_phy_ctrl_2 = 0x006B009F,
152 .emif_ddr_ext_phy_ctrl_3 = 0x006B00A2,
153 .emif_ddr_ext_phy_ctrl_4 = 0x006B00A8,
154 .emif_ddr_ext_phy_ctrl_5 = 0x006B00A8,
155 .emif_rd_wr_lvl_rmp_win = 0x00000000,
156 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
157 .emif_rd_wr_lvl_ctl = 0x00000000,
158 .emif_rd_wr_exec_thresh = 0x00000305
161 const struct emif_regs emif1_ddr3_532_mhz_1cs_2G = {
162 .sdram_config_init = 0x61851ab2,
163 .sdram_config = 0x61851ab2,
164 .sdram_config2 = 0x08000000,
165 .ref_ctrl = 0x000040F1,
166 .ref_ctrl_final = 0x00001035,
167 .sdram_tim1 = 0xCCCF36B3,
168 .sdram_tim2 = 0x30BF7FDA,
169 .sdram_tim3 = 0x427F8BA8,
170 .read_idle_ctrl = 0x00050000,
171 .zq_config = 0x0007190B,
172 .temp_alert_config = 0x00000000,
173 .emif_ddr_phy_ctlr_1_init = 0x0024400B,
174 .emif_ddr_phy_ctlr_1 = 0x0E24400B,
175 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
176 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
177 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
178 .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
179 .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
180 .emif_rd_wr_lvl_rmp_win = 0x00000000,
181 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
182 .emif_rd_wr_lvl_ctl = 0x00000000,
183 .emif_rd_wr_exec_thresh = 0x00000305
186 const struct emif_regs emif2_ddr3_532_mhz_1cs_2G = {
187 .sdram_config_init = 0x61851B32,
188 .sdram_config = 0x61851B32,
189 .sdram_config2 = 0x08000000,
190 .ref_ctrl = 0x000040F1,
191 .ref_ctrl_final = 0x00001035,
192 .sdram_tim1 = 0xCCCF36B3,
193 .sdram_tim2 = 0x308F7FDA,
194 .sdram_tim3 = 0x427F88A8,
195 .read_idle_ctrl = 0x00050000,
196 .zq_config = 0x0007190B,
197 .temp_alert_config = 0x00000000,
198 .emif_ddr_phy_ctlr_1_init = 0x0024400B,
199 .emif_ddr_phy_ctlr_1 = 0x0E24400B,
200 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
201 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
202 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
203 .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
204 .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
205 .emif_rd_wr_lvl_rmp_win = 0x00000000,
206 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
207 .emif_rd_wr_lvl_ctl = 0x00000000,
208 .emif_rd_wr_exec_thresh = 0x00000305
211 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
215 ram_size = board_ti_get_emif_size();
217 switch (omap_revision()) {
223 if (ram_size > CONFIG_MAX_MEM_MAPPED)
224 *regs = &emif1_ddr3_532_mhz_1cs_2G;
226 *regs = &emif1_ddr3_532_mhz_1cs;
229 if (ram_size > CONFIG_MAX_MEM_MAPPED)
230 *regs = &emif2_ddr3_532_mhz_1cs_2G;
232 *regs = &emif2_ddr3_532_mhz_1cs;
238 if (ram_size < CONFIG_MAX_MEM_MAPPED)
239 *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1;
241 *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es2;
244 *regs = &emif1_ddr3_532_mhz_1cs;
248 static const struct dmm_lisa_map_regs lisa_map_dra7_1536MB = {
249 .dmm_lisa_map_0 = 0x0,
250 .dmm_lisa_map_1 = 0x80640300,
251 .dmm_lisa_map_2 = 0xC0500220,
252 .dmm_lisa_map_3 = 0xFF020100,
256 static const struct dmm_lisa_map_regs lisa_map_2G_x_2 = {
257 .dmm_lisa_map_0 = 0x0,
258 .dmm_lisa_map_1 = 0x0,
259 .dmm_lisa_map_2 = 0x80600100,
260 .dmm_lisa_map_3 = 0xFF020100,
264 const struct dmm_lisa_map_regs lisa_map_dra7_2GB = {
265 .dmm_lisa_map_0 = 0x0,
266 .dmm_lisa_map_1 = 0x0,
267 .dmm_lisa_map_2 = 0x80740300,
268 .dmm_lisa_map_3 = 0xFF020100,
273 * DRA722 EVM EMIF1 2GB CONFIGURATION
274 * EMIF1 4 devices of 512Mb x 8 Micron
276 const struct dmm_lisa_map_regs lisa_map_2G_x_4 = {
277 .dmm_lisa_map_0 = 0x0,
278 .dmm_lisa_map_1 = 0x0,
279 .dmm_lisa_map_2 = 0x80700100,
280 .dmm_lisa_map_3 = 0xFF020100,
284 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
288 ram_size = board_ti_get_emif_size();
290 switch (omap_revision()) {
294 if (ram_size > CONFIG_MAX_MEM_MAPPED)
295 *dmm_lisa_regs = &lisa_map_dra7_2GB;
297 *dmm_lisa_regs = &lisa_map_dra7_1536MB;
302 if (ram_size < CONFIG_MAX_MEM_MAPPED)
303 *dmm_lisa_regs = &lisa_map_2G_x_2;
305 *dmm_lisa_regs = &lisa_map_2G_x_4;
310 struct vcores_data dra752_volts = {
311 .mpu.value = VDD_MPU_DRA7,
312 .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU,
313 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
314 .mpu.addr = TPS659038_REG_ADDR_SMPS12,
315 .mpu.pmic = &tps659038,
316 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
318 .eve.value = VDD_EVE_DRA7,
319 .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE,
320 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
321 .eve.addr = TPS659038_REG_ADDR_SMPS45,
322 .eve.pmic = &tps659038,
323 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
325 .gpu.value = VDD_GPU_DRA7,
326 .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU,
327 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
328 .gpu.addr = TPS659038_REG_ADDR_SMPS6,
329 .gpu.pmic = &tps659038,
330 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
332 .core.value = VDD_CORE_DRA7,
333 .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE,
334 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
335 .core.addr = TPS659038_REG_ADDR_SMPS7,
336 .core.pmic = &tps659038,
338 .iva.value = VDD_IVA_DRA7,
339 .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA,
340 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
341 .iva.addr = TPS659038_REG_ADDR_SMPS8,
342 .iva.pmic = &tps659038,
343 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
346 struct vcores_data dra722_volts = {
347 .mpu.value = VDD_MPU_DRA7,
348 .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU,
349 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
350 .mpu.addr = TPS65917_REG_ADDR_SMPS1,
351 .mpu.pmic = &tps659038,
352 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
354 .core.value = VDD_CORE_DRA7,
355 .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE,
356 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
357 .core.addr = TPS65917_REG_ADDR_SMPS2,
358 .core.pmic = &tps659038,
361 * The DSPEVE, GPU and IVA rails are usually grouped on DRA72x
362 * designs and powered by TPS65917 SMPS3, as on the J6Eco EVM.
364 .gpu.value = VDD_GPU_DRA7,
365 .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU,
366 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
367 .gpu.addr = TPS65917_REG_ADDR_SMPS3,
368 .gpu.pmic = &tps659038,
369 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
371 .eve.value = VDD_EVE_DRA7,
372 .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE,
373 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
374 .eve.addr = TPS65917_REG_ADDR_SMPS3,
375 .eve.pmic = &tps659038,
376 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
378 .iva.value = VDD_IVA_DRA7,
379 .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA,
380 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
381 .iva.addr = TPS65917_REG_ADDR_SMPS3,
382 .iva.pmic = &tps659038,
383 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
394 gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
399 void dram_init_banksize(void)
403 ram_size = board_ti_get_emif_size();
405 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
406 gd->bd->bi_dram[0].size = get_effective_memsize();
407 if (ram_size > CONFIG_MAX_MEM_MAPPED) {
408 gd->bd->bi_dram[1].start = 0x200000000;
409 gd->bd->bi_dram[1].size = ram_size - CONFIG_MAX_MEM_MAPPED;
413 int board_late_init(void)
415 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
416 char *name = "unknown";
419 if (board_is_dra72x_revc_or_later())
420 name = "dra72x-revc";
427 set_board_info_env(name);
429 omap_die_id_serial();
434 #ifdef CONFIG_SPL_BUILD
435 void do_board_detect(void)
439 rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
440 CONFIG_EEPROM_CHIP_ADDRESS);
442 printf("ti_i2c_eeprom_init failed %d\n", rc);
447 void do_board_detect(void)
452 rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
453 CONFIG_EEPROM_CHIP_ADDRESS);
455 printf("ti_i2c_eeprom_init failed %d\n", rc);
457 if (board_is_dra74x_evm()) {
458 bname = "DRA74x EVM";
459 } else if (board_is_dra72x_evm()) {
460 bname = "DRA72x EVM";
462 /* If EEPROM is not populated */
464 bname = "DRA72x EVM";
466 bname = "DRA74x EVM";
470 snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
471 "Board: %s REV %s\n", bname, board_ti_get_rev());
473 #endif /* CONFIG_SPL_BUILD */
475 void vcores_init(void)
477 if (board_is_dra74x_evm()) {
478 *omap_vcores = &dra752_volts;
479 } else if (board_is_dra72x_evm()) {
480 *omap_vcores = &dra722_volts;
482 /* If EEPROM is not populated */
484 *omap_vcores = &dra722_volts;
486 *omap_vcores = &dra752_volts;
490 void set_muxconf_regs(void)
492 do_set_mux32((*ctrl)->control_padconf_core_base,
493 early_padconf, ARRAY_SIZE(early_padconf));
496 #ifdef CONFIG_IODELAY_RECALIBRATION
497 void recalibrate_iodelay(void)
499 struct pad_conf_entry const *pads, *delta_pads = NULL;
500 struct iodelay_cfg_entry const *iodelay;
501 int npads, niodelays, delta_npads = 0;
504 switch (omap_revision()) {
507 pads = dra72x_core_padconf_array_common;
508 npads = ARRAY_SIZE(dra72x_core_padconf_array_common);
509 if (board_is_dra72x_revc_or_later()) {
510 delta_pads = dra72x_rgmii_padconf_array_revc;
512 ARRAY_SIZE(dra72x_rgmii_padconf_array_revc);
513 iodelay = dra72_iodelay_cfg_array_revc;
514 niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revc);
516 delta_pads = dra72x_rgmii_padconf_array_revb;
518 ARRAY_SIZE(dra72x_rgmii_padconf_array_revb);
519 iodelay = dra72_iodelay_cfg_array_revb;
520 niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revb);
525 pads = dra74x_core_padconf_array;
526 npads = ARRAY_SIZE(dra74x_core_padconf_array);
527 iodelay = dra742_es1_1_iodelay_cfg_array;
528 niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array);
532 pads = dra74x_core_padconf_array;
533 npads = ARRAY_SIZE(dra74x_core_padconf_array);
534 iodelay = dra742_es2_0_iodelay_cfg_array;
535 niodelays = ARRAY_SIZE(dra742_es2_0_iodelay_cfg_array);
536 /* Setup port1 and port2 for rgmii with 'no-id' mode */
537 clrset_spare_register(1, 0, RGMII2_ID_MODE_N_MASK |
538 RGMII1_ID_MODE_N_MASK);
541 /* Setup I/O isolation */
542 ret = __recalibrate_iodelay_start();
546 /* Do the muxing here */
547 do_set_mux32((*ctrl)->control_padconf_core_base, pads, npads);
549 /* Now do the weird minor deltas that should be safe */
551 do_set_mux32((*ctrl)->control_padconf_core_base,
552 delta_pads, delta_npads);
554 /* Setup IOdelay configuration */
555 ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays);
557 /* Closeup.. remove isolation */
558 __recalibrate_iodelay_end(ret);
562 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
563 int board_mmc_init(bd_t *bis)
565 omap_mmc_init(0, 0, 0, -1, -1);
566 omap_mmc_init(1, 0, 0, -1, -1);
571 #ifdef CONFIG_USB_DWC3
572 static struct dwc3_device usb_otg_ss1 = {
573 .maximum_speed = USB_SPEED_SUPER,
574 .base = DRA7_USB_OTG_SS1_BASE,
575 .tx_fifo_resize = false,
579 static struct dwc3_omap_device usb_otg_ss1_glue = {
580 .base = (void *)DRA7_USB_OTG_SS1_GLUE_BASE,
581 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
585 static struct ti_usb_phy_device usb_phy1_device = {
586 .pll_ctrl_base = (void *)DRA7_USB3_PHY1_PLL_CTRL,
587 .usb2_phy_power = (void *)DRA7_USB2_PHY1_POWER,
588 .usb3_phy_power = (void *)DRA7_USB3_PHY1_POWER,
592 static struct dwc3_device usb_otg_ss2 = {
593 .maximum_speed = USB_SPEED_SUPER,
594 .base = DRA7_USB_OTG_SS2_BASE,
595 .tx_fifo_resize = false,
599 static struct dwc3_omap_device usb_otg_ss2_glue = {
600 .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE,
601 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
605 static struct ti_usb_phy_device usb_phy2_device = {
606 .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER,
610 int board_usb_init(int index, enum usb_init_type init)
612 enable_usb_clocks(index);
615 if (init == USB_INIT_DEVICE) {
616 usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
617 usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
619 usb_otg_ss1.dr_mode = USB_DR_MODE_HOST;
620 usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
623 ti_usb_phy_uboot_init(&usb_phy1_device);
624 dwc3_omap_uboot_init(&usb_otg_ss1_glue);
625 dwc3_uboot_init(&usb_otg_ss1);
628 if (init == USB_INIT_DEVICE) {
629 usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
630 usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
632 usb_otg_ss2.dr_mode = USB_DR_MODE_HOST;
633 usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
636 ti_usb_phy_uboot_init(&usb_phy2_device);
637 dwc3_omap_uboot_init(&usb_otg_ss2_glue);
638 dwc3_uboot_init(&usb_otg_ss2);
641 printf("Invalid Controller Index\n");
647 int board_usb_cleanup(int index, enum usb_init_type init)
652 ti_usb_phy_uboot_exit(index);
653 dwc3_uboot_exit(index);
654 dwc3_omap_uboot_exit(index);
657 printf("Invalid Controller Index\n");
659 disable_usb_clocks(index);
663 int usb_gadget_handle_interrupts(int index)
667 status = dwc3_omap_uboot_interrupt_status(index);
669 dwc3_uboot_handle_interrupt(index);
675 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
676 int spl_start_uboot(void)
678 /* break into full u-boot on 'c' */
679 if (serial_tstc() && serial_getc() == 'c')
682 #ifdef CONFIG_SPL_ENV_SUPPORT
685 if (getenv_yesno("boot_os") != 1)
693 #ifdef CONFIG_DRIVER_TI_CPSW
694 extern u32 *const omap_si_rev;
696 static void cpsw_control(int enabled)
698 /* VTP can be added here */
703 static struct cpsw_slave_data cpsw_slaves[] = {
705 .slave_reg_ofs = 0x208,
706 .sliver_reg_ofs = 0xd80,
710 .slave_reg_ofs = 0x308,
711 .sliver_reg_ofs = 0xdc0,
716 static struct cpsw_platform_data cpsw_data = {
717 .mdio_base = CPSW_MDIO_BASE,
718 .cpsw_base = CPSW_BASE,
721 .cpdma_reg_ofs = 0x800,
723 .slave_data = cpsw_slaves,
724 .ale_reg_ofs = 0xd00,
726 .host_port_reg_ofs = 0x108,
727 .hw_stats_reg_ofs = 0x900,
728 .bd_ram_ofs = 0x2000,
729 .mac_control = (1 << 5),
730 .control = cpsw_control,
732 .version = CPSW_CTRL_VERSION_2,
735 int board_eth_init(bd_t *bis)
739 uint32_t mac_hi, mac_lo;
742 /* try reading mac address from efuse */
743 mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
744 mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
745 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
746 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
747 mac_addr[2] = mac_hi & 0xFF;
748 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
749 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
750 mac_addr[5] = mac_lo & 0xFF;
752 if (!getenv("ethaddr")) {
753 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
755 if (is_valid_ethaddr(mac_addr))
756 eth_setenv_enetaddr("ethaddr", mac_addr);
759 mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
760 mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
761 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
762 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
763 mac_addr[2] = mac_hi & 0xFF;
764 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
765 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
766 mac_addr[5] = mac_lo & 0xFF;
768 if (!getenv("eth1addr")) {
769 if (is_valid_ethaddr(mac_addr))
770 eth_setenv_enetaddr("eth1addr", mac_addr);
773 ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
775 writel(ctrl_val, (*ctrl)->control_core_control_io1);
777 if (*omap_si_rev == DRA722_ES1_0)
778 cpsw_data.active_slave = 1;
780 if (board_is_dra72x_revc_or_later()) {
781 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII_ID;
782 cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII_ID;
785 ret = cpsw_register(&cpsw_data);
787 printf("Error %d registering CPSW switch\n", ret);
793 #ifdef CONFIG_BOARD_EARLY_INIT_F
794 /* VTT regulator enable */
795 static inline void vtt_regulator_enable(void)
797 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
800 /* Do not enable VTT for DRA722 */
805 * EVM Rev G and later use gpio7_11 for DDR3 termination.
806 * This is safe enough to do on older revs.
808 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
809 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
812 int board_early_init_f(void)
814 vtt_regulator_enable();
819 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
820 int ft_board_setup(void *blob, bd_t *bd)
822 ft_cpu_setup(blob, bd);
828 #ifdef CONFIG_SPL_LOAD_FIT
829 int board_fit_config_name_match(const char *name)
832 if (board_is_dra72x_revc_or_later()) {
833 if (!strcmp(name, "dra72-evm-revc"))
835 } else if (!strcmp(name, "dra72-evm")) {
838 } else if (!is_dra72x() && !strcmp(name, "dra7-evm")) {
846 #ifdef CONFIG_TI_SECURE_DEVICE
847 void board_fit_image_post_process(void **p_image, size_t *p_size)
849 secure_boot_verify_image(p_image, p_size);