3 * Texas Instruments Incorporated, <www.ti.com>
5 * Lokesh Vutla <lokeshvutla@ti.com>
7 * Based on previous work by:
8 * Aneesh V <aneesh@ti.com>
9 * Steve Sakoman <steve@sakoman.com>
11 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/arch/sys_proto.h>
17 #include <asm/arch/mmc_host_def.h>
18 #include <asm/arch/sata.h>
19 #include <environment.h>
23 #ifdef CONFIG_DRIVER_TI_CPSW
27 DECLARE_GLOBAL_DATA_PTR;
29 const struct omap_sysinfo sysinfo = {
34 * Adjust I/O delays on the Tx control and data lines of each MAC port. This
35 * is a workaround in order to work properly with the DP83865 PHYs on the EVM.
36 * In 3COM RGMII mode this PHY applies it's own internal clock delay, so we
37 * essentially need to counteract the DRA7xx internal delay, and we do this
38 * by delaying the control and data lines. If not using this PHY, you probably
39 * don't need to do this stuff!
41 static void dra7xx_adj_io_delay(const struct io_delay *io_dly)
49 writel(CFG_IO_DELAY_UNLOCK_KEY, CFG_IO_DELAY_LOCK);
51 while(io_dly[i].addr) {
52 writel(CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK,
54 delta = io_dly[i].dly;
55 reg_val = readl(io_dly[i].addr) & 0x3ff;
56 coarse = ((reg_val >> 5) & 0x1F) + ((delta >> 5) & 0x1F);
57 coarse = (coarse > 0x1F) ? (0x1F) : (coarse);
58 fine = (reg_val & 0x1F) + (delta & 0x1F);
59 fine = (fine > 0x1F) ? (0x1F) : (fine);
60 reg_val = CFG_IO_DELAY_ACCESS_PATTERN |
61 CFG_IO_DELAY_LOCK_MASK |
62 ((coarse << 5) | (fine));
63 writel(reg_val, io_dly[i].addr);
67 writel(CFG_IO_DELAY_LOCK_KEY, CFG_IO_DELAY_LOCK);
78 gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
83 int board_late_init(void)
90 * @brief misc_init_r - Configure EVM board specific configurations
91 * such as power configurations, ethernet initialization as phase2 of
101 static void do_set_mux32(u32 base,
102 struct pad_conf_entry const *array, int size)
105 struct pad_conf_entry *pad = (struct pad_conf_entry *)array;
107 for (i = 0; i < size; i++, pad++)
108 writel(pad->val, base + pad->offset);
111 void set_muxconf_regs_essential(void)
113 do_set_mux32((*ctrl)->control_padconf_core_base,
114 core_padconf_array_essential,
115 sizeof(core_padconf_array_essential) /
116 sizeof(struct pad_conf_entry));
119 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
120 int board_mmc_init(bd_t *bis)
122 omap_mmc_init(0, 0, 0, -1, -1);
123 omap_mmc_init(1, 0, 0, -1, -1);
128 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
129 int spl_start_uboot(void)
131 /* break into full u-boot on 'c' */
132 if (serial_tstc() && serial_getc() == 'c')
135 #ifdef CONFIG_SPL_ENV_SUPPORT
138 if (getenv_yesno("boot_os") != 1)
146 #ifdef CONFIG_DRIVER_TI_CPSW
148 /* Delay value to add to calibrated value */
149 #define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8)
150 #define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8)
151 #define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2)
152 #define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0)
153 #define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0)
154 #define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8)
155 #define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8)
156 #define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2)
157 #define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0)
158 #define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0)
160 static void cpsw_control(int enabled)
162 /* VTP can be added here */
167 static struct cpsw_slave_data cpsw_slaves[] = {
169 .slave_reg_ofs = 0x208,
170 .sliver_reg_ofs = 0xd80,
174 .slave_reg_ofs = 0x308,
175 .sliver_reg_ofs = 0xdc0,
180 static struct cpsw_platform_data cpsw_data = {
181 .mdio_base = CPSW_MDIO_BASE,
182 .cpsw_base = CPSW_BASE,
185 .cpdma_reg_ofs = 0x800,
187 .slave_data = cpsw_slaves,
188 .ale_reg_ofs = 0xd00,
190 .host_port_reg_ofs = 0x108,
191 .hw_stats_reg_ofs = 0x900,
192 .bd_ram_ofs = 0x2000,
193 .mac_control = (1 << 5),
194 .control = cpsw_control,
196 .version = CPSW_CTRL_VERSION_2,
199 int board_eth_init(bd_t *bis)
203 uint32_t mac_hi, mac_lo;
205 const struct io_delay io_dly[] = {
206 {CFG_RGMII0_TXCTL, RGMII0_TXCTL_DLY_VAL},
207 {CFG_RGMII0_TXD0, RGMII0_TXD0_DLY_VAL},
208 {CFG_RGMII0_TXD1, RGMII0_TXD1_DLY_VAL},
209 {CFG_RGMII0_TXD2, RGMII0_TXD2_DLY_VAL},
210 {CFG_RGMII0_TXD3, RGMII0_TXD3_DLY_VAL},
211 {CFG_VIN2A_D13, VIN2A_D13_DLY_VAL},
212 {CFG_VIN2A_D17, VIN2A_D17_DLY_VAL},
213 {CFG_VIN2A_D16, VIN2A_D16_DLY_VAL},
214 {CFG_VIN2A_D15, VIN2A_D15_DLY_VAL},
215 {CFG_VIN2A_D14, VIN2A_D14_DLY_VAL},
219 /* Adjust IO delay for RGMII tx path */
220 dra7xx_adj_io_delay(io_dly);
222 /* try reading mac address from efuse */
223 mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
224 mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
225 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
226 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
227 mac_addr[2] = mac_hi & 0xFF;
228 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
229 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
230 mac_addr[5] = mac_lo & 0xFF;
232 if (!getenv("ethaddr")) {
233 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
235 if (is_valid_ether_addr(mac_addr))
236 eth_setenv_enetaddr("ethaddr", mac_addr);
239 mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
240 mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
241 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
242 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
243 mac_addr[2] = mac_hi & 0xFF;
244 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
245 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
246 mac_addr[5] = mac_lo & 0xFF;
248 if (!getenv("eth1addr")) {
249 if (is_valid_ether_addr(mac_addr))
250 eth_setenv_enetaddr("eth1addr", mac_addr);
253 ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
255 writel(ctrl_val, (*ctrl)->control_core_control_io1);
257 ret = cpsw_register(&cpsw_data);
259 printf("Error %d registering CPSW switch\n", ret);