board/ti/am57xx/board.c

   1 /*
   2  * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
   3  *
   4  * Author: Felipe Balbi <balbi@ti.com>
   5  *
   6  * Based on board/ti/dra7xx/evm.c
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <palmas.h>
  13 #include <sata.h>
  14 #include <usb.h>
  15 #include <asm/omap_common.h>
  16 #include <asm/omap_sec_common.h>
  17 #include <asm/emif.h>
  18 #include <asm/gpio.h>
  19 #include <asm/arch/gpio.h>
  20 #include <asm/arch/clock.h>
  21 #include <asm/arch/dra7xx_iodelay.h>
  22 #include <asm/arch/sys_proto.h>
  23 #include <asm/arch/mmc_host_def.h>
  24 #include <asm/arch/sata.h>
  25 #include <asm/arch/gpio.h>
  26 #include <asm/arch/omap.h>
  27 #include <environment.h>
  28 #include <usb.h>
  29 #include <linux/usb/gadget.h>
  30 #include <dwc3-uboot.h>
  31 #include <dwc3-omap-uboot.h>
  32 #include <ti-usb-phy-uboot.h>
  33
  34 #include "../common/board_detect.h"
  35 #include "mux_data.h"
  36
  37 #define board_is_x15()          board_ti_is("BBRDX15_")
  38 #define board_is_x15_revb1()    (board_ti_is("BBRDX15_") && \
  39                                  (strncmp("B.10", board_ti_get_rev(), 3) <= 0))
  40 #define board_is_am572x_evm()   board_ti_is("AM572PM_")
  41 #define board_is_am572x_evm_reva3()     \
  42                                 (board_ti_is("AM572PM_") && \
  43                                  (strncmp("A.30", board_ti_get_rev(), 3) <= 0))
  44 #define board_is_am572x_idk()   board_ti_is("AM572IDK")
  45
  46 #ifdef CONFIG_DRIVER_TI_CPSW
  47 #include <cpsw.h>
  48 #endif
  49
  50 DECLARE_GLOBAL_DATA_PTR;
  51
  52 /* GPIO 7_11 */
  53 #define GPIO_DDR_VTT_EN 203
  54
  55 #define SYSINFO_BOARD_NAME_MAX_LEN      45
  56
  57 const struct omap_sysinfo sysinfo = {
  58         "Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n"
  59 };
  60
  61 static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
  62         .dmm_lisa_map_3 = 0x80740300,
  63         .is_ma_present  = 0x1
  64 };
  65
  66 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
  67 {
  68         *dmm_lisa_regs = &beagle_x15_lisa_regs;
  69 }
  70
  71 static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
  72         .sdram_config_init              = 0x61851b32,
  73         .sdram_config                   = 0x61851b32,
  74         .sdram_config2                  = 0x08000000,
  75         .ref_ctrl                       = 0x000040F1,
  76         .ref_ctrl_final                 = 0x00001035,
  77         .sdram_tim1                     = 0xcccf36ab,
  78         .sdram_tim2                     = 0x308f7fda,
  79         .sdram_tim3                     = 0x409f88a8,
  80         .read_idle_ctrl                 = 0x00050000,
  81         .zq_config                      = 0x5007190b,
  82         .temp_alert_config              = 0x00000000,
  83         .emif_ddr_phy_ctlr_1_init       = 0x0024400b,
  84         .emif_ddr_phy_ctlr_1            = 0x0e24400b,
  85         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
  86         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
  87         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
  88         .emif_ddr_ext_phy_ctrl_4        = 0x009b009b,
  89         .emif_ddr_ext_phy_ctrl_5        = 0x009e009e,
  90         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
  91         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
  92         .emif_rd_wr_lvl_ctl             = 0x00000000,
  93         .emif_rd_wr_exec_thresh         = 0x00000305
  94 };
  95
  96 /* Ext phy ctrl regs 1-35 */
  97 static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
  98         0x10040100,
  99         0x00910091,
 100         0x00950095,
 101         0x009B009B,
 102         0x009E009E,
 103         0x00980098,
 104         0x00340034,
 105         0x00350035,
 106         0x00340034,
 107         0x00310031,
 108         0x00340034,
 109         0x007F007F,
 110         0x007F007F,
 111         0x007F007F,
 112         0x007F007F,
 113         0x007F007F,
 114         0x00480048,
 115         0x004A004A,
 116         0x00520052,
 117         0x00550055,
 118         0x00500050,
 119         0x00000000,
 120         0x00600020,
 121         0x40011080,
 122         0x08102040,
 123         0x0,
 124         0x0,
 125         0x0,
 126         0x0,
 127         0x0,
 128         0x0,
 129         0x0,
 130         0x0,
 131         0x0,
 132         0x0
 133 };
 134
 135 static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
 136         .sdram_config_init              = 0x61851b32,
 137         .sdram_config                   = 0x61851b32,
 138         .sdram_config2                  = 0x08000000,
 139         .ref_ctrl                       = 0x000040F1,
 140         .ref_ctrl_final                 = 0x00001035,
 141         .sdram_tim1                     = 0xcccf36b3,
 142         .sdram_tim2                     = 0x308f7fda,
 143         .sdram_tim3                     = 0x407f88a8,
 144         .read_idle_ctrl                 = 0x00050000,
 145         .zq_config                      = 0x5007190b,
 146         .temp_alert_config              = 0x00000000,
 147         .emif_ddr_phy_ctlr_1_init       = 0x0024400b,
 148         .emif_ddr_phy_ctlr_1            = 0x0e24400b,
 149         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 150         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 151         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 152         .emif_ddr_ext_phy_ctrl_4        = 0x009b009b,
 153         .emif_ddr_ext_phy_ctrl_5        = 0x009e009e,
 154         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 155         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 156         .emif_rd_wr_lvl_ctl             = 0x00000000,
 157         .emif_rd_wr_exec_thresh         = 0x00000305
 158 };
 159
 160 static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
 161         0x10040100,
 162         0x00910091,
 163         0x00950095,
 164         0x009B009B,
 165         0x009E009E,
 166         0x00980098,
 167         0x00340034,
 168         0x00350035,
 169         0x00340034,
 170         0x00310031,
 171         0x00340034,
 172         0x007F007F,
 173         0x007F007F,
 174         0x007F007F,
 175         0x007F007F,
 176         0x007F007F,
 177         0x00480048,
 178         0x004A004A,
 179         0x00520052,
 180         0x00550055,
 181         0x00500050,
 182         0x00000000,
 183         0x00600020,
 184         0x40011080,
 185         0x08102040,
 186         0x0,
 187         0x0,
 188         0x0,
 189         0x0,
 190         0x0,
 191         0x0,
 192         0x0,
 193         0x0,
 194         0x0,
 195         0x0
 196 };
 197
 198 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 199 {
 200         switch (emif_nr) {
 201         case 1:
 202                 *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
 203                 break;
 204         case 2:
 205                 *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
 206                 break;
 207         }
 208 }
 209
 210 void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
 211 {
 212         switch (emif_nr) {
 213         case 1:
 214                 *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
 215                 *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
 216                 break;
 217         case 2:
 218                 *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
 219                 *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
 220                 break;
 221         }
 222 }
 223
 224 struct vcores_data beagle_x15_volts = {
 225         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 226         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 227         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 228         .mpu.addr               = TPS659038_REG_ADDR_SMPS12,
 229         .mpu.pmic               = &tps659038,
 230         .mpu.abb_tx_done_mask   = OMAP_ABB_MPU_TXDONE_MASK,
 231
 232         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 233         .eve.value[OPP_OD]      = VDD_EVE_DRA7_OD,
 234         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 235         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 236         .eve.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_DSPEVE_OD,
 237         .eve.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 238         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 239         .eve.addr               = TPS659038_REG_ADDR_SMPS45,
 240         .eve.pmic               = &tps659038,
 241         .eve.abb_tx_done_mask   = OMAP_ABB_EVE_TXDONE_MASK,
 242
 243         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 244         .gpu.value[OPP_OD]      = VDD_GPU_DRA7_OD,
 245         .gpu.value[OPP_HIGH]    = VDD_GPU_DRA7_HIGH,
 246         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 247         .gpu.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_GPU_OD,
 248         .gpu.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_GPU_HIGH,
 249         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 250         .gpu.addr               = TPS659038_REG_ADDR_SMPS45,
 251         .gpu.pmic               = &tps659038,
 252         .gpu.abb_tx_done_mask   = OMAP_ABB_GPU_TXDONE_MASK,
 253
 254         .core.value[OPP_NOM]    = VDD_CORE_DRA7_NOM,
 255         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 256         .core.efuse.reg_bits    = DRA752_EFUSE_REGBITS,
 257         .core.addr              = TPS659038_REG_ADDR_SMPS6,
 258         .core.pmic              = &tps659038,
 259
 260         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 261         .iva.value[OPP_OD]      = VDD_IVA_DRA7_OD,
 262         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 263         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 264         .iva.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_IVA_OD,
 265         .iva.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_IVA_HIGH,
 266         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 267         .iva.addr               = TPS659038_REG_ADDR_SMPS45,
 268         .iva.pmic               = &tps659038,
 269         .iva.abb_tx_done_mask   = OMAP_ABB_IVA_TXDONE_MASK,
 270 };
 271
 272 struct vcores_data am572x_idk_volts = {
 273         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 274         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 275         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 276         .mpu.addr               = TPS659038_REG_ADDR_SMPS12,
 277         .mpu.pmic               = &tps659038,
 278         .mpu.abb_tx_done_mask   = OMAP_ABB_MPU_TXDONE_MASK,
 279
 280         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 281         .eve.value[OPP_OD]      = VDD_EVE_DRA7_OD,
 282         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 283         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 284         .eve.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_DSPEVE_OD,
 285         .eve.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 286         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 287         .eve.addr               = TPS659038_REG_ADDR_SMPS45,
 288         .eve.pmic               = &tps659038,
 289         .eve.abb_tx_done_mask   = OMAP_ABB_EVE_TXDONE_MASK,
 290
 291         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 292         .gpu.value[OPP_OD]      = VDD_GPU_DRA7_OD,
 293         .gpu.value[OPP_HIGH]    = VDD_GPU_DRA7_HIGH,
 294         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 295         .gpu.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_GPU_OD,
 296         .gpu.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_GPU_HIGH,
 297         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 298         .gpu.addr               = TPS659038_REG_ADDR_SMPS6,
 299         .gpu.pmic               = &tps659038,
 300         .gpu.abb_tx_done_mask   = OMAP_ABB_GPU_TXDONE_MASK,
 301
 302         .core.value[OPP_NOM]    = VDD_CORE_DRA7_NOM,
 303         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 304         .core.efuse.reg_bits    = DRA752_EFUSE_REGBITS,
 305         .core.addr              = TPS659038_REG_ADDR_SMPS7,
 306         .core.pmic              = &tps659038,
 307
 308         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 309         .iva.value[OPP_OD]      = VDD_IVA_DRA7_OD,
 310         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 311         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 312         .iva.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_IVA_OD,
 313         .iva.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_IVA_HIGH,
 314         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 315         .iva.addr               = TPS659038_REG_ADDR_SMPS8,
 316         .iva.pmic               = &tps659038,
 317         .iva.abb_tx_done_mask   = OMAP_ABB_IVA_TXDONE_MASK,
 318 };
 319
 320 int get_voltrail_opp(int rail_offset)
 321 {
 322         int opp;
 323
 324         switch (rail_offset) {
 325         case VOLT_MPU:
 326                 opp = DRA7_MPU_OPP;
 327                 break;
 328         case VOLT_CORE:
 329                 opp = DRA7_CORE_OPP;
 330                 break;
 331         case VOLT_GPU:
 332                 opp = DRA7_GPU_OPP;
 333                 break;
 334         case VOLT_EVE:
 335                 opp = DRA7_DSPEVE_OPP;
 336                 break;
 337         case VOLT_IVA:
 338                 opp = DRA7_IVA_OPP;
 339                 break;
 340         default:
 341                 opp = OPP_NOM;
 342         }
 343
 344         return opp;
 345 }
 346
 347
 348 #ifdef CONFIG_SPL_BUILD
 349 /* No env to setup for SPL */
 350 static inline void setup_board_eeprom_env(void) { }
 351
 352 /* Override function to read eeprom information */
 353 void do_board_detect(void)
 354 {
 355         int rc;
 356
 357         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 358                                   CONFIG_EEPROM_CHIP_ADDRESS);
 359         if (rc)
 360                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 361 }
 362
 363 #else   /* CONFIG_SPL_BUILD */
 364
 365 /* Override function to read eeprom information: actual i2c read done by SPL*/
 366 void do_board_detect(void)
 367 {
 368         char *bname = NULL;
 369         int rc;
 370
 371         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 372                                   CONFIG_EEPROM_CHIP_ADDRESS);
 373         if (rc)
 374                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 375
 376         if (board_is_x15())
 377                 bname = "BeagleBoard X15";
 378         else if (board_is_am572x_evm())
 379                 bname = "AM572x EVM";
 380         else if (board_is_am572x_idk())
 381                 bname = "AM572x IDK";
 382
 383         if (bname)
 384                 snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
 385                          "Board: %s REV %s\n", bname, board_ti_get_rev());
 386 }
 387
 388 static void setup_board_eeprom_env(void)
 389 {
 390         char *name = "beagle_x15";
 391         int rc;
 392
 393         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 394                                   CONFIG_EEPROM_CHIP_ADDRESS);
 395         if (rc)
 396                 goto invalid_eeprom;
 397
 398         if (board_is_x15()) {
 399                 if (board_is_x15_revb1())
 400                         name = "beagle_x15_revb1";
 401                 else
 402                         name = "beagle_x15";
 403         } else if (board_is_am572x_evm()) {
 404                 if (board_is_am572x_evm_reva3())
 405                         name = "am57xx_evm_reva3";
 406                 else
 407                         name = "am57xx_evm";
 408         } else if (board_is_am572x_idk()) {
 409                 name = "am572x_idk";
 410         } else {
 411                 printf("Unidentified board claims %s in eeprom header\n",
 412                        board_ti_get_name());
 413         }
 414
 415 invalid_eeprom:
 416         set_board_info_env(name);
 417 }
 418
 419 #endif  /* CONFIG_SPL_BUILD */
 420
 421 void vcores_init(void)
 422 {
 423         if (board_is_am572x_idk())
 424                 *omap_vcores = &am572x_idk_volts;
 425         else
 426                 *omap_vcores = &beagle_x15_volts;
 427 }
 428
 429 void hw_data_init(void)
 430 {
 431         *prcm = &dra7xx_prcm;
 432         *dplls_data = &dra7xx_dplls;
 433         *ctrl = &dra7xx_ctrl;
 434 }
 435
 436 int board_init(void)
 437 {
 438         gpmc_init();
 439         gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
 440
 441         return 0;
 442 }
 443
 444 int board_late_init(void)
 445 {
 446         setup_board_eeprom_env();
 447
 448         /*
 449          * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
 450          * This is the POWERHOLD-in-Low behavior.
 451          */
 452         palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
 453
 454         /*
 455          * Default FIT boot on HS devices. Non FIT images are not allowed
 456          * on HS devices.
 457          */
 458         if (get_device_type() == HS_DEVICE)
 459                 setenv("boot_fit", "1");
 460
 461         return 0;
 462 }
 463
 464 void set_muxconf_regs(void)
 465 {
 466         do_set_mux32((*ctrl)->control_padconf_core_base,
 467                      early_padconf, ARRAY_SIZE(early_padconf));
 468 }
 469
 470 #ifdef CONFIG_IODELAY_RECALIBRATION
 471 void recalibrate_iodelay(void)
 472 {
 473         const struct pad_conf_entry *pconf;
 474         const struct iodelay_cfg_entry *iod;
 475         int pconf_sz, iod_sz;
 476
 477         if (board_is_am572x_idk()) {
 478                 pconf = core_padconf_array_essential_am572x_idk;
 479                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk);
 480                 iod = iodelay_cfg_array_am572x_idk;
 481                 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk);
 482         } else {
 483                 /* Common for X15/GPEVM */
 484                 pconf = core_padconf_array_essential_x15;
 485                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_x15);
 486                 iod = iodelay_cfg_array_x15;
 487                 iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15);
 488         }
 489
 490         __recalibrate_iodelay(pconf, pconf_sz, iod, iod_sz);
 491 }
 492 #endif
 493
 494 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
 495 int board_mmc_init(bd_t *bis)
 496 {
 497         omap_mmc_init(0, 0, 0, -1, -1);
 498         omap_mmc_init(1, 0, 0, -1, -1);
 499         return 0;
 500 }
 501 #endif
 502
 503 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
 504 int spl_start_uboot(void)
 505 {
 506         /* break into full u-boot on 'c' */
 507         if (serial_tstc() && serial_getc() == 'c')
 508                 return 1;
 509
 510 #ifdef CONFIG_SPL_ENV_SUPPORT
 511         env_init();
 512         env_relocate_spec();
 513         if (getenv_yesno("boot_os") != 1)
 514                 return 1;
 515 #endif
 516
 517         return 0;
 518 }
 519 #endif
 520
 521 #ifdef CONFIG_USB_DWC3
 522 static struct dwc3_device usb_otg_ss2 = {
 523         .maximum_speed = USB_SPEED_HIGH,
 524         .base = DRA7_USB_OTG_SS2_BASE,
 525         .tx_fifo_resize = false,
 526         .index = 1,
 527 };
 528
 529 static struct dwc3_omap_device usb_otg_ss2_glue = {
 530         .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE,
 531         .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
 532         .index = 1,
 533 };
 534
 535 static struct ti_usb_phy_device usb_phy2_device = {
 536         .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER,
 537         .index = 1,
 538 };
 539
 540 int usb_gadget_handle_interrupts(int index)
 541 {
 542         u32 status;
 543
 544         status = dwc3_omap_uboot_interrupt_status(index);
 545         if (status)
 546                 dwc3_uboot_handle_interrupt(index);
 547
 548         return 0;
 549 }
 550 #endif /* CONFIG_USB_DWC3 */
 551
 552 #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
 553 int board_usb_init(int index, enum usb_init_type init)
 554 {
 555         enable_usb_clocks(index);
 556         switch (index) {
 557         case 0:
 558                 if (init == USB_INIT_DEVICE) {
 559                         printf("port %d can't be used as device\n", index);
 560                         disable_usb_clocks(index);
 561                         return -EINVAL;
 562                 }
 563                 break;
 564         case 1:
 565                 if (init == USB_INIT_DEVICE) {
 566 #ifdef CONFIG_USB_DWC3
 567                         usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
 568                         usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
 569                         ti_usb_phy_uboot_init(&usb_phy2_device);
 570                         dwc3_omap_uboot_init(&usb_otg_ss2_glue);
 571                         dwc3_uboot_init(&usb_otg_ss2);
 572 #endif
 573                 } else {
 574                         printf("port %d can't be used as host\n", index);
 575                         disable_usb_clocks(index);
 576                         return -EINVAL;
 577                 }
 578
 579                 break;
 580         default:
 581                 printf("Invalid Controller Index\n");
 582         }
 583
 584         return 0;
 585 }
 586
 587 int board_usb_cleanup(int index, enum usb_init_type init)
 588 {
 589 #ifdef CONFIG_USB_DWC3
 590         switch (index) {
 591         case 0:
 592         case 1:
 593                 if (init == USB_INIT_DEVICE) {
 594                         ti_usb_phy_uboot_exit(index);
 595                         dwc3_uboot_exit(index);
 596                         dwc3_omap_uboot_exit(index);
 597                 }
 598                 break;
 599         default:
 600                 printf("Invalid Controller Index\n");
 601         }
 602 #endif
 603         disable_usb_clocks(index);
 604         return 0;
 605 }
 606 #endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
 607
 608 #ifdef CONFIG_DRIVER_TI_CPSW
 609
 610 /* Delay value to add to calibrated value */
 611 #define RGMII0_TXCTL_DLY_VAL            ((0x3 << 5) + 0x8)
 612 #define RGMII0_TXD0_DLY_VAL             ((0x3 << 5) + 0x8)
 613 #define RGMII0_TXD1_DLY_VAL             ((0x3 << 5) + 0x2)
 614 #define RGMII0_TXD2_DLY_VAL             ((0x4 << 5) + 0x0)
 615 #define RGMII0_TXD3_DLY_VAL             ((0x4 << 5) + 0x0)
 616 #define VIN2A_D13_DLY_VAL               ((0x3 << 5) + 0x8)
 617 #define VIN2A_D17_DLY_VAL               ((0x3 << 5) + 0x8)
 618 #define VIN2A_D16_DLY_VAL               ((0x3 << 5) + 0x2)
 619 #define VIN2A_D15_DLY_VAL               ((0x4 << 5) + 0x0)
 620 #define VIN2A_D14_DLY_VAL               ((0x4 << 5) + 0x0)
 621
 622 static void cpsw_control(int enabled)
 623 {
 624         /* VTP can be added here */
 625 }
 626
 627 static struct cpsw_slave_data cpsw_slaves[] = {
 628         {
 629                 .slave_reg_ofs  = 0x208,
 630                 .sliver_reg_ofs = 0xd80,
 631                 .phy_addr       = 1,
 632         },
 633         {
 634                 .slave_reg_ofs  = 0x308,
 635                 .sliver_reg_ofs = 0xdc0,
 636                 .phy_addr       = 2,
 637         },
 638 };
 639
 640 static struct cpsw_platform_data cpsw_data = {
 641         .mdio_base              = CPSW_MDIO_BASE,
 642         .cpsw_base              = CPSW_BASE,
 643         .mdio_div               = 0xff,
 644         .channels               = 8,
 645         .cpdma_reg_ofs          = 0x800,
 646         .slaves                 = 1,
 647         .slave_data             = cpsw_slaves,
 648         .ale_reg_ofs            = 0xd00,
 649         .ale_entries            = 1024,
 650         .host_port_reg_ofs      = 0x108,
 651         .hw_stats_reg_ofs       = 0x900,
 652         .bd_ram_ofs             = 0x2000,
 653         .mac_control            = (1 << 5),
 654         .control                = cpsw_control,
 655         .host_port_num          = 0,
 656         .version                = CPSW_CTRL_VERSION_2,
 657 };
 658
 659 static u64 mac_to_u64(u8 mac[6])
 660 {
 661         int i;
 662         u64 addr = 0;
 663
 664         for (i = 0; i < 6; i++) {
 665                 addr <<= 8;
 666                 addr |= mac[i];
 667         }
 668
 669         return addr;
 670 }
 671
 672 static void u64_to_mac(u64 addr, u8 mac[6])
 673 {
 674         mac[5] = addr;
 675         mac[4] = addr >> 8;
 676         mac[3] = addr >> 16;
 677         mac[2] = addr >> 24;
 678         mac[1] = addr >> 32;
 679         mac[0] = addr >> 40;
 680 }
 681
 682 int board_eth_init(bd_t *bis)
 683 {
 684         int ret;
 685         uint8_t mac_addr[6];
 686         uint32_t mac_hi, mac_lo;
 687         uint32_t ctrl_val;
 688         int i;
 689         u64 mac1, mac2;
 690         u8 mac_addr1[6], mac_addr2[6];
 691         int num_macs;
 692
 693         /* try reading mac address from efuse */
 694         mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
 695         mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
 696         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
 697         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 698         mac_addr[2] = mac_hi & 0xFF;
 699         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
 700         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
 701         mac_addr[5] = mac_lo & 0xFF;
 702
 703         if (!getenv("ethaddr")) {
 704                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
 705
 706                 if (is_valid_ethaddr(mac_addr))
 707                         eth_setenv_enetaddr("ethaddr", mac_addr);
 708         }
 709
 710         mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
 711         mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
 712         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
 713         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 714         mac_addr[2] = mac_hi & 0xFF;
 715         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
 716         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
 717         mac_addr[5] = mac_lo & 0xFF;
 718
 719         if (!getenv("eth1addr")) {
 720                 if (is_valid_ethaddr(mac_addr))
 721                         eth_setenv_enetaddr("eth1addr", mac_addr);
 722         }
 723
 724         ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
 725         ctrl_val |= 0x22;
 726         writel(ctrl_val, (*ctrl)->control_core_control_io1);
 727
 728         /* The phy address for the AM572x IDK are different than x15 */
 729         if (board_is_am572x_idk()) {
 730                 cpsw_data.slave_data[0].phy_addr = 0;
 731                 cpsw_data.slave_data[1].phy_addr = 1;
 732         }
 733
 734         ret = cpsw_register(&cpsw_data);
 735         if (ret < 0)
 736                 printf("Error %d registering CPSW switch\n", ret);
 737
 738         /*
 739          * Export any Ethernet MAC addresses from EEPROM.
 740          * On AM57xx the 2 MAC addresses define the address range
 741          */
 742         board_ti_get_eth_mac_addr(0, mac_addr1);
 743         board_ti_get_eth_mac_addr(1, mac_addr2);
 744
 745         if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) {
 746                 mac1 = mac_to_u64(mac_addr1);
 747                 mac2 = mac_to_u64(mac_addr2);
 748
 749                 /* must contain an address range */
 750                 num_macs = mac2 - mac1 + 1;
 751                 /* <= 50 to protect against user programming error */
 752                 if (num_macs > 0 && num_macs <= 50) {
 753                         for (i = 0; i < num_macs; i++) {
 754                                 u64_to_mac(mac1 + i, mac_addr);
 755                                 if (is_valid_ethaddr(mac_addr)) {
 756                                         eth_setenv_enetaddr_by_index("eth",
 757                                                                      i + 2,
 758                                                                      mac_addr);
 759                                 }
 760                         }
 761                 }
 762         }
 763
 764         return ret;
 765 }
 766 #endif
 767
 768 #ifdef CONFIG_BOARD_EARLY_INIT_F
 769 /* VTT regulator enable */
 770 static inline void vtt_regulator_enable(void)
 771 {
 772         if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
 773                 return;
 774
 775         gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
 776         gpio_direction_output(GPIO_DDR_VTT_EN, 1);
 777 }
 778
 779 int board_early_init_f(void)
 780 {
 781         vtt_regulator_enable();
 782         return 0;
 783 }
 784 #endif
 785
 786 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 787 int ft_board_setup(void *blob, bd_t *bd)
 788 {
 789         ft_cpu_setup(blob, bd);
 790
 791         return 0;
 792 }
 793 #endif
 794
 795 #ifdef CONFIG_SPL_LOAD_FIT
 796 int board_fit_config_name_match(const char *name)
 797 {
 798         if (board_is_x15()) {
 799                 if (board_is_x15_revb1()) {
 800                         if (!strcmp(name, "am57xx-beagle-x15-revb1"))
 801                                 return 0;
 802                 } else if (!strcmp(name, "am57xx-beagle-x15")) {
 803                         return 0;
 804                 }
 805         } else if (board_is_am572x_evm() &&
 806                    !strcmp(name, "am57xx-beagle-x15")) {
 807                 return 0;
 808         } else if (board_is_am572x_idk() && !strcmp(name, "am572x-idk")) {
 809                 return 0;
 810         }
 811
 812         return -1;
 813 }
 814 #endif
 815
 816 #ifdef CONFIG_TI_SECURE_DEVICE
 817 void board_fit_image_post_process(void **p_image, size_t *p_size)
 818 {
 819         secure_boot_verify_image(p_image, p_size);
 820 }
 821
 822 void board_tee_image_process(ulong tee_image, size_t tee_size)
 823 {
 824         secure_tee_install((u32)tee_image);
 825 }
 826
 827 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
 828 #endif