2 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
4 * Author: Felipe Balbi <balbi@ti.com>
6 * Based on board/ti/dra7xx/evm.c
8 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/omap_common.h>
18 #include <asm/arch/gpio.h>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/dra7xx_iodelay.h>
21 #include <asm/arch/sys_proto.h>
22 #include <asm/arch/mmc_host_def.h>
23 #include <asm/arch/sata.h>
24 #include <asm/arch/gpio.h>
25 #include <asm/arch/omap.h>
26 #include <environment.h>
28 #include <linux/usb/gadget.h>
29 #include <dwc3-uboot.h>
30 #include <dwc3-omap-uboot.h>
31 #include <ti-usb-phy-uboot.h>
35 #ifdef CONFIG_DRIVER_TI_CPSW
39 DECLARE_GLOBAL_DATA_PTR;
42 #define GPIO_DDR_VTT_EN 203
44 const struct omap_sysinfo sysinfo = {
45 "Board: BeagleBoard x15\n"
48 static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
49 .dmm_lisa_map_3 = 0x80740300,
53 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
55 *dmm_lisa_regs = &beagle_x15_lisa_regs;
58 static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
59 .sdram_config_init = 0x61851b32,
60 .sdram_config = 0x61851b32,
61 .sdram_config2 = 0x00000000,
62 .ref_ctrl = 0x000040F1,
63 .ref_ctrl_final = 0x00001035,
64 .sdram_tim1 = 0xceef266b,
65 .sdram_tim2 = 0x328f7fda,
66 .sdram_tim3 = 0x027f88a8,
67 .read_idle_ctrl = 0x00050000,
68 .zq_config = 0x0007190b,
69 .temp_alert_config = 0x00000000,
70 .emif_ddr_phy_ctlr_1_init = 0x0024400b,
71 .emif_ddr_phy_ctlr_1 = 0x0e24400b,
72 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
73 .emif_ddr_ext_phy_ctrl_2 = 0x00740074,
74 .emif_ddr_ext_phy_ctrl_3 = 0x00780078,
75 .emif_ddr_ext_phy_ctrl_4 = 0x007c007c,
76 .emif_ddr_ext_phy_ctrl_5 = 0x007b007b,
77 .emif_rd_wr_lvl_rmp_win = 0x00000000,
78 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
79 .emif_rd_wr_lvl_ctl = 0x00000000,
80 .emif_rd_wr_exec_thresh = 0x00000305
83 /* Ext phy ctrl regs 1-35 */
84 static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
126 static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
127 .sdram_config_init = 0x61851b32,
128 .sdram_config = 0x61851b32,
129 .sdram_config2 = 0x00000000,
130 .ref_ctrl = 0x000040F1,
131 .ref_ctrl_final = 0x00001035,
132 .sdram_tim1 = 0xceef266b,
133 .sdram_tim2 = 0x328f7fda,
134 .sdram_tim3 = 0x027f88a8,
135 .read_idle_ctrl = 0x00050000,
136 .zq_config = 0x0007190b,
137 .temp_alert_config = 0x00000000,
138 .emif_ddr_phy_ctlr_1_init = 0x0024400b,
139 .emif_ddr_phy_ctlr_1 = 0x0e24400b,
140 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
141 .emif_ddr_ext_phy_ctrl_2 = 0x00820082,
142 .emif_ddr_ext_phy_ctrl_3 = 0x008b008b,
143 .emif_ddr_ext_phy_ctrl_4 = 0x00800080,
144 .emif_ddr_ext_phy_ctrl_5 = 0x007e007e,
145 .emif_rd_wr_lvl_rmp_win = 0x00000000,
146 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
147 .emif_rd_wr_lvl_ctl = 0x00000000,
148 .emif_rd_wr_exec_thresh = 0x00000305
151 static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
191 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
195 *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
198 *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
203 void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
207 *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
208 *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
211 *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
212 *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
217 struct vcores_data beagle_x15_volts = {
218 .mpu.value = VDD_MPU_DRA752,
219 .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM,
220 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
221 .mpu.addr = TPS659038_REG_ADDR_SMPS12,
222 .mpu.pmic = &tps659038,
224 .eve.value = VDD_EVE_DRA752,
225 .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
226 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
227 .eve.addr = TPS659038_REG_ADDR_SMPS45,
228 .eve.pmic = &tps659038,
230 .gpu.value = VDD_GPU_DRA752,
231 .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM,
232 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
233 .gpu.addr = TPS659038_REG_ADDR_SMPS45,
234 .gpu.pmic = &tps659038,
236 .core.value = VDD_CORE_DRA752,
237 .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,
238 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
239 .core.addr = TPS659038_REG_ADDR_SMPS6,
240 .core.pmic = &tps659038,
242 .iva.value = VDD_IVA_DRA752,
243 .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM,
244 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
245 .iva.addr = TPS659038_REG_ADDR_SMPS45,
246 .iva.pmic = &tps659038,
249 void hw_data_init(void)
251 *prcm = &dra7xx_prcm;
252 *dplls_data = &dra7xx_dplls;
253 *omap_vcores = &beagle_x15_volts;
254 *ctrl = &dra7xx_ctrl;
260 gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
265 int board_late_init(void)
269 * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
270 * This is the POWERHOLD-in-Low behavior.
272 palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
276 void set_muxconf_regs_essential(void)
278 do_set_mux32((*ctrl)->control_padconf_core_base,
279 early_padconf, ARRAY_SIZE(early_padconf));
282 #ifdef CONFIG_IODELAY_RECALIBRATION
283 void recalibrate_iodelay(void)
285 __recalibrate_iodelay(core_padconf_array_essential,
286 ARRAY_SIZE(core_padconf_array_essential),
287 iodelay_cfg_array, ARRAY_SIZE(iodelay_cfg_array));
291 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
292 int board_mmc_init(bd_t *bis)
294 omap_mmc_init(0, 0, 0, -1, -1);
295 omap_mmc_init(1, 0, 0, -1, -1);
300 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
301 int spl_start_uboot(void)
303 /* break into full u-boot on 'c' */
304 if (serial_tstc() && serial_getc() == 'c')
307 #ifdef CONFIG_SPL_ENV_SUPPORT
310 if (getenv_yesno("boot_os") != 1)
318 #ifdef CONFIG_USB_DWC3
319 static struct dwc3_device usb_otg_ss1 = {
320 .maximum_speed = USB_SPEED_SUPER,
321 .base = DRA7_USB_OTG_SS1_BASE,
322 .tx_fifo_resize = false,
326 static struct dwc3_omap_device usb_otg_ss1_glue = {
327 .base = (void *)DRA7_USB_OTG_SS1_GLUE_BASE,
328 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
332 static struct ti_usb_phy_device usb_phy1_device = {
333 .pll_ctrl_base = (void *)DRA7_USB3_PHY1_PLL_CTRL,
334 .usb2_phy_power = (void *)DRA7_USB2_PHY1_POWER,
335 .usb3_phy_power = (void *)DRA7_USB3_PHY1_POWER,
339 static struct dwc3_device usb_otg_ss2 = {
340 .maximum_speed = USB_SPEED_HIGH,
341 .base = DRA7_USB_OTG_SS2_BASE,
342 .tx_fifo_resize = false,
346 static struct dwc3_omap_device usb_otg_ss2_glue = {
347 .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE,
348 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
352 static struct ti_usb_phy_device usb_phy2_device = {
353 .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER,
357 int board_usb_init(int index, enum usb_init_type init)
359 enable_usb_clocks(index);
362 if (init == USB_INIT_DEVICE) {
363 printf("port %d can't be used as device\n", index);
364 disable_usb_clocks(index);
367 usb_otg_ss1.dr_mode = USB_DR_MODE_HOST;
368 usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
369 setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
370 OTG_SS_CLKCTRL_MODULEMODE_HW |
371 OPTFCLKEN_REFCLK960M);
374 ti_usb_phy_uboot_init(&usb_phy1_device);
375 dwc3_omap_uboot_init(&usb_otg_ss1_glue);
376 dwc3_uboot_init(&usb_otg_ss1);
379 if (init == USB_INIT_DEVICE) {
380 usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
381 usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
383 printf("port %d can't be used as host\n", index);
384 disable_usb_clocks(index);
388 ti_usb_phy_uboot_init(&usb_phy2_device);
389 dwc3_omap_uboot_init(&usb_otg_ss2_glue);
390 dwc3_uboot_init(&usb_otg_ss2);
393 printf("Invalid Controller Index\n");
399 int board_usb_cleanup(int index, enum usb_init_type init)
404 ti_usb_phy_uboot_exit(index);
405 dwc3_uboot_exit(index);
406 dwc3_omap_uboot_exit(index);
409 printf("Invalid Controller Index\n");
411 disable_usb_clocks(index);
415 int usb_gadget_handle_interrupts(int index)
419 status = dwc3_omap_uboot_interrupt_status(index);
421 dwc3_uboot_handle_interrupt(index);
427 #ifdef CONFIG_DRIVER_TI_CPSW
429 /* Delay value to add to calibrated value */
430 #define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8)
431 #define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8)
432 #define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2)
433 #define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0)
434 #define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0)
435 #define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8)
436 #define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8)
437 #define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2)
438 #define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0)
439 #define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0)
441 static void cpsw_control(int enabled)
443 /* VTP can be added here */
446 static struct cpsw_slave_data cpsw_slaves[] = {
448 .slave_reg_ofs = 0x208,
449 .sliver_reg_ofs = 0xd80,
453 .slave_reg_ofs = 0x308,
454 .sliver_reg_ofs = 0xdc0,
459 static struct cpsw_platform_data cpsw_data = {
460 .mdio_base = CPSW_MDIO_BASE,
461 .cpsw_base = CPSW_BASE,
464 .cpdma_reg_ofs = 0x800,
466 .slave_data = cpsw_slaves,
467 .ale_reg_ofs = 0xd00,
469 .host_port_reg_ofs = 0x108,
470 .hw_stats_reg_ofs = 0x900,
471 .bd_ram_ofs = 0x2000,
472 .mac_control = (1 << 5),
473 .control = cpsw_control,
475 .version = CPSW_CTRL_VERSION_2,
478 int board_eth_init(bd_t *bis)
482 uint32_t mac_hi, mac_lo;
485 /* try reading mac address from efuse */
486 mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
487 mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
488 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
489 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
490 mac_addr[2] = mac_hi & 0xFF;
491 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
492 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
493 mac_addr[5] = mac_lo & 0xFF;
495 if (!getenv("ethaddr")) {
496 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
498 if (is_valid_ethaddr(mac_addr))
499 eth_setenv_enetaddr("ethaddr", mac_addr);
502 mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
503 mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
504 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
505 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
506 mac_addr[2] = mac_hi & 0xFF;
507 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
508 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
509 mac_addr[5] = mac_lo & 0xFF;
511 if (!getenv("eth1addr")) {
512 if (is_valid_ethaddr(mac_addr))
513 eth_setenv_enetaddr("eth1addr", mac_addr);
516 ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
518 writel(ctrl_val, (*ctrl)->control_core_control_io1);
520 ret = cpsw_register(&cpsw_data);
522 printf("Error %d registering CPSW switch\n", ret);
528 #ifdef CONFIG_BOARD_EARLY_INIT_F
529 /* VTT regulator enable */
530 static inline void vtt_regulator_enable(void)
532 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
535 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
536 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
539 int board_early_init_f(void)
541 vtt_regulator_enable();