board/ti/am57xx/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
   4  *
   5  * Author: Felipe Balbi <balbi@ti.com>
   6  *
   7  * Based on board/ti/dra7xx/evm.c
   8  */
   9
  10 #include <common.h>
  11 #include <env.h>
  12 #include <fdt_support.h>
  13 #include <init.h>
  14 #include <palmas.h>
  15 #include <sata.h>
  16 #include <serial.h>
  17 #include <usb.h>
  18 #include <errno.h>
  19 #include <asm/omap_common.h>
  20 #include <asm/omap_sec_common.h>
  21 #include <asm/emif.h>
  22 #include <asm/gpio.h>
  23 #include <asm/arch/gpio.h>
  24 #include <asm/arch/clock.h>
  25 #include <asm/arch/dra7xx_iodelay.h>
  26 #include <asm/arch/sys_proto.h>
  27 #include <asm/arch/mmc_host_def.h>
  28 #include <asm/arch/sata.h>
  29 #include <asm/arch/gpio.h>
  30 #include <asm/arch/omap.h>
  31 #include <usb.h>
  32 #include <linux/usb/gadget.h>
  33 #include <dwc3-uboot.h>
  34 #include <dwc3-omap-uboot.h>
  35 #include <ti-usb-phy-uboot.h>
  36 #include <mmc.h>
  37 #include <dm/uclass.h>
  38
  39 #include "../common/board_detect.h"
  40 #include "mux_data.h"
  41
  42 #ifdef CONFIG_SUPPORT_EMMC_BOOT
  43 static int board_bootmode_has_emmc(void);
  44 #endif
  45
  46 #define board_is_x15()          board_ti_is("BBRDX15_")
  47 #define board_is_x15_revb1()    (board_ti_is("BBRDX15_") && \
  48                                  !strncmp("B.10", board_ti_get_rev(), 3))
  49 #define board_is_x15_revc()     (board_ti_is("BBRDX15_") && \
  50                                  !strncmp("C.00", board_ti_get_rev(), 3))
  51 #define board_is_am572x_evm()   board_ti_is("AM572PM_")
  52 #define board_is_am572x_evm_reva3()     \
  53                                 (board_ti_is("AM572PM_") && \
  54                                  !strncmp("A.30", board_ti_get_rev(), 3))
  55 #define board_is_am574x_idk()   board_ti_is("AM574IDK")
  56 #define board_is_am572x_idk()   board_ti_is("AM572IDK")
  57 #define board_is_am571x_idk()   board_ti_is("AM571IDK")
  58 #define board_is_bbai()         board_ti_is("BBONE-AI")
  59
  60 #ifdef CONFIG_DRIVER_TI_CPSW
  61 #include <cpsw.h>
  62 #endif
  63
  64 DECLARE_GLOBAL_DATA_PTR;
  65
  66 #define GPIO_ETH_LCD            GPIO_TO_PIN(2, 22)
  67 /* GPIO 7_11 */
  68 #define GPIO_DDR_VTT_EN 203
  69
  70 /* Touch screen controller to identify the LCD */
  71 #define OSD_TS_FT_BUS_ADDRESS   0
  72 #define OSD_TS_FT_CHIP_ADDRESS  0x38
  73 #define OSD_TS_FT_REG_ID        0xA3
  74 /*
  75  * Touchscreen IDs for various OSD panels
  76  * Ref: http://www.osddisplays.com/TI/OSD101T2587-53TS_A.1.pdf
  77  */
  78 /* Used on newer osd101t2587 Panels */
  79 #define OSD_TS_FT_ID_5x46       0x54
  80 /* Used on older osd101t2045 Panels */
  81 #define OSD_TS_FT_ID_5606       0x08
  82
  83 #define SYSINFO_BOARD_NAME_MAX_LEN      45
  84
  85 #define TPS65903X_PRIMARY_SECONDARY_PAD2        0xFB
  86 #define TPS65903X_PAD2_POWERHOLD_MASK           0x20
  87
  88 const struct omap_sysinfo sysinfo = {
  89         "Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n"
  90 };
  91
  92 static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
  93         .dmm_lisa_map_3 = 0x80740300,
  94         .is_ma_present  = 0x1
  95 };
  96
  97 static const struct dmm_lisa_map_regs am571x_idk_lisa_regs = {
  98         .dmm_lisa_map_3 = 0x80640100,
  99         .is_ma_present  = 0x1
 100 };
 101
 102 static const struct dmm_lisa_map_regs am574x_idk_lisa_regs = {
 103         .dmm_lisa_map_2 = 0xc0600200,
 104         .dmm_lisa_map_3 = 0x80600100,
 105         .is_ma_present  = 0x1
 106 };
 107
 108 static const struct dmm_lisa_map_regs bbai_lisa_regs = {
 109         .dmm_lisa_map_3 = 0x80640100,
 110         .is_ma_present  = 0x1
 111 };
 112
 113 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
 114 {
 115         if (board_is_am571x_idk())
 116                 *dmm_lisa_regs = &am571x_idk_lisa_regs;
 117         else if (board_is_am574x_idk())
 118                 *dmm_lisa_regs = &am574x_idk_lisa_regs;
 119         else if (board_is_bbai())
 120                 *dmm_lisa_regs = &bbai_lisa_regs;
 121         else
 122                 *dmm_lisa_regs = &beagle_x15_lisa_regs;
 123 }
 124
 125 static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
 126         .sdram_config_init              = 0x61851b32,
 127         .sdram_config                   = 0x61851b32,
 128         .sdram_config2                  = 0x08000000,
 129         .ref_ctrl                       = 0x000040F1,
 130         .ref_ctrl_final                 = 0x00001035,
 131         .sdram_tim1                     = 0xcccf36ab,
 132         .sdram_tim2                     = 0x308f7fda,
 133         .sdram_tim3                     = 0x409f88a8,
 134         .read_idle_ctrl                 = 0x00050000,
 135         .zq_config                      = 0x5007190b,
 136         .temp_alert_config              = 0x00000000,
 137         .emif_ddr_phy_ctlr_1_init       = 0x0024400b,
 138         .emif_ddr_phy_ctlr_1            = 0x0e24400b,
 139         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 140         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 141         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 142         .emif_ddr_ext_phy_ctrl_4        = 0x009b009b,
 143         .emif_ddr_ext_phy_ctrl_5        = 0x009e009e,
 144         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 145         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 146         .emif_rd_wr_lvl_ctl             = 0x00000000,
 147         .emif_rd_wr_exec_thresh         = 0x00000305
 148 };
 149
 150 /* Ext phy ctrl regs 1-35 */
 151 static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
 152         0x10040100,
 153         0x00910091,
 154         0x00950095,
 155         0x009B009B,
 156         0x009E009E,
 157         0x00980098,
 158         0x00340034,
 159         0x00350035,
 160         0x00340034,
 161         0x00310031,
 162         0x00340034,
 163         0x007F007F,
 164         0x007F007F,
 165         0x007F007F,
 166         0x007F007F,
 167         0x007F007F,
 168         0x00480048,
 169         0x004A004A,
 170         0x00520052,
 171         0x00550055,
 172         0x00500050,
 173         0x00000000,
 174         0x00600020,
 175         0x40011080,
 176         0x08102040,
 177         0x0,
 178         0x0,
 179         0x0,
 180         0x0,
 181         0x0,
 182         0x0,
 183         0x0,
 184         0x0,
 185         0x0,
 186         0x0
 187 };
 188
 189 static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
 190         .sdram_config_init              = 0x61851b32,
 191         .sdram_config                   = 0x61851b32,
 192         .sdram_config2                  = 0x08000000,
 193         .ref_ctrl                       = 0x000040F1,
 194         .ref_ctrl_final                 = 0x00001035,
 195         .sdram_tim1                     = 0xcccf36b3,
 196         .sdram_tim2                     = 0x308f7fda,
 197         .sdram_tim3                     = 0x407f88a8,
 198         .read_idle_ctrl                 = 0x00050000,
 199         .zq_config                      = 0x5007190b,
 200         .temp_alert_config              = 0x00000000,
 201         .emif_ddr_phy_ctlr_1_init       = 0x0024400b,
 202         .emif_ddr_phy_ctlr_1            = 0x0e24400b,
 203         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 204         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 205         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 206         .emif_ddr_ext_phy_ctrl_4        = 0x009b009b,
 207         .emif_ddr_ext_phy_ctrl_5        = 0x009e009e,
 208         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 209         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 210         .emif_rd_wr_lvl_ctl             = 0x00000000,
 211         .emif_rd_wr_exec_thresh         = 0x00000305
 212 };
 213
 214 static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
 215         0x10040100,
 216         0x00910091,
 217         0x00950095,
 218         0x009B009B,
 219         0x009E009E,
 220         0x00980098,
 221         0x00340034,
 222         0x00350035,
 223         0x00340034,
 224         0x00310031,
 225         0x00340034,
 226         0x007F007F,
 227         0x007F007F,
 228         0x007F007F,
 229         0x007F007F,
 230         0x007F007F,
 231         0x00480048,
 232         0x004A004A,
 233         0x00520052,
 234         0x00550055,
 235         0x00500050,
 236         0x00000000,
 237         0x00600020,
 238         0x40011080,
 239         0x08102040,
 240         0x0,
 241         0x0,
 242         0x0,
 243         0x0,
 244         0x0,
 245         0x0,
 246         0x0,
 247         0x0,
 248         0x0,
 249         0x0
 250 };
 251
 252 static const struct emif_regs am571x_emif1_ddr3_666mhz_emif_regs = {
 253         .sdram_config_init              = 0x61863332,
 254         .sdram_config                   = 0x61863332,
 255         .sdram_config2                  = 0x08000000,
 256         .ref_ctrl                       = 0x0000514d,
 257         .ref_ctrl_final                 = 0x0000144a,
 258         .sdram_tim1                     = 0xd333887c,
 259         .sdram_tim2                     = 0x30b37fe3,
 260         .sdram_tim3                     = 0x409f8ad8,
 261         .read_idle_ctrl                 = 0x00050000,
 262         .zq_config                      = 0x5007190b,
 263         .temp_alert_config              = 0x00000000,
 264         .emif_ddr_phy_ctlr_1_init       = 0x0024400f,
 265         .emif_ddr_phy_ctlr_1            = 0x0e24400f,
 266         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 267         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 268         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 269         .emif_ddr_ext_phy_ctrl_4        = 0x009b009b,
 270         .emif_ddr_ext_phy_ctrl_5        = 0x009e009e,
 271         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 272         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 273         .emif_rd_wr_lvl_ctl             = 0x00000000,
 274         .emif_rd_wr_exec_thresh         = 0x00000305
 275 };
 276
 277 static const struct emif_regs am574x_emif1_ddr3_666mhz_emif_ecc_regs = {
 278         .sdram_config_init              = 0x61863332,
 279         .sdram_config                   = 0x61863332,
 280         .sdram_config2                  = 0x08000000,
 281         .ref_ctrl                       = 0x0000514d,
 282         .ref_ctrl_final                 = 0x0000144a,
 283         .sdram_tim1                     = 0xd333887c,
 284         .sdram_tim2                     = 0x30b37fe3,
 285         .sdram_tim3                     = 0x409f8ad8,
 286         .read_idle_ctrl                 = 0x00050000,
 287         .zq_config                      = 0x5007190b,
 288         .temp_alert_config              = 0x00000000,
 289         .emif_ddr_phy_ctlr_1_init       = 0x0024400f,
 290         .emif_ddr_phy_ctlr_1            = 0x0e24400f,
 291         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 292         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 293         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 294         .emif_ddr_ext_phy_ctrl_4        = 0x009b009b,
 295         .emif_ddr_ext_phy_ctrl_5        = 0x009e009e,
 296         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 297         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 298         .emif_rd_wr_lvl_ctl             = 0x00000000,
 299         .emif_rd_wr_exec_thresh         = 0x00000305,
 300         .emif_ecc_ctrl_reg              = 0xD0000001,
 301         .emif_ecc_address_range_1       = 0x3FFF0000,
 302         .emif_ecc_address_range_2       = 0x00000000
 303 };
 304
 305 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 306 {
 307         switch (emif_nr) {
 308         case 1:
 309                 if (board_is_am571x_idk())
 310                         *regs = &am571x_emif1_ddr3_666mhz_emif_regs;
 311                 else if (board_is_am574x_idk())
 312                         *regs = &am574x_emif1_ddr3_666mhz_emif_ecc_regs;
 313                 else
 314                         *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
 315                 break;
 316         case 2:
 317                 if (board_is_am574x_idk())
 318                         *regs = &am571x_emif1_ddr3_666mhz_emif_regs;
 319                 else
 320                         *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
 321                 break;
 322         }
 323 }
 324
 325 void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
 326 {
 327         switch (emif_nr) {
 328         case 1:
 329                 *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
 330                 *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
 331                 break;
 332         case 2:
 333                 *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
 334                 *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
 335                 break;
 336         }
 337 }
 338
 339 struct vcores_data beagle_x15_volts = {
 340         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 341         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 342         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 343         .mpu.addr               = TPS659038_REG_ADDR_SMPS12,
 344         .mpu.pmic               = &tps659038,
 345         .mpu.abb_tx_done_mask   = OMAP_ABB_MPU_TXDONE_MASK,
 346
 347         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 348         .eve.value[OPP_OD]      = VDD_EVE_DRA7_OD,
 349         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 350         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 351         .eve.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_DSPEVE_OD,
 352         .eve.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 353         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 354         .eve.addr               = TPS659038_REG_ADDR_SMPS45,
 355         .eve.pmic               = &tps659038,
 356         .eve.abb_tx_done_mask   = OMAP_ABB_EVE_TXDONE_MASK,
 357
 358         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 359         .gpu.value[OPP_OD]      = VDD_GPU_DRA7_OD,
 360         .gpu.value[OPP_HIGH]    = VDD_GPU_DRA7_HIGH,
 361         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 362         .gpu.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_GPU_OD,
 363         .gpu.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_GPU_HIGH,
 364         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 365         .gpu.addr               = TPS659038_REG_ADDR_SMPS45,
 366         .gpu.pmic               = &tps659038,
 367         .gpu.abb_tx_done_mask   = OMAP_ABB_GPU_TXDONE_MASK,
 368
 369         .core.value[OPP_NOM]    = VDD_CORE_DRA7_NOM,
 370         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 371         .core.efuse.reg_bits    = DRA752_EFUSE_REGBITS,
 372         .core.addr              = TPS659038_REG_ADDR_SMPS6,
 373         .core.pmic              = &tps659038,
 374
 375         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 376         .iva.value[OPP_OD]      = VDD_IVA_DRA7_OD,
 377         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 378         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 379         .iva.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_IVA_OD,
 380         .iva.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_IVA_HIGH,
 381         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 382         .iva.addr               = TPS659038_REG_ADDR_SMPS45,
 383         .iva.pmic               = &tps659038,
 384         .iva.abb_tx_done_mask   = OMAP_ABB_IVA_TXDONE_MASK,
 385 };
 386
 387 struct vcores_data am572x_idk_volts = {
 388         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 389         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 390         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 391         .mpu.addr               = TPS659038_REG_ADDR_SMPS12,
 392         .mpu.pmic               = &tps659038,
 393         .mpu.abb_tx_done_mask   = OMAP_ABB_MPU_TXDONE_MASK,
 394
 395         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 396         .eve.value[OPP_OD]      = VDD_EVE_DRA7_OD,
 397         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 398         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 399         .eve.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_DSPEVE_OD,
 400         .eve.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 401         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 402         .eve.addr               = TPS659038_REG_ADDR_SMPS45,
 403         .eve.pmic               = &tps659038,
 404         .eve.abb_tx_done_mask   = OMAP_ABB_EVE_TXDONE_MASK,
 405
 406         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 407         .gpu.value[OPP_OD]      = VDD_GPU_DRA7_OD,
 408         .gpu.value[OPP_HIGH]    = VDD_GPU_DRA7_HIGH,
 409         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 410         .gpu.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_GPU_OD,
 411         .gpu.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_GPU_HIGH,
 412         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 413         .gpu.addr               = TPS659038_REG_ADDR_SMPS6,
 414         .gpu.pmic               = &tps659038,
 415         .gpu.abb_tx_done_mask   = OMAP_ABB_GPU_TXDONE_MASK,
 416
 417         .core.value[OPP_NOM]    = VDD_CORE_DRA7_NOM,
 418         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 419         .core.efuse.reg_bits    = DRA752_EFUSE_REGBITS,
 420         .core.addr              = TPS659038_REG_ADDR_SMPS7,
 421         .core.pmic              = &tps659038,
 422
 423         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 424         .iva.value[OPP_OD]      = VDD_IVA_DRA7_OD,
 425         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 426         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 427         .iva.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_IVA_OD,
 428         .iva.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_IVA_HIGH,
 429         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 430         .iva.addr               = TPS659038_REG_ADDR_SMPS8,
 431         .iva.pmic               = &tps659038,
 432         .iva.abb_tx_done_mask   = OMAP_ABB_IVA_TXDONE_MASK,
 433 };
 434
 435 struct vcores_data am571x_idk_volts = {
 436         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 437         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 438         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 439         .mpu.addr               = TPS659038_REG_ADDR_SMPS12,
 440         .mpu.pmic               = &tps659038,
 441         .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
 442
 443         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 444         .eve.value[OPP_OD]      = VDD_EVE_DRA7_OD,
 445         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 446         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 447         .eve.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_DSPEVE_OD,
 448         .eve.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 449         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 450         .eve.addr               = TPS659038_REG_ADDR_SMPS45,
 451         .eve.pmic               = &tps659038,
 452         .eve.abb_tx_done_mask   = OMAP_ABB_EVE_TXDONE_MASK,
 453
 454         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 455         .gpu.value[OPP_OD]      = VDD_GPU_DRA7_OD,
 456         .gpu.value[OPP_HIGH]    = VDD_GPU_DRA7_HIGH,
 457         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 458         .gpu.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_GPU_OD,
 459         .gpu.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_GPU_HIGH,
 460         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 461         .gpu.addr               = TPS659038_REG_ADDR_SMPS6,
 462         .gpu.pmic               = &tps659038,
 463         .gpu.abb_tx_done_mask   = OMAP_ABB_GPU_TXDONE_MASK,
 464
 465         .core.value[OPP_NOM]    = VDD_CORE_DRA7_NOM,
 466         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 467         .core.efuse.reg_bits    = DRA752_EFUSE_REGBITS,
 468         .core.addr              = TPS659038_REG_ADDR_SMPS7,
 469         .core.pmic              = &tps659038,
 470
 471         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 472         .iva.value[OPP_OD]      = VDD_IVA_DRA7_OD,
 473         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 474         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 475         .iva.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_IVA_OD,
 476         .iva.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_IVA_HIGH,
 477         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 478         .iva.addr               = TPS659038_REG_ADDR_SMPS45,
 479         .iva.pmic               = &tps659038,
 480         .iva.abb_tx_done_mask   = OMAP_ABB_IVA_TXDONE_MASK,
 481 };
 482
 483 int get_voltrail_opp(int rail_offset)
 484 {
 485         int opp;
 486
 487         switch (rail_offset) {
 488         case VOLT_MPU:
 489                 opp = DRA7_MPU_OPP;
 490                 break;
 491         case VOLT_CORE:
 492                 opp = DRA7_CORE_OPP;
 493                 break;
 494         case VOLT_GPU:
 495                 opp = DRA7_GPU_OPP;
 496                 break;
 497         case VOLT_EVE:
 498                 opp = DRA7_DSPEVE_OPP;
 499                 break;
 500         case VOLT_IVA:
 501                 opp = DRA7_IVA_OPP;
 502                 break;
 503         default:
 504                 opp = OPP_NOM;
 505         }
 506
 507         return opp;
 508 }
 509
 510
 511 #ifdef CONFIG_SPL_BUILD
 512 /* No env to setup for SPL */
 513 static inline void setup_board_eeprom_env(void) { }
 514
 515 /* Override function to read eeprom information */
 516 void do_board_detect(void)
 517 {
 518         int rc;
 519
 520         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 521                                   CONFIG_EEPROM_CHIP_ADDRESS);
 522         if (rc)
 523                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 524
 525 #ifdef CONFIG_SUPPORT_EMMC_BOOT
 526         rc = board_bootmode_has_emmc();
 527         if (!rc)
 528                 rc = ti_emmc_boardid_get();
 529         if (rc)
 530                 printf("ti_emmc_boardid_get failed %d\n", rc);
 531 #endif
 532 }
 533
 534 #else   /* CONFIG_SPL_BUILD */
 535
 536 /* Override function to read eeprom information: actual i2c read done by SPL*/
 537 void do_board_detect(void)
 538 {
 539         char *bname = NULL;
 540         int rc;
 541
 542         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 543                                   CONFIG_EEPROM_CHIP_ADDRESS);
 544         if (rc)
 545                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 546
 547 #ifdef CONFIG_SUPPORT_EMMC_BOOT
 548         rc = board_bootmode_has_emmc();
 549         if (!rc)
 550                 rc = ti_emmc_boardid_get();
 551         if (rc)
 552                 printf("ti_emmc_boardid_get failed %d\n", rc);
 553 #endif
 554
 555         if (board_is_x15())
 556                 bname = "BeagleBoard X15";
 557         else if (board_is_am572x_evm())
 558                 bname = "AM572x EVM";
 559         else if (board_is_am574x_idk())
 560                 bname = "AM574x IDK";
 561         else if (board_is_am572x_idk())
 562                 bname = "AM572x IDK";
 563         else if (board_is_am571x_idk())
 564                 bname = "AM571x IDK";
 565         else if (board_is_bbai())
 566                 bname = "BeagleBone AI";
 567
 568         if (bname)
 569                 snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
 570                          "Board: %s REV %s\n", bname, board_ti_get_rev());
 571 }
 572
 573 static void setup_board_eeprom_env(void)
 574 {
 575         char *name = "beagle_x15";
 576         int rc;
 577
 578         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 579                                   CONFIG_EEPROM_CHIP_ADDRESS);
 580         if (rc)
 581                 goto invalid_eeprom;
 582
 583         if (board_is_x15()) {
 584                 if (board_is_x15_revb1())
 585                         name = "beagle_x15_revb1";
 586                 else if (board_is_x15_revc())
 587                         name = "beagle_x15_revc";
 588                 else
 589                         name = "beagle_x15";
 590         } else if (board_is_am572x_evm()) {
 591                 if (board_is_am572x_evm_reva3())
 592                         name = "am57xx_evm_reva3";
 593                 else
 594                         name = "am57xx_evm";
 595         } else if (board_is_am574x_idk()) {
 596                 name = "am574x_idk";
 597         } else if (board_is_am572x_idk()) {
 598                 name = "am572x_idk";
 599         } else if (board_is_am571x_idk()) {
 600                 name = "am571x_idk";
 601         } else if (board_is_bbai()) {
 602                 name = "am5729_beagleboneai";
 603         } else {
 604                 printf("Unidentified board claims %s in eeprom header\n",
 605                        board_ti_get_name());
 606         }
 607
 608 invalid_eeprom:
 609         set_board_info_env(name);
 610 }
 611
 612 #endif  /* CONFIG_SPL_BUILD */
 613
 614 void vcores_init(void)
 615 {
 616         if (board_is_am572x_idk() || board_is_am574x_idk())
 617                 *omap_vcores = &am572x_idk_volts;
 618         else if (board_is_am571x_idk())
 619                 *omap_vcores = &am571x_idk_volts;
 620         else
 621                 *omap_vcores = &beagle_x15_volts;
 622 }
 623
 624 void hw_data_init(void)
 625 {
 626         *prcm = &dra7xx_prcm;
 627         if (is_dra72x())
 628                 *dplls_data = &dra72x_dplls;
 629         else if (is_dra76x())
 630                 *dplls_data = &dra76x_dplls;
 631         else
 632                 *dplls_data = &dra7xx_dplls;
 633         *ctrl = &dra7xx_ctrl;
 634 }
 635
 636 bool am571x_idk_needs_lcd(void)
 637 {
 638         bool needs_lcd;
 639
 640         gpio_request(GPIO_ETH_LCD, "nLCD_Detect");
 641         if (gpio_get_value(GPIO_ETH_LCD))
 642                 needs_lcd = false;
 643         else
 644                 needs_lcd = true;
 645
 646         gpio_free(GPIO_ETH_LCD);
 647
 648         return needs_lcd;
 649 }
 650
 651 int board_init(void)
 652 {
 653         gpmc_init();
 654         gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
 655
 656         return 0;
 657 }
 658
 659 void am57x_idk_lcd_detect(void)
 660 {
 661         int r = -ENODEV;
 662         char *idk_lcd = "no";
 663         struct udevice *dev;
 664
 665         /* Only valid for IDKs */
 666         if (board_is_x15() || board_is_am572x_evm() ||  board_is_bbai())
 667                 return;
 668
 669         /* Only AM571x IDK has gpio control detect.. so check that */
 670         if (board_is_am571x_idk() && !am571x_idk_needs_lcd())
 671                 goto out;
 672
 673         r = i2c_get_chip_for_busnum(OSD_TS_FT_BUS_ADDRESS,
 674                                     OSD_TS_FT_CHIP_ADDRESS, 1, &dev);
 675         if (r) {
 676                 printf("%s: Failed to get I2C device %d/%d (ret %d)\n",
 677                        __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS,
 678                        r);
 679                 /* AM572x IDK has no explicit settings for optional LCD kit */
 680                 if (board_is_am571x_idk())
 681                         printf("%s: Touch screen detect failed: %d!\n",
 682                                __func__, r);
 683                 goto out;
 684         }
 685
 686         /* Read FT ID */
 687         r = dm_i2c_reg_read(dev, OSD_TS_FT_REG_ID);
 688         if (r < 0) {
 689                 printf("%s: Touch screen ID read %d:0x%02x[0x%02x] failed:%d\n",
 690                        __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS,
 691                        OSD_TS_FT_REG_ID, r);
 692                 goto out;
 693         }
 694
 695         switch (r) {
 696         case OSD_TS_FT_ID_5606:
 697                 idk_lcd = "osd101t2045";
 698                 break;
 699         case OSD_TS_FT_ID_5x46:
 700                 idk_lcd = "osd101t2587";
 701                 break;
 702         default:
 703                 printf("%s: Unidentifed Touch screen ID 0x%02x\n",
 704                        __func__, r);
 705                 /* we will let default be "no lcd" */
 706         }
 707 out:
 708         env_set("idk_lcd", idk_lcd);
 709         return;
 710 }
 711
 712 #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
 713 static int device_okay(const char *path)
 714 {
 715         int node;
 716
 717         node = fdt_path_offset(gd->fdt_blob, path);
 718         if (node < 0)
 719                 return 0;
 720
 721         return fdtdec_get_is_enabled(gd->fdt_blob, node);
 722 }
 723 #endif
 724
 725 int board_late_init(void)
 726 {
 727         setup_board_eeprom_env();
 728         u8 val;
 729         struct udevice *dev;
 730
 731         /*
 732          * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
 733          * This is the POWERHOLD-in-Low behavior.
 734          */
 735         palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
 736
 737         /*
 738          * Default FIT boot on HS devices. Non FIT images are not allowed
 739          * on HS devices.
 740          */
 741         if (get_device_type() == HS_DEVICE)
 742                 env_set("boot_fit", "1");
 743
 744         /*
 745          * Set the GPIO7 Pad to POWERHOLD. This has higher priority
 746          * over DEV_CTRL.DEV_ON bit. This can be reset in case of
 747          * PMIC Power off. So to be on the safer side set it back
 748          * to POWERHOLD mode irrespective of the current state.
 749          */
 750         palmas_i2c_read_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
 751                            &val);
 752         val = val | TPS65903X_PAD2_POWERHOLD_MASK;
 753         palmas_i2c_write_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
 754                             val);
 755
 756         omap_die_id_serial();
 757         omap_set_fastboot_vars();
 758
 759         am57x_idk_lcd_detect();
 760
 761         /* Just probe the potentially supported cdce913 device */
 762         uclass_get_device(UCLASS_CLK, 0, &dev);
 763
 764         if (board_is_bbai())
 765                 env_set("console", "ttyS0,115200n8");
 766
 767 #if !defined(CONFIG_SPL_BUILD)
 768         board_ti_set_ethaddr(2);
 769 #endif
 770
 771 #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
 772         if (device_okay("/ocp/omap_dwc3_1@48880000"))
 773                 enable_usb_clocks(0);
 774         if (device_okay("/ocp/omap_dwc3_2@488c0000"))
 775                 enable_usb_clocks(1);
 776 #endif
 777         return 0;
 778 }
 779
 780 void set_muxconf_regs(void)
 781 {
 782         do_set_mux32((*ctrl)->control_padconf_core_base,
 783                      early_padconf, ARRAY_SIZE(early_padconf));
 784
 785 #ifdef CONFIG_SUPPORT_EMMC_BOOT
 786         do_set_mux32((*ctrl)->control_padconf_core_base,
 787                      emmc_padconf, ARRAY_SIZE(emmc_padconf));
 788 #endif
 789 }
 790
 791 #ifdef CONFIG_IODELAY_RECALIBRATION
 792 void recalibrate_iodelay(void)
 793 {
 794         const struct pad_conf_entry *pconf;
 795         const struct iodelay_cfg_entry *iod, *delta_iod;
 796         int pconf_sz, iod_sz, delta_iod_sz = 0;
 797         int ret;
 798
 799         if (board_is_am572x_idk()) {
 800                 pconf = core_padconf_array_essential_am572x_idk;
 801                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk);
 802                 iod = iodelay_cfg_array_am572x_idk;
 803                 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk);
 804         } else if (board_is_am574x_idk()) {
 805                 pconf = core_padconf_array_essential_am574x_idk;
 806                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am574x_idk);
 807                 iod = iodelay_cfg_array_am574x_idk;
 808                 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am574x_idk);
 809         } else if (board_is_am571x_idk()) {
 810                 pconf = core_padconf_array_essential_am571x_idk;
 811                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am571x_idk);
 812                 iod = iodelay_cfg_array_am571x_idk;
 813                 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk);
 814         } else if (board_is_bbai()) {
 815                 pconf = core_padconf_array_essential_bbai;
 816                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_bbai);
 817                 iod = iodelay_cfg_array_bbai;
 818                 iod_sz = ARRAY_SIZE(iodelay_cfg_array_bbai);
 819         } else {
 820                 /* Common for X15/GPEVM */
 821                 pconf = core_padconf_array_essential_x15;
 822                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_x15);
 823                 /* There never was an SR1.0 X15.. So.. */
 824                 if (omap_revision() == DRA752_ES1_1) {
 825                         iod = iodelay_cfg_array_x15_sr1_1;
 826                         iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr1_1);
 827                 } else {
 828                         /* Since full production should switch to SR2.0  */
 829                         iod = iodelay_cfg_array_x15_sr2_0;
 830                         iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr2_0);
 831                 }
 832         }
 833
 834         /* Setup I/O isolation */
 835         ret = __recalibrate_iodelay_start();
 836         if (ret)
 837                 goto err;
 838
 839         /* Do the muxing here */
 840         do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
 841
 842         /* Now do the weird minor deltas that should be safe */
 843         if (board_is_x15() || board_is_am572x_evm()) {
 844                 if (board_is_x15_revb1() || board_is_am572x_evm_reva3() ||
 845                     board_is_x15_revc()) {
 846                         pconf = core_padconf_array_delta_x15_sr2_0;
 847                         pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr2_0);
 848                 } else {
 849                         pconf = core_padconf_array_delta_x15_sr1_1;
 850                         pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr1_1);
 851                 }
 852                 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
 853         }
 854
 855         if (board_is_am571x_idk()) {
 856                 if (am571x_idk_needs_lcd()) {
 857                         pconf = core_padconf_array_vout_am571x_idk;
 858                         pconf_sz = ARRAY_SIZE(core_padconf_array_vout_am571x_idk);
 859                         delta_iod = iodelay_cfg_array_am571x_idk_4port;
 860                         delta_iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk_4port);
 861
 862                 } else {
 863                         pconf = core_padconf_array_icss1eth_am571x_idk;
 864                         pconf_sz = ARRAY_SIZE(core_padconf_array_icss1eth_am571x_idk);
 865                 }
 866                 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
 867         }
 868
 869         /* Setup IOdelay configuration */
 870         ret = do_set_iodelay((*ctrl)->iodelay_config_base, iod, iod_sz);
 871         if (delta_iod_sz)
 872                 ret = do_set_iodelay((*ctrl)->iodelay_config_base, delta_iod,
 873                                      delta_iod_sz);
 874
 875 err:
 876         /* Closeup.. remove isolation */
 877         __recalibrate_iodelay_end(ret);
 878 }
 879 #endif
 880
 881 #if defined(CONFIG_MMC)
 882 int board_mmc_init(bd_t *bis)
 883 {
 884         omap_mmc_init(0, 0, 0, -1, -1);
 885         omap_mmc_init(1, 0, 0, -1, -1);
 886         return 0;
 887 }
 888
 889 static const struct mmc_platform_fixups am57x_es1_1_mmc1_fixups = {
 890         .hw_rev = "rev11",
 891         .unsupported_caps = MMC_CAP(MMC_HS_200) |
 892                             MMC_CAP(UHS_SDR104),
 893         .max_freq = 96000000,
 894 };
 895
 896 static const struct mmc_platform_fixups am57x_es1_1_mmc23_fixups = {
 897         .hw_rev = "rev11",
 898         .unsupported_caps = MMC_CAP(MMC_HS_200) |
 899                             MMC_CAP(UHS_SDR104) |
 900                             MMC_CAP(UHS_SDR50),
 901         .max_freq = 48000000,
 902 };
 903
 904 const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
 905 {
 906         switch (omap_revision()) {
 907         case DRA752_ES1_0:
 908         case DRA752_ES1_1:
 909                 if (addr == OMAP_HSMMC1_BASE)
 910                         return &am57x_es1_1_mmc1_fixups;
 911                 else
 912                         return &am57x_es1_1_mmc23_fixups;
 913         default:
 914                 return NULL;
 915         }
 916 }
 917 #endif
 918
 919 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
 920 int spl_start_uboot(void)
 921 {
 922         /* break into full u-boot on 'c' */
 923         if (serial_tstc() && serial_getc() == 'c')
 924                 return 1;
 925
 926 #ifdef CONFIG_SPL_ENV_SUPPORT
 927         env_init();
 928         env_load();
 929         if (env_get_yesno("boot_os") != 1)
 930                 return 1;
 931 #endif
 932
 933         return 0;
 934 }
 935 #endif
 936
 937 #ifdef CONFIG_DRIVER_TI_CPSW
 938
 939 /* Delay value to add to calibrated value */
 940 #define RGMII0_TXCTL_DLY_VAL            ((0x3 << 5) + 0x8)
 941 #define RGMII0_TXD0_DLY_VAL             ((0x3 << 5) + 0x8)
 942 #define RGMII0_TXD1_DLY_VAL             ((0x3 << 5) + 0x2)
 943 #define RGMII0_TXD2_DLY_VAL             ((0x4 << 5) + 0x0)
 944 #define RGMII0_TXD3_DLY_VAL             ((0x4 << 5) + 0x0)
 945 #define VIN2A_D13_DLY_VAL               ((0x3 << 5) + 0x8)
 946 #define VIN2A_D17_DLY_VAL               ((0x3 << 5) + 0x8)
 947 #define VIN2A_D16_DLY_VAL               ((0x3 << 5) + 0x2)
 948 #define VIN2A_D15_DLY_VAL               ((0x4 << 5) + 0x0)
 949 #define VIN2A_D14_DLY_VAL               ((0x4 << 5) + 0x0)
 950
 951 static void cpsw_control(int enabled)
 952 {
 953         /* VTP can be added here */
 954 }
 955
 956 static struct cpsw_slave_data cpsw_slaves[] = {
 957         {
 958                 .slave_reg_ofs  = 0x208,
 959                 .sliver_reg_ofs = 0xd80,
 960                 .phy_addr       = 1,
 961         },
 962         {
 963                 .slave_reg_ofs  = 0x308,
 964                 .sliver_reg_ofs = 0xdc0,
 965                 .phy_addr       = 2,
 966         },
 967 };
 968
 969 static struct cpsw_platform_data cpsw_data = {
 970         .mdio_base              = CPSW_MDIO_BASE,
 971         .cpsw_base              = CPSW_BASE,
 972         .mdio_div               = 0xff,
 973         .channels               = 8,
 974         .cpdma_reg_ofs          = 0x800,
 975         .slaves                 = 1,
 976         .slave_data             = cpsw_slaves,
 977         .ale_reg_ofs            = 0xd00,
 978         .ale_entries            = 1024,
 979         .host_port_reg_ofs      = 0x108,
 980         .hw_stats_reg_ofs       = 0x900,
 981         .bd_ram_ofs             = 0x2000,
 982         .mac_control            = (1 << 5),
 983         .control                = cpsw_control,
 984         .host_port_num          = 0,
 985         .version                = CPSW_CTRL_VERSION_2,
 986 };
 987
 988 static u64 mac_to_u64(u8 mac[6])
 989 {
 990         int i;
 991         u64 addr = 0;
 992
 993         for (i = 0; i < 6; i++) {
 994                 addr <<= 8;
 995                 addr |= mac[i];
 996         }
 997
 998         return addr;
 999 }
1000
1001 static void u64_to_mac(u64 addr, u8 mac[6])
1002 {
1003         mac[5] = addr;
1004         mac[4] = addr >> 8;
1005         mac[3] = addr >> 16;
1006         mac[2] = addr >> 24;
1007         mac[1] = addr >> 32;
1008         mac[0] = addr >> 40;
1009 }
1010
1011 int board_eth_init(bd_t *bis)
1012 {
1013         int ret;
1014         uint8_t mac_addr[6];
1015         uint32_t mac_hi, mac_lo;
1016         uint32_t ctrl_val;
1017         int i;
1018         u64 mac1, mac2;
1019         u8 mac_addr1[6], mac_addr2[6];
1020         int num_macs;
1021
1022         /* try reading mac address from efuse */
1023         mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
1024         mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
1025         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
1026         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
1027         mac_addr[2] = mac_hi & 0xFF;
1028         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
1029         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
1030         mac_addr[5] = mac_lo & 0xFF;
1031
1032         if (!env_get("ethaddr")) {
1033                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
1034
1035                 if (is_valid_ethaddr(mac_addr))
1036                         eth_env_set_enetaddr("ethaddr", mac_addr);
1037         }
1038
1039         mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
1040         mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
1041         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
1042         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
1043         mac_addr[2] = mac_hi & 0xFF;
1044         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
1045         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
1046         mac_addr[5] = mac_lo & 0xFF;
1047
1048         if (!env_get("eth1addr")) {
1049                 if (is_valid_ethaddr(mac_addr))
1050                         eth_env_set_enetaddr("eth1addr", mac_addr);
1051         }
1052
1053         ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
1054         ctrl_val |= 0x22;
1055         writel(ctrl_val, (*ctrl)->control_core_control_io1);
1056
1057         /* The phy address for the AM57xx IDK are different than x15 */
1058         if (board_is_am572x_idk() || board_is_am571x_idk() ||
1059             board_is_am574x_idk()) {
1060                 cpsw_data.slave_data[0].phy_addr = 0;
1061                 cpsw_data.slave_data[1].phy_addr = 1;
1062         }
1063
1064         ret = cpsw_register(&cpsw_data);
1065         if (ret < 0)
1066                 printf("Error %d registering CPSW switch\n", ret);
1067
1068         /*
1069          * Export any Ethernet MAC addresses from EEPROM.
1070          * On AM57xx the 2 MAC addresses define the address range
1071          */
1072         board_ti_get_eth_mac_addr(0, mac_addr1);
1073         board_ti_get_eth_mac_addr(1, mac_addr2);
1074
1075         if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) {
1076                 mac1 = mac_to_u64(mac_addr1);
1077                 mac2 = mac_to_u64(mac_addr2);
1078
1079                 /* must contain an address range */
1080                 num_macs = mac2 - mac1 + 1;
1081                 /* <= 50 to protect against user programming error */
1082                 if (num_macs > 0 && num_macs <= 50) {
1083                         for (i = 0; i < num_macs; i++) {
1084                                 u64_to_mac(mac1 + i, mac_addr);
1085                                 if (is_valid_ethaddr(mac_addr)) {
1086                                         eth_env_set_enetaddr_by_index("eth",
1087                                                                       i + 2,
1088                                                                       mac_addr);
1089                                 }
1090                         }
1091                 }
1092         }
1093
1094         return ret;
1095 }
1096 #endif
1097
1098 #ifdef CONFIG_BOARD_EARLY_INIT_F
1099 /* VTT regulator enable */
1100 static inline void vtt_regulator_enable(void)
1101 {
1102         if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
1103                 return;
1104
1105         gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
1106         gpio_direction_output(GPIO_DDR_VTT_EN, 1);
1107 }
1108
1109 int board_early_init_f(void)
1110 {
1111         vtt_regulator_enable();
1112         return 0;
1113 }
1114 #endif
1115
1116 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
1117 int ft_board_setup(void *blob, bd_t *bd)
1118 {
1119         ft_cpu_setup(blob, bd);
1120
1121         return 0;
1122 }
1123 #endif
1124
1125 #ifdef CONFIG_SPL_LOAD_FIT
1126 int board_fit_config_name_match(const char *name)
1127 {
1128         if (board_is_x15()) {
1129                 if (board_is_x15_revb1()) {
1130                         if (!strcmp(name, "am57xx-beagle-x15-revb1"))
1131                                 return 0;
1132                 } else if (board_is_x15_revc()) {
1133                         if (!strcmp(name, "am57xx-beagle-x15-revc"))
1134                                 return 0;
1135                 } else if (!strcmp(name, "am57xx-beagle-x15")) {
1136                         return 0;
1137                 }
1138         } else if (board_is_am572x_evm() &&
1139                    !strcmp(name, "am57xx-beagle-x15")) {
1140                 return 0;
1141         } else if (board_is_am572x_idk() && !strcmp(name, "am572x-idk")) {
1142                 return 0;
1143         } else if (board_is_am574x_idk() && !strcmp(name, "am574x-idk")) {
1144                 return 0;
1145         } else if (board_is_am571x_idk() && !strcmp(name, "am571x-idk")) {
1146                 return 0;
1147         } else if (board_is_bbai() && !strcmp(name, "am5729-beagleboneai")) {
1148                 return 0;
1149         }
1150
1151         return -1;
1152 }
1153 #endif
1154
1155 #if CONFIG_IS_ENABLED(FASTBOOT) && !CONFIG_IS_ENABLED(ENV_IS_NOWHERE)
1156 int fastboot_set_reboot_flag(void)
1157 {
1158         printf("Setting reboot to fastboot flag ...\n");
1159         env_set("dofastboot", "1");
1160         env_save();
1161         return 0;
1162 }
1163 #endif
1164
1165 #ifdef CONFIG_SUPPORT_EMMC_BOOT
1166 static int board_bootmode_has_emmc(void)
1167 {
1168         /* Check that boot mode is same as BBAI */
1169         if (gd->arch.omap_boot_mode != 2)
1170                 return -EIO;
1171
1172         return 0;
1173 }
1174 #endif
1175
1176 #ifdef CONFIG_TI_SECURE_DEVICE
1177 void board_fit_image_post_process(void **p_image, size_t *p_size)
1178 {
1179         secure_boot_verify_image(p_image, p_size);
1180 }
1181
1182 void board_tee_image_process(ulong tee_image, size_t tee_size)
1183 {
1184         secure_tee_install((u32)tee_image);
1185 }
1186
1187 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
1188 #endif