1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
5 * Author: Felipe Balbi <balbi@ti.com>
7 * Based on board/ti/dra7xx/evm.c
12 #include <fdt_support.h>
20 #include <asm/omap_common.h>
21 #include <asm/omap_sec_common.h>
24 #include <asm/arch/gpio.h>
25 #include <asm/arch/clock.h>
26 #include <asm/arch/dra7xx_iodelay.h>
27 #include <asm/arch/sys_proto.h>
28 #include <asm/arch/mmc_host_def.h>
29 #include <asm/arch/sata.h>
30 #include <asm/arch/gpio.h>
31 #include <asm/arch/omap.h>
33 #include <linux/usb/gadget.h>
34 #include <dwc3-uboot.h>
35 #include <dwc3-omap-uboot.h>
36 #include <ti-usb-phy-uboot.h>
38 #include <dm/uclass.h>
41 #include "../common/board_detect.h"
44 #ifdef CONFIG_SUPPORT_EMMC_BOOT
45 static int board_bootmode_has_emmc(void);
48 #define board_is_x15() board_ti_is("BBRDX15_")
49 #define board_is_x15_revb1() (board_ti_is("BBRDX15_") && \
50 !strncmp("B.10", board_ti_get_rev(), 3))
51 #define board_is_x15_revc() (board_ti_is("BBRDX15_") && \
52 !strncmp("C.00", board_ti_get_rev(), 3))
53 #define board_is_am572x_evm() board_ti_is("AM572PM_")
54 #define board_is_am572x_evm_reva3() \
55 (board_ti_is("AM572PM_") && \
56 !strncmp("A.30", board_ti_get_rev(), 3))
57 #define board_is_am574x_idk() board_ti_is("AM574IDK")
58 #define board_is_am572x_idk() board_ti_is("AM572IDK")
59 #define board_is_am571x_idk() board_ti_is("AM571IDK")
60 #define board_is_bbai() board_ti_is("BBONE-AI")
62 #ifdef CONFIG_DRIVER_TI_CPSW
66 DECLARE_GLOBAL_DATA_PTR;
68 #define GPIO_ETH_LCD GPIO_TO_PIN(2, 22)
70 #define GPIO_DDR_VTT_EN 203
72 /* Touch screen controller to identify the LCD */
73 #define OSD_TS_FT_BUS_ADDRESS 0
74 #define OSD_TS_FT_CHIP_ADDRESS 0x38
75 #define OSD_TS_FT_REG_ID 0xA3
77 * Touchscreen IDs for various OSD panels
78 * Ref: http://www.osddisplays.com/TI/OSD101T2587-53TS_A.1.pdf
80 /* Used on newer osd101t2587 Panels */
81 #define OSD_TS_FT_ID_5x46 0x54
82 /* Used on older osd101t2045 Panels */
83 #define OSD_TS_FT_ID_5606 0x08
85 #define SYSINFO_BOARD_NAME_MAX_LEN 45
87 #define TPS65903X_PRIMARY_SECONDARY_PAD2 0xFB
88 #define TPS65903X_PAD2_POWERHOLD_MASK 0x20
90 const struct omap_sysinfo sysinfo = {
91 "Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n"
94 static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
95 .dmm_lisa_map_3 = 0x80740300,
99 static const struct dmm_lisa_map_regs am571x_idk_lisa_regs = {
100 .dmm_lisa_map_3 = 0x80640100,
104 static const struct dmm_lisa_map_regs am574x_idk_lisa_regs = {
105 .dmm_lisa_map_2 = 0xc0600200,
106 .dmm_lisa_map_3 = 0x80600100,
110 static const struct dmm_lisa_map_regs bbai_lisa_regs = {
111 .dmm_lisa_map_3 = 0x80640100,
115 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
117 if (board_is_am571x_idk())
118 *dmm_lisa_regs = &am571x_idk_lisa_regs;
119 else if (board_is_am574x_idk())
120 *dmm_lisa_regs = &am574x_idk_lisa_regs;
121 else if (board_is_bbai())
122 *dmm_lisa_regs = &bbai_lisa_regs;
124 *dmm_lisa_regs = &beagle_x15_lisa_regs;
127 static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
128 .sdram_config_init = 0x61851b32,
129 .sdram_config = 0x61851b32,
130 .sdram_config2 = 0x08000000,
131 .ref_ctrl = 0x000040F1,
132 .ref_ctrl_final = 0x00001035,
133 .sdram_tim1 = 0xcccf36ab,
134 .sdram_tim2 = 0x308f7fda,
135 .sdram_tim3 = 0x409f88a8,
136 .read_idle_ctrl = 0x00050000,
137 .zq_config = 0x5007190b,
138 .temp_alert_config = 0x00000000,
139 .emif_ddr_phy_ctlr_1_init = 0x0024400b,
140 .emif_ddr_phy_ctlr_1 = 0x0e24400b,
141 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
142 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
143 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
144 .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
145 .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
146 .emif_rd_wr_lvl_rmp_win = 0x00000000,
147 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
148 .emif_rd_wr_lvl_ctl = 0x00000000,
149 .emif_rd_wr_exec_thresh = 0x00000305
152 /* Ext phy ctrl regs 1-35 */
153 static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
191 static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
192 .sdram_config_init = 0x61851b32,
193 .sdram_config = 0x61851b32,
194 .sdram_config2 = 0x08000000,
195 .ref_ctrl = 0x000040F1,
196 .ref_ctrl_final = 0x00001035,
197 .sdram_tim1 = 0xcccf36b3,
198 .sdram_tim2 = 0x308f7fda,
199 .sdram_tim3 = 0x407f88a8,
200 .read_idle_ctrl = 0x00050000,
201 .zq_config = 0x5007190b,
202 .temp_alert_config = 0x00000000,
203 .emif_ddr_phy_ctlr_1_init = 0x0024400b,
204 .emif_ddr_phy_ctlr_1 = 0x0e24400b,
205 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
206 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
207 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
208 .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
209 .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
210 .emif_rd_wr_lvl_rmp_win = 0x00000000,
211 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
212 .emif_rd_wr_lvl_ctl = 0x00000000,
213 .emif_rd_wr_exec_thresh = 0x00000305
216 static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
254 static const struct emif_regs am571x_emif1_ddr3_666mhz_emif_regs = {
255 .sdram_config_init = 0x61863332,
256 .sdram_config = 0x61863332,
257 .sdram_config2 = 0x08000000,
258 .ref_ctrl = 0x0000514d,
259 .ref_ctrl_final = 0x0000144a,
260 .sdram_tim1 = 0xd333887c,
261 .sdram_tim2 = 0x30b37fe3,
262 .sdram_tim3 = 0x409f8ad8,
263 .read_idle_ctrl = 0x00050000,
264 .zq_config = 0x5007190b,
265 .temp_alert_config = 0x00000000,
266 .emif_ddr_phy_ctlr_1_init = 0x0024400f,
267 .emif_ddr_phy_ctlr_1 = 0x0e24400f,
268 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
269 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
270 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
271 .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
272 .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
273 .emif_rd_wr_lvl_rmp_win = 0x00000000,
274 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
275 .emif_rd_wr_lvl_ctl = 0x00000000,
276 .emif_rd_wr_exec_thresh = 0x00000305
279 static const struct emif_regs am574x_emif1_ddr3_666mhz_emif_ecc_regs = {
280 .sdram_config_init = 0x61863332,
281 .sdram_config = 0x61863332,
282 .sdram_config2 = 0x08000000,
283 .ref_ctrl = 0x0000514d,
284 .ref_ctrl_final = 0x0000144a,
285 .sdram_tim1 = 0xd333887c,
286 .sdram_tim2 = 0x30b37fe3,
287 .sdram_tim3 = 0x409f8ad8,
288 .read_idle_ctrl = 0x00050000,
289 .zq_config = 0x5007190b,
290 .temp_alert_config = 0x00000000,
291 .emif_ddr_phy_ctlr_1_init = 0x0024400f,
292 .emif_ddr_phy_ctlr_1 = 0x0e24400f,
293 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
294 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
295 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
296 .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
297 .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
298 .emif_rd_wr_lvl_rmp_win = 0x00000000,
299 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
300 .emif_rd_wr_lvl_ctl = 0x00000000,
301 .emif_rd_wr_exec_thresh = 0x00000305,
302 .emif_ecc_ctrl_reg = 0xD0000001,
303 .emif_ecc_address_range_1 = 0x3FFF0000,
304 .emif_ecc_address_range_2 = 0x00000000
307 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
311 if (board_is_am571x_idk())
312 *regs = &am571x_emif1_ddr3_666mhz_emif_regs;
313 else if (board_is_am574x_idk())
314 *regs = &am574x_emif1_ddr3_666mhz_emif_ecc_regs;
316 *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
319 if (board_is_am574x_idk())
320 *regs = &am571x_emif1_ddr3_666mhz_emif_regs;
322 *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
327 void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
331 *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
332 *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
335 *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
336 *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
341 struct vcores_data beagle_x15_volts = {
342 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
343 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
344 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
345 .mpu.addr = TPS659038_REG_ADDR_SMPS12,
346 .mpu.pmic = &tps659038,
347 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
349 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
350 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
351 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
352 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
353 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
354 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
355 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
356 .eve.addr = TPS659038_REG_ADDR_SMPS45,
357 .eve.pmic = &tps659038,
358 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
360 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
361 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
362 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
363 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
364 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
365 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
366 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
367 .gpu.addr = TPS659038_REG_ADDR_SMPS45,
368 .gpu.pmic = &tps659038,
369 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
371 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
372 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
373 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
374 .core.addr = TPS659038_REG_ADDR_SMPS6,
375 .core.pmic = &tps659038,
377 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
378 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
379 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
380 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
381 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
382 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
383 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
384 .iva.addr = TPS659038_REG_ADDR_SMPS45,
385 .iva.pmic = &tps659038,
386 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
389 struct vcores_data am572x_idk_volts = {
390 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
391 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
392 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
393 .mpu.addr = TPS659038_REG_ADDR_SMPS12,
394 .mpu.pmic = &tps659038,
395 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
397 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
398 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
399 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
400 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
401 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
402 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
403 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
404 .eve.addr = TPS659038_REG_ADDR_SMPS45,
405 .eve.pmic = &tps659038,
406 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
408 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
409 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
410 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
411 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
412 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
413 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
414 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
415 .gpu.addr = TPS659038_REG_ADDR_SMPS6,
416 .gpu.pmic = &tps659038,
417 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
419 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
420 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
421 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
422 .core.addr = TPS659038_REG_ADDR_SMPS7,
423 .core.pmic = &tps659038,
425 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
426 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
427 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
428 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
429 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
430 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
431 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
432 .iva.addr = TPS659038_REG_ADDR_SMPS8,
433 .iva.pmic = &tps659038,
434 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
437 struct vcores_data am571x_idk_volts = {
438 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
439 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
440 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
441 .mpu.addr = TPS659038_REG_ADDR_SMPS12,
442 .mpu.pmic = &tps659038,
443 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
445 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
446 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
447 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
448 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
449 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
450 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
451 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
452 .eve.addr = TPS659038_REG_ADDR_SMPS45,
453 .eve.pmic = &tps659038,
454 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
456 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
457 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
458 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
459 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
460 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
461 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
462 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
463 .gpu.addr = TPS659038_REG_ADDR_SMPS6,
464 .gpu.pmic = &tps659038,
465 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
467 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
468 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
469 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
470 .core.addr = TPS659038_REG_ADDR_SMPS7,
471 .core.pmic = &tps659038,
473 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
474 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
475 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
476 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
477 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
478 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
479 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
480 .iva.addr = TPS659038_REG_ADDR_SMPS45,
481 .iva.pmic = &tps659038,
482 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
485 int get_voltrail_opp(int rail_offset)
489 switch (rail_offset) {
500 opp = DRA7_DSPEVE_OPP;
513 #ifdef CONFIG_SPL_BUILD
514 /* No env to setup for SPL */
515 static inline void setup_board_eeprom_env(void) { }
517 /* Override function to read eeprom information */
518 void do_board_detect(void)
522 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
523 CONFIG_EEPROM_CHIP_ADDRESS);
525 printf("ti_i2c_eeprom_init failed %d\n", rc);
527 #ifdef CONFIG_SUPPORT_EMMC_BOOT
528 rc = board_bootmode_has_emmc();
530 rc = ti_emmc_boardid_get();
532 printf("ti_emmc_boardid_get failed %d\n", rc);
536 #else /* CONFIG_SPL_BUILD */
538 /* Override function to read eeprom information: actual i2c read done by SPL*/
539 void do_board_detect(void)
544 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
545 CONFIG_EEPROM_CHIP_ADDRESS);
547 printf("ti_i2c_eeprom_init failed %d\n", rc);
549 #ifdef CONFIG_SUPPORT_EMMC_BOOT
550 rc = board_bootmode_has_emmc();
552 rc = ti_emmc_boardid_get();
554 printf("ti_emmc_boardid_get failed %d\n", rc);
558 bname = "BeagleBoard X15";
559 else if (board_is_am572x_evm())
560 bname = "AM572x EVM";
561 else if (board_is_am574x_idk())
562 bname = "AM574x IDK";
563 else if (board_is_am572x_idk())
564 bname = "AM572x IDK";
565 else if (board_is_am571x_idk())
566 bname = "AM571x IDK";
567 else if (board_is_bbai())
568 bname = "BeagleBone AI";
571 snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
572 "Board: %s REV %s\n", bname, board_ti_get_rev());
575 static void setup_board_eeprom_env(void)
577 char *name = "beagle_x15";
580 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
581 CONFIG_EEPROM_CHIP_ADDRESS);
585 if (board_is_x15()) {
586 if (board_is_x15_revb1())
587 name = "beagle_x15_revb1";
588 else if (board_is_x15_revc())
589 name = "beagle_x15_revc";
592 } else if (board_is_am572x_evm()) {
593 if (board_is_am572x_evm_reva3())
594 name = "am57xx_evm_reva3";
597 } else if (board_is_am574x_idk()) {
599 } else if (board_is_am572x_idk()) {
601 } else if (board_is_am571x_idk()) {
603 } else if (board_is_bbai()) {
604 name = "am5729_beagleboneai";
606 printf("Unidentified board claims %s in eeprom header\n",
607 board_ti_get_name());
611 set_board_info_env(name);
614 #endif /* CONFIG_SPL_BUILD */
616 void vcores_init(void)
618 if (board_is_am572x_idk() || board_is_am574x_idk())
619 *omap_vcores = &am572x_idk_volts;
620 else if (board_is_am571x_idk())
621 *omap_vcores = &am571x_idk_volts;
623 *omap_vcores = &beagle_x15_volts;
626 void hw_data_init(void)
628 *prcm = &dra7xx_prcm;
630 *dplls_data = &dra72x_dplls;
631 else if (is_dra76x())
632 *dplls_data = &dra76x_dplls;
634 *dplls_data = &dra7xx_dplls;
635 *ctrl = &dra7xx_ctrl;
638 bool am571x_idk_needs_lcd(void)
642 gpio_request(GPIO_ETH_LCD, "nLCD_Detect");
643 if (gpio_get_value(GPIO_ETH_LCD))
648 gpio_free(GPIO_ETH_LCD);
656 gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
661 void am57x_idk_lcd_detect(void)
664 char *idk_lcd = "no";
667 /* Only valid for IDKs */
668 if (board_is_x15() || board_is_am572x_evm() || board_is_bbai())
671 /* Only AM571x IDK has gpio control detect.. so check that */
672 if (board_is_am571x_idk() && !am571x_idk_needs_lcd())
675 r = i2c_get_chip_for_busnum(OSD_TS_FT_BUS_ADDRESS,
676 OSD_TS_FT_CHIP_ADDRESS, 1, &dev);
678 printf("%s: Failed to get I2C device %d/%d (ret %d)\n",
679 __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS,
681 /* AM572x IDK has no explicit settings for optional LCD kit */
682 if (board_is_am571x_idk())
683 printf("%s: Touch screen detect failed: %d!\n",
689 r = dm_i2c_reg_read(dev, OSD_TS_FT_REG_ID);
691 printf("%s: Touch screen ID read %d:0x%02x[0x%02x] failed:%d\n",
692 __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS,
693 OSD_TS_FT_REG_ID, r);
698 case OSD_TS_FT_ID_5606:
699 idk_lcd = "osd101t2045";
701 case OSD_TS_FT_ID_5x46:
702 idk_lcd = "osd101t2587";
705 printf("%s: Unidentifed Touch screen ID 0x%02x\n",
707 /* we will let default be "no lcd" */
710 env_set("idk_lcd", idk_lcd);
713 * On AM571x_IDK, no Display with J51 set to LCD is considered as an
714 * invalid configuration and we prevent boot to get user attention.
716 if (board_is_am571x_idk() && am571x_idk_needs_lcd() &&
717 !strncmp(idk_lcd, "no", 2)) {
718 printf("%s: Invalid HW configuration: display not detected/supported but J51 is set. Remove J51 to boot without display.\n",
726 #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
727 static int device_okay(const char *path)
731 node = fdt_path_offset(gd->fdt_blob, path);
735 return fdtdec_get_is_enabled(gd->fdt_blob, node);
739 int board_late_init(void)
741 setup_board_eeprom_env();
746 * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
747 * This is the POWERHOLD-in-Low behavior.
749 palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
752 * Default FIT boot on HS devices. Non FIT images are not allowed
755 if (get_device_type() == HS_DEVICE)
756 env_set("boot_fit", "1");
759 * Set the GPIO7 Pad to POWERHOLD. This has higher priority
760 * over DEV_CTRL.DEV_ON bit. This can be reset in case of
761 * PMIC Power off. So to be on the safer side set it back
762 * to POWERHOLD mode irrespective of the current state.
764 palmas_i2c_read_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
766 val = val | TPS65903X_PAD2_POWERHOLD_MASK;
767 palmas_i2c_write_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
770 omap_die_id_serial();
771 omap_set_fastboot_vars();
773 am57x_idk_lcd_detect();
775 /* Just probe the potentially supported cdce913 device */
776 uclass_get_device(UCLASS_CLK, 0, &dev);
779 env_set("console", "ttyS0,115200n8");
781 #if !defined(CONFIG_SPL_BUILD)
782 board_ti_set_ethaddr(2);
785 #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
786 if (device_okay("/ocp/omap_dwc3_1@48880000"))
787 enable_usb_clocks(0);
788 if (device_okay("/ocp/omap_dwc3_2@488c0000"))
789 enable_usb_clocks(1);
794 void set_muxconf_regs(void)
796 do_set_mux32((*ctrl)->control_padconf_core_base,
797 early_padconf, ARRAY_SIZE(early_padconf));
799 #ifdef CONFIG_SUPPORT_EMMC_BOOT
800 do_set_mux32((*ctrl)->control_padconf_core_base,
801 emmc_padconf, ARRAY_SIZE(emmc_padconf));
805 #ifdef CONFIG_IODELAY_RECALIBRATION
806 void recalibrate_iodelay(void)
808 const struct pad_conf_entry *pconf;
809 const struct iodelay_cfg_entry *iod, *delta_iod;
810 int pconf_sz, iod_sz, delta_iod_sz = 0;
813 if (board_is_am572x_idk()) {
814 pconf = core_padconf_array_essential_am572x_idk;
815 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk);
816 iod = iodelay_cfg_array_am572x_idk;
817 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk);
818 } else if (board_is_am574x_idk()) {
819 pconf = core_padconf_array_essential_am574x_idk;
820 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am574x_idk);
821 iod = iodelay_cfg_array_am574x_idk;
822 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am574x_idk);
823 } else if (board_is_am571x_idk()) {
824 pconf = core_padconf_array_essential_am571x_idk;
825 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am571x_idk);
826 iod = iodelay_cfg_array_am571x_idk;
827 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk);
828 } else if (board_is_bbai()) {
829 pconf = core_padconf_array_essential_bbai;
830 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_bbai);
831 iod = iodelay_cfg_array_bbai;
832 iod_sz = ARRAY_SIZE(iodelay_cfg_array_bbai);
834 /* Common for X15/GPEVM */
835 pconf = core_padconf_array_essential_x15;
836 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_x15);
837 /* There never was an SR1.0 X15.. So.. */
838 if (omap_revision() == DRA752_ES1_1) {
839 iod = iodelay_cfg_array_x15_sr1_1;
840 iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr1_1);
842 /* Since full production should switch to SR2.0 */
843 iod = iodelay_cfg_array_x15_sr2_0;
844 iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr2_0);
848 /* Setup I/O isolation */
849 ret = __recalibrate_iodelay_start();
853 /* Do the muxing here */
854 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
856 /* Now do the weird minor deltas that should be safe */
857 if (board_is_x15() || board_is_am572x_evm()) {
858 if (board_is_x15_revb1() || board_is_am572x_evm_reva3() ||
859 board_is_x15_revc()) {
860 pconf = core_padconf_array_delta_x15_sr2_0;
861 pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr2_0);
863 pconf = core_padconf_array_delta_x15_sr1_1;
864 pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr1_1);
866 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
869 if (board_is_am571x_idk()) {
870 if (am571x_idk_needs_lcd()) {
871 pconf = core_padconf_array_vout_am571x_idk;
872 pconf_sz = ARRAY_SIZE(core_padconf_array_vout_am571x_idk);
873 delta_iod = iodelay_cfg_array_am571x_idk_4port;
874 delta_iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk_4port);
877 pconf = core_padconf_array_icss1eth_am571x_idk;
878 pconf_sz = ARRAY_SIZE(core_padconf_array_icss1eth_am571x_idk);
880 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
883 /* Setup IOdelay configuration */
884 ret = do_set_iodelay((*ctrl)->iodelay_config_base, iod, iod_sz);
886 ret = do_set_iodelay((*ctrl)->iodelay_config_base, delta_iod,
890 /* Closeup.. remove isolation */
891 __recalibrate_iodelay_end(ret);
895 #if defined(CONFIG_MMC)
896 int board_mmc_init(bd_t *bis)
898 omap_mmc_init(0, 0, 0, -1, -1);
899 omap_mmc_init(1, 0, 0, -1, -1);
903 static const struct mmc_platform_fixups am57x_es1_1_mmc1_fixups = {
905 .unsupported_caps = MMC_CAP(MMC_HS_200) |
907 .max_freq = 96000000,
910 static const struct mmc_platform_fixups am57x_es1_1_mmc23_fixups = {
912 .unsupported_caps = MMC_CAP(MMC_HS_200) |
913 MMC_CAP(UHS_SDR104) |
915 .max_freq = 48000000,
918 const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
920 switch (omap_revision()) {
923 if (addr == OMAP_HSMMC1_BASE)
924 return &am57x_es1_1_mmc1_fixups;
926 return &am57x_es1_1_mmc23_fixups;
933 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
934 int spl_start_uboot(void)
936 /* break into full u-boot on 'c' */
937 if (serial_tstc() && serial_getc() == 'c')
940 #ifdef CONFIG_SPL_ENV_SUPPORT
943 if (env_get_yesno("boot_os") != 1)
951 #ifdef CONFIG_DRIVER_TI_CPSW
953 /* Delay value to add to calibrated value */
954 #define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8)
955 #define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8)
956 #define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2)
957 #define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0)
958 #define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0)
959 #define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8)
960 #define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8)
961 #define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2)
962 #define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0)
963 #define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0)
965 static void cpsw_control(int enabled)
967 /* VTP can be added here */
970 static struct cpsw_slave_data cpsw_slaves[] = {
972 .slave_reg_ofs = 0x208,
973 .sliver_reg_ofs = 0xd80,
977 .slave_reg_ofs = 0x308,
978 .sliver_reg_ofs = 0xdc0,
983 static struct cpsw_platform_data cpsw_data = {
984 .mdio_base = CPSW_MDIO_BASE,
985 .cpsw_base = CPSW_BASE,
988 .cpdma_reg_ofs = 0x800,
990 .slave_data = cpsw_slaves,
991 .ale_reg_ofs = 0xd00,
993 .host_port_reg_ofs = 0x108,
994 .hw_stats_reg_ofs = 0x900,
995 .bd_ram_ofs = 0x2000,
996 .mac_control = (1 << 5),
997 .control = cpsw_control,
999 .version = CPSW_CTRL_VERSION_2,
1002 static u64 mac_to_u64(u8 mac[6])
1007 for (i = 0; i < 6; i++) {
1015 static void u64_to_mac(u64 addr, u8 mac[6])
1019 mac[3] = addr >> 16;
1020 mac[2] = addr >> 24;
1021 mac[1] = addr >> 32;
1022 mac[0] = addr >> 40;
1025 int board_eth_init(bd_t *bis)
1028 uint8_t mac_addr[6];
1029 uint32_t mac_hi, mac_lo;
1033 u8 mac_addr1[6], mac_addr2[6];
1036 /* try reading mac address from efuse */
1037 mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
1038 mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
1039 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
1040 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
1041 mac_addr[2] = mac_hi & 0xFF;
1042 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
1043 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
1044 mac_addr[5] = mac_lo & 0xFF;
1046 if (!env_get("ethaddr")) {
1047 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
1049 if (is_valid_ethaddr(mac_addr))
1050 eth_env_set_enetaddr("ethaddr", mac_addr);
1053 mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
1054 mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
1055 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
1056 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
1057 mac_addr[2] = mac_hi & 0xFF;
1058 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
1059 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
1060 mac_addr[5] = mac_lo & 0xFF;
1062 if (!env_get("eth1addr")) {
1063 if (is_valid_ethaddr(mac_addr))
1064 eth_env_set_enetaddr("eth1addr", mac_addr);
1067 ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
1069 writel(ctrl_val, (*ctrl)->control_core_control_io1);
1071 /* The phy address for the AM57xx IDK are different than x15 */
1072 if (board_is_am572x_idk() || board_is_am571x_idk() ||
1073 board_is_am574x_idk()) {
1074 cpsw_data.slave_data[0].phy_addr = 0;
1075 cpsw_data.slave_data[1].phy_addr = 1;
1078 ret = cpsw_register(&cpsw_data);
1080 printf("Error %d registering CPSW switch\n", ret);
1083 * Export any Ethernet MAC addresses from EEPROM.
1084 * On AM57xx the 2 MAC addresses define the address range
1086 board_ti_get_eth_mac_addr(0, mac_addr1);
1087 board_ti_get_eth_mac_addr(1, mac_addr2);
1089 if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) {
1090 mac1 = mac_to_u64(mac_addr1);
1091 mac2 = mac_to_u64(mac_addr2);
1093 /* must contain an address range */
1094 num_macs = mac2 - mac1 + 1;
1095 /* <= 50 to protect against user programming error */
1096 if (num_macs > 0 && num_macs <= 50) {
1097 for (i = 0; i < num_macs; i++) {
1098 u64_to_mac(mac1 + i, mac_addr);
1099 if (is_valid_ethaddr(mac_addr)) {
1100 eth_env_set_enetaddr_by_index("eth",
1112 #ifdef CONFIG_BOARD_EARLY_INIT_F
1113 /* VTT regulator enable */
1114 static inline void vtt_regulator_enable(void)
1116 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
1119 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
1120 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
1123 int board_early_init_f(void)
1125 vtt_regulator_enable();
1130 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
1131 int ft_board_setup(void *blob, bd_t *bd)
1133 ft_cpu_setup(blob, bd);
1139 #ifdef CONFIG_SPL_LOAD_FIT
1140 int board_fit_config_name_match(const char *name)
1142 if (board_is_x15()) {
1143 if (board_is_x15_revb1()) {
1144 if (!strcmp(name, "am57xx-beagle-x15-revb1"))
1146 } else if (board_is_x15_revc()) {
1147 if (!strcmp(name, "am57xx-beagle-x15-revc"))
1149 } else if (!strcmp(name, "am57xx-beagle-x15")) {
1152 } else if (board_is_am572x_evm() &&
1153 !strcmp(name, "am57xx-beagle-x15")) {
1155 } else if (board_is_am572x_idk() && !strcmp(name, "am572x-idk")) {
1157 } else if (board_is_am574x_idk() && !strcmp(name, "am574x-idk")) {
1159 } else if (board_is_am571x_idk() && !strcmp(name, "am571x-idk")) {
1161 } else if (board_is_bbai() && !strcmp(name, "am5729-beagleboneai")) {
1169 #if CONFIG_IS_ENABLED(FASTBOOT) && !CONFIG_IS_ENABLED(ENV_IS_NOWHERE)
1170 int fastboot_set_reboot_flag(void)
1172 printf("Setting reboot to fastboot flag ...\n");
1173 env_set("dofastboot", "1");
1179 #ifdef CONFIG_SUPPORT_EMMC_BOOT
1180 static int board_bootmode_has_emmc(void)
1182 /* Check that boot mode is same as BBAI */
1183 if (gd->arch.omap_boot_mode != 2)
1190 #ifdef CONFIG_TI_SECURE_DEVICE
1191 void board_fit_image_post_process(void **p_image, size_t *p_size)
1193 secure_boot_verify_image(p_image, p_size);
1196 void board_tee_image_process(ulong tee_image, size_t tee_size)
1198 secure_tee_install((u32)tee_image);
1201 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);