4 * Board functions for TI AM43XX based boards
6 * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
8 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/errno.h>
15 #include <asm/arch/clock.h>
16 #include <asm/arch/sys_proto.h>
17 #include <asm/arch/mux.h>
18 #include <asm/arch/ddr_defs.h>
19 #include <asm/arch/gpio.h>
22 #include <power/tps65218.h>
26 DECLARE_GLOBAL_DATA_PTR;
28 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
31 * Read header information from EEPROM into global structure.
33 static int read_eeprom(struct am43xx_board_id *header)
35 /* Check if baseboard eeprom is available */
36 if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
37 printf("Could not probe the EEPROM at 0x%x\n",
38 CONFIG_SYS_I2C_EEPROM_ADDR);
42 /* read the eeprom using i2c */
43 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,
44 sizeof(struct am43xx_board_id))) {
45 printf("Could not read the EEPROM\n");
49 if (header->magic != 0xEE3355AA) {
51 * read the eeprom using i2c again,
52 * but use only a 1 byte address
54 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
55 sizeof(struct am43xx_board_id))) {
56 printf("Could not read the EEPROM at 0x%x\n",
57 CONFIG_SYS_I2C_EEPROM_ADDR);
61 if (header->magic != 0xEE3355AA) {
62 printf("Incorrect magic number (0x%x) in EEPROM\n",
68 strncpy(am43xx_board_name, (char *)header->name, sizeof(header->name));
69 am43xx_board_name[sizeof(header->name)] = 0;
74 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
78 const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = {
80 {-1, -1, -1, -1, -1, -1, -1}, /* OPP 50 */
81 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
82 {-1, -1, -1, -1, -1, -1, -1}, /* OPP 100 */
83 {-1, -1, -1, -1, -1, -1, -1}, /* OPP 120 */
84 {-1, -1, -1, -1, -1, -1, -1}, /* OPP TB */
85 {-1, -1, -1, -1, -1, -1, -1} /* OPP NT */
88 {300, 23, 1, -1, -1, -1, -1}, /* OPP 50 */
89 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
90 {600, 23, 1, -1, -1, -1, -1}, /* OPP 100 */
91 {720, 23, 1, -1, -1, -1, -1}, /* OPP 120 */
92 {800, 23, 1, -1, -1, -1, -1}, /* OPP TB */
93 {1000, 23, 1, -1, -1, -1, -1} /* OPP NT */
96 {300, 24, 1, -1, -1, -1, -1}, /* OPP 50 */
97 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
98 {600, 24, 1, -1, -1, -1, -1}, /* OPP 100 */
99 {720, 24, 1, -1, -1, -1, -1}, /* OPP 120 */
100 {800, 24, 1, -1, -1, -1, -1}, /* OPP TB */
101 {1000, 24, 1, -1, -1, -1, -1} /* OPP NT */
104 {300, 25, 1, -1, -1, -1, -1}, /* OPP 50 */
105 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
106 {600, 25, 1, -1, -1, -1, -1}, /* OPP 100 */
107 {720, 25, 1, -1, -1, -1, -1}, /* OPP 120 */
108 {800, 25, 1, -1, -1, -1, -1}, /* OPP TB */
109 {1000, 25, 1, -1, -1, -1, -1} /* OPP NT */
113 const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = {
114 {-1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
115 {1000, 23, -1, -1, 10, 8, 4}, /* 24 MHz */
116 {1000, 24, -1, -1, 10, 8, 4}, /* 25 MHz */
117 {1000, 25, -1, -1, 10, 8, 4} /* 26 MHz */
120 const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = {
121 {-1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
122 {960, 23, 5, -1, -1, -1, -1}, /* 24 MHz */
123 {960, 24, 5, -1, -1, -1, -1}, /* 25 MHz */
124 {960, 25, 5, -1, -1, -1, -1} /* 26 MHz */
127 const struct dpll_params epos_evm_dpll_ddr = {
128 266, 24, 1, -1, 1, -1, -1};
130 const struct dpll_params gp_evm_dpll_ddr = {
131 400, 23, 1, -1, 1, -1, -1};
133 const struct ctrl_ioregs ioregs_lpddr2 = {
134 .cm0ioctl = LPDDR2_ADDRCTRL_IOCTRL_VALUE,
135 .cm1ioctl = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE,
136 .cm2ioctl = LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE,
137 .dt0ioctl = LPDDR2_DATA0_IOCTRL_VALUE,
138 .dt1ioctl = LPDDR2_DATA0_IOCTRL_VALUE,
139 .dt2ioctrl = LPDDR2_DATA0_IOCTRL_VALUE,
140 .dt3ioctrl = LPDDR2_DATA0_IOCTRL_VALUE,
141 .emif_sdram_config_ext = 0x1,
144 const struct emif_regs emif_regs_lpddr2 = {
145 .sdram_config = 0x808012BA,
146 .ref_ctrl = 0x0000040D,
147 .sdram_tim1 = 0xEA86B411,
148 .sdram_tim2 = 0x103A094A,
149 .sdram_tim3 = 0x0F6BA37F,
150 .read_idle_ctrl = 0x00050000,
151 .zq_config = 0x50074BE4,
152 .temp_alert_config = 0x0,
153 .emif_rd_wr_lvl_rmp_win = 0x0,
154 .emif_rd_wr_lvl_rmp_ctl = 0x0,
155 .emif_rd_wr_lvl_ctl = 0x0,
156 .emif_ddr_phy_ctlr_1 = 0x0E084006,
157 .emif_rd_wr_exec_thresh = 0x00000405,
158 .emif_ddr_ext_phy_ctrl_1 = 0x04010040,
159 .emif_ddr_ext_phy_ctrl_2 = 0x00500050,
160 .emif_ddr_ext_phy_ctrl_3 = 0x00500050,
161 .emif_ddr_ext_phy_ctrl_4 = 0x00500050,
162 .emif_ddr_ext_phy_ctrl_5 = 0x00500050
165 const u32 ext_phy_ctrl_const_base_lpddr2[] = {
188 const struct ctrl_ioregs ioregs_ddr3 = {
189 .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE,
190 .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
191 .cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
192 .dt0ioctl = DDR3_DATA0_IOCTRL_VALUE,
193 .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE,
194 .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE,
195 .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE,
196 .emif_sdram_config_ext = 0x0143,
199 const struct emif_regs ddr3_emif_regs_400Mhz = {
200 .sdram_config = 0x638413B2,
201 .ref_ctrl = 0x00000C30,
202 .sdram_tim1 = 0xEAAAD4DB,
203 .sdram_tim2 = 0x266B7FDA,
204 .sdram_tim3 = 0x107F8678,
205 .read_idle_ctrl = 0x00050000,
206 .zq_config = 0x50074BE4,
207 .temp_alert_config = 0x0,
208 .emif_ddr_phy_ctlr_1 = 0x0E004008,
209 .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
210 .emif_ddr_ext_phy_ctrl_2 = 0x00400040,
211 .emif_ddr_ext_phy_ctrl_3 = 0x00400040,
212 .emif_ddr_ext_phy_ctrl_4 = 0x00400040,
213 .emif_ddr_ext_phy_ctrl_5 = 0x00400040,
214 .emif_rd_wr_lvl_rmp_win = 0x0,
215 .emif_rd_wr_lvl_rmp_ctl = 0x0,
216 .emif_rd_wr_lvl_ctl = 0x0,
217 .emif_rd_wr_exec_thresh = 0x00000405
220 static const struct emif_regs ddr3_sk_emif_regs_400Mhz = {
221 .sdram_config = 0x638413b2,
222 .sdram_config2 = 0x00000000,
223 .ref_ctrl = 0x00000c30,
224 .sdram_tim1 = 0xeaaad4db,
225 .sdram_tim2 = 0x266b7fda,
226 .sdram_tim3 = 0x107f8678,
227 .read_idle_ctrl = 0x00050000,
228 .zq_config = 0x50074be4,
229 .temp_alert_config = 0x0,
230 .emif_ddr_phy_ctlr_1 = 0x0e084008,
231 .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
232 .emif_ddr_ext_phy_ctrl_2 = 0x89,
233 .emif_ddr_ext_phy_ctrl_3 = 0x90,
234 .emif_ddr_ext_phy_ctrl_4 = 0x8e,
235 .emif_ddr_ext_phy_ctrl_5 = 0x8d,
236 .emif_rd_wr_lvl_rmp_win = 0x0,
237 .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
238 .emif_rd_wr_lvl_ctl = 0x00000000,
239 .emif_rd_wr_exec_thresh = 0x00000000,
242 const u32 ext_phy_ctrl_const_base_ddr3[] = {
265 static const u32 ext_phy_ctrl_const_base_ddr3_sk[] = {
266 /* first 5 are taken care by emif_regs */
307 void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
309 if (board_is_eposevm()) {
310 *regs = ext_phy_ctrl_const_base_lpddr2;
311 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2);
312 } else if (board_is_gpevm()) {
313 *regs = ext_phy_ctrl_const_base_ddr3;
314 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3);
315 } else if (board_is_sk()) {
316 *regs = ext_phy_ctrl_const_base_ddr3_sk;
317 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_sk);
323 const struct dpll_params *get_dpll_ddr_params(void)
325 if (board_is_eposevm())
326 return &epos_evm_dpll_ddr;
327 else if (board_is_gpevm() || board_is_sk())
328 return &gp_evm_dpll_ddr;
330 printf(" Board '%s' not supported\n", am43xx_board_name);
335 * get_sys_clk_index : returns the index of the sys_clk read from
336 * ctrl status register. This value is either
337 * read from efuse or sysboot pins.
339 static u32 get_sys_clk_index(void)
341 struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
342 u32 ind = readl(&ctrl->statusreg), src;
344 src = (ind & CTRL_CRYSTAL_FREQ_SRC_MASK) >> CTRL_CRYSTAL_FREQ_SRC_SHIFT;
345 if (src == CTRL_CRYSTAL_FREQ_SRC_EFUSE) /* Value read from EFUSE */
346 return ((ind & CTRL_CRYSTAL_FREQ_SELECTION_MASK) >>
347 CTRL_CRYSTAL_FREQ_SELECTION_SHIFT);
348 else /* Value read from SYS BOOT pins */
349 return ((ind & CTRL_SYSBOOT_15_14_MASK) >>
350 CTRL_SYSBOOT_15_14_SHIFT);
355 * Returns the index for safest OPP of the device to boot.
356 * max_off: Index of the MAX OPP in DEV ATTRIBUTE register.
357 * min_off: Index of the MIN OPP in DEV ATTRIBUTE register.
358 * This data is read from dev_attribute register which is e-fused.
359 * A'1' in bit indicates OPP disabled and not available, a '0' indicates
360 * OPP available. Lowest OPP starts with min_off. So returning the
361 * bit with rightmost '0'.
363 static int get_opp_offset(int max_off, int min_off)
365 struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
368 /* Bits 0:11 are defined to be the MPU_MAX_FREQ */
369 opp = readl(&ctrl->dev_attr) & ~0xFFFFF000;
371 for (i = max_off; i >= min_off; i--) {
372 offset = opp & (1 << i);
380 const struct dpll_params *get_dpll_mpu_params(void)
382 int opp = get_opp_offset(DEV_ATTR_MAX_OFFSET, DEV_ATTR_MIN_OFFSET);
383 u32 ind = get_sys_clk_index();
385 return &dpll_mpu[ind][opp];
388 const struct dpll_params *get_dpll_core_params(void)
390 int ind = get_sys_clk_index();
392 return &dpll_core[ind];
395 const struct dpll_params *get_dpll_per_params(void)
397 int ind = get_sys_clk_index();
399 return &dpll_per[ind];
402 void scale_vcores(void)
404 const struct dpll_params *mpu_params;
406 struct am43xx_board_id header;
408 enable_i2c0_pin_mux();
409 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
410 if (read_eeprom(&header) < 0)
411 puts("Could not get board ID.\n");
413 /* Get the frequency */
414 mpu_params = get_dpll_mpu_params();
416 if (i2c_probe(TPS65218_CHIP_PM))
419 if (mpu_params->m == 1000) {
420 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV;
421 } else if (mpu_params->m == 600) {
422 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV;
424 puts("Unknown MPU clock, not scaling\n");
428 /* Set DCDC1 (CORE) voltage to 1.1V */
429 if (tps65218_voltage_update(TPS65218_DCDC1,
430 TPS65218_DCDC_VOLT_SEL_1100MV)) {
431 puts("tps65218_voltage_update failure\n");
435 /* Set DCDC2 (MPU) voltage */
436 if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) {
437 puts("tps65218_voltage_update failure\n");
442 void set_uart_mux_conf(void)
444 enable_uart0_pin_mux();
447 void set_mux_conf_regs(void)
449 enable_board_pin_mux();
452 static void enable_vtt_regulator(void)
457 writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL);
459 /* enable output for GPIO5_7 */
460 writel(GPIO_SETDATAOUT(7),
461 AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT);
462 temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
463 temp = temp & ~(GPIO_OE_ENABLE(7));
464 writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
467 void sdram_init(void)
470 * EPOS EVM has 1GB LPDDR2 connected to EMIF.
471 * GP EMV has 1GB DDR3 connected to EMIF
472 * along with VTT regulator.
474 if (board_is_eposevm()) {
475 config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0);
476 } else if (board_is_gpevm()) {
477 enable_vtt_regulator();
478 config_ddr(0, &ioregs_ddr3, NULL, NULL,
479 &ddr3_emif_regs_400Mhz, 0);
480 } else if (board_is_sk()) {
481 config_ddr(400, &ioregs_ddr3, NULL, NULL,
482 &ddr3_sk_emif_regs_400Mhz, 0);
489 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
494 #ifdef CONFIG_BOARD_LATE_INIT
495 int board_late_init(void)
497 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
498 char safe_string[HDR_NAME_LEN + 1];
499 struct am43xx_board_id header;
501 if (read_eeprom(&header) < 0)
502 puts("Could not get board ID.\n");
504 /* Now set variables based on the header. */
505 strncpy(safe_string, (char *)header.name, sizeof(header.name));
506 safe_string[sizeof(header.name)] = 0;
507 setenv("board_name", safe_string);
509 strncpy(safe_string, (char *)header.version, sizeof(header.version));
510 safe_string[sizeof(header.version)] = 0;
511 setenv("board_rev", safe_string);
517 #ifdef CONFIG_DRIVER_TI_CPSW
519 static void cpsw_control(int enabled)
521 /* Additional controls can be added here */
525 static struct cpsw_slave_data cpsw_slaves[] = {
527 .slave_reg_ofs = 0x208,
528 .sliver_reg_ofs = 0xd80,
532 .slave_reg_ofs = 0x308,
533 .sliver_reg_ofs = 0xdc0,
538 static struct cpsw_platform_data cpsw_data = {
539 .mdio_base = CPSW_MDIO_BASE,
540 .cpsw_base = CPSW_BASE,
543 .cpdma_reg_ofs = 0x800,
545 .slave_data = cpsw_slaves,
546 .ale_reg_ofs = 0xd00,
548 .host_port_reg_ofs = 0x108,
549 .hw_stats_reg_ofs = 0x900,
550 .bd_ram_ofs = 0x2000,
551 .mac_control = (1 << 5),
552 .control = cpsw_control,
554 .version = CPSW_CTRL_VERSION_2,
557 int board_eth_init(bd_t *bis)
561 uint32_t mac_hi, mac_lo;
563 /* try reading mac address from efuse */
564 mac_lo = readl(&cdev->macid0l);
565 mac_hi = readl(&cdev->macid0h);
566 mac_addr[0] = mac_hi & 0xFF;
567 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
568 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
569 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
570 mac_addr[4] = mac_lo & 0xFF;
571 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
573 if (!getenv("ethaddr")) {
574 puts("<ethaddr> not set. Validating first E-fuse MAC\n");
575 if (is_valid_ether_addr(mac_addr))
576 eth_setenv_enetaddr("ethaddr", mac_addr);
579 mac_lo = readl(&cdev->macid1l);
580 mac_hi = readl(&cdev->macid1h);
581 mac_addr[0] = mac_hi & 0xFF;
582 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
583 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
584 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
585 mac_addr[4] = mac_lo & 0xFF;
586 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
588 if (!getenv("eth1addr")) {
589 if (is_valid_ether_addr(mac_addr))
590 eth_setenv_enetaddr("eth1addr", mac_addr);
593 if (board_is_eposevm()) {
594 writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
595 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
596 cpsw_slaves[0].phy_addr = 16;
597 } else if (board_is_sk()) {
598 writel(RGMII_MODE_ENABLE, &cdev->miisel);
599 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
600 cpsw_slaves[0].phy_addr = 4;
601 cpsw_slaves[1].phy_addr = 5;
603 writel(RGMII_MODE_ENABLE, &cdev->miisel);
604 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
605 cpsw_slaves[0].phy_addr = 0;
608 rv = cpsw_register(&cpsw_data);
610 printf("Error %d registering CPSW switch\n", rv);