4 * Board functions for TI AM43XX based boards
6 * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
8 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/errno.h>
15 #include <asm/arch/clock.h>
16 #include <asm/arch/sys_proto.h>
17 #include <asm/arch/mux.h>
18 #include <asm/arch/ddr_defs.h>
19 #include <asm/arch/gpio.h>
22 #include <power/tps65218.h>
26 DECLARE_GLOBAL_DATA_PTR;
28 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
31 * Read header information from EEPROM into global structure.
33 static int read_eeprom(struct am43xx_board_id *header)
35 /* Check if baseboard eeprom is available */
36 if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
37 printf("Could not probe the EEPROM at 0x%x\n",
38 CONFIG_SYS_I2C_EEPROM_ADDR);
42 /* read the eeprom using i2c */
43 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,
44 sizeof(struct am43xx_board_id))) {
45 printf("Could not read the EEPROM\n");
49 if (header->magic != 0xEE3355AA) {
51 * read the eeprom using i2c again,
52 * but use only a 1 byte address
54 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
55 sizeof(struct am43xx_board_id))) {
56 printf("Could not read the EEPROM at 0x%x\n",
57 CONFIG_SYS_I2C_EEPROM_ADDR);
61 if (header->magic != 0xEE3355AA) {
62 printf("Incorrect magic number (0x%x) in EEPROM\n",
68 strncpy(am43xx_board_name, (char *)header->name, sizeof(header->name));
69 am43xx_board_name[sizeof(header->name)] = 0;
71 strncpy(am43xx_board_rev, (char *)header->version, sizeof(header->version));
72 am43xx_board_rev[sizeof(header->version)] = 0;
77 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
81 const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = {
83 {-1, -1, -1, -1, -1, -1, -1}, /* OPP 50 */
84 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
85 {-1, -1, -1, -1, -1, -1, -1}, /* OPP 100 */
86 {-1, -1, -1, -1, -1, -1, -1}, /* OPP 120 */
87 {-1, -1, -1, -1, -1, -1, -1}, /* OPP TB */
88 {-1, -1, -1, -1, -1, -1, -1} /* OPP NT */
91 {300, 23, 1, -1, -1, -1, -1}, /* OPP 50 */
92 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
93 {600, 23, 1, -1, -1, -1, -1}, /* OPP 100 */
94 {720, 23, 1, -1, -1, -1, -1}, /* OPP 120 */
95 {800, 23, 1, -1, -1, -1, -1}, /* OPP TB */
96 {1000, 23, 1, -1, -1, -1, -1} /* OPP NT */
99 {300, 24, 1, -1, -1, -1, -1}, /* OPP 50 */
100 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
101 {600, 24, 1, -1, -1, -1, -1}, /* OPP 100 */
102 {720, 24, 1, -1, -1, -1, -1}, /* OPP 120 */
103 {800, 24, 1, -1, -1, -1, -1}, /* OPP TB */
104 {1000, 24, 1, -1, -1, -1, -1} /* OPP NT */
107 {300, 25, 1, -1, -1, -1, -1}, /* OPP 50 */
108 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
109 {600, 25, 1, -1, -1, -1, -1}, /* OPP 100 */
110 {720, 25, 1, -1, -1, -1, -1}, /* OPP 120 */
111 {800, 25, 1, -1, -1, -1, -1}, /* OPP TB */
112 {1000, 25, 1, -1, -1, -1, -1} /* OPP NT */
116 const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = {
117 {-1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
118 {1000, 23, -1, -1, 10, 8, 4}, /* 24 MHz */
119 {1000, 24, -1, -1, 10, 8, 4}, /* 25 MHz */
120 {1000, 25, -1, -1, 10, 8, 4} /* 26 MHz */
123 const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = {
124 {-1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
125 {960, 23, 5, -1, -1, -1, -1}, /* 24 MHz */
126 {960, 24, 5, -1, -1, -1, -1}, /* 25 MHz */
127 {960, 25, 5, -1, -1, -1, -1} /* 26 MHz */
130 const struct dpll_params epos_evm_dpll_ddr = {
131 266, 24, 1, -1, 1, -1, -1};
133 const struct dpll_params gp_evm_dpll_ddr = {
134 400, 23, 1, -1, 1, -1, -1};
136 const struct ctrl_ioregs ioregs_lpddr2 = {
137 .cm0ioctl = LPDDR2_ADDRCTRL_IOCTRL_VALUE,
138 .cm1ioctl = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE,
139 .cm2ioctl = LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE,
140 .dt0ioctl = LPDDR2_DATA0_IOCTRL_VALUE,
141 .dt1ioctl = LPDDR2_DATA0_IOCTRL_VALUE,
142 .dt2ioctrl = LPDDR2_DATA0_IOCTRL_VALUE,
143 .dt3ioctrl = LPDDR2_DATA0_IOCTRL_VALUE,
144 .emif_sdram_config_ext = 0x1,
147 const struct emif_regs emif_regs_lpddr2 = {
148 .sdram_config = 0x808012BA,
149 .ref_ctrl = 0x0000040D,
150 .sdram_tim1 = 0xEA86B411,
151 .sdram_tim2 = 0x103A094A,
152 .sdram_tim3 = 0x0F6BA37F,
153 .read_idle_ctrl = 0x00050000,
154 .zq_config = 0x50074BE4,
155 .temp_alert_config = 0x0,
156 .emif_rd_wr_lvl_rmp_win = 0x0,
157 .emif_rd_wr_lvl_rmp_ctl = 0x0,
158 .emif_rd_wr_lvl_ctl = 0x0,
159 .emif_ddr_phy_ctlr_1 = 0x0E084006,
160 .emif_rd_wr_exec_thresh = 0x00000405,
161 .emif_ddr_ext_phy_ctrl_1 = 0x04010040,
162 .emif_ddr_ext_phy_ctrl_2 = 0x00500050,
163 .emif_ddr_ext_phy_ctrl_3 = 0x00500050,
164 .emif_ddr_ext_phy_ctrl_4 = 0x00500050,
165 .emif_ddr_ext_phy_ctrl_5 = 0x00500050
168 const u32 ext_phy_ctrl_const_base_lpddr2[] = {
191 const struct ctrl_ioregs ioregs_ddr3 = {
192 .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE,
193 .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
194 .cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
195 .dt0ioctl = DDR3_DATA0_IOCTRL_VALUE,
196 .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE,
197 .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE,
198 .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE,
199 .emif_sdram_config_ext = 0x0143,
202 const struct emif_regs ddr3_emif_regs_400Mhz = {
203 .sdram_config = 0x638413B2,
204 .ref_ctrl = 0x00000C30,
205 .sdram_tim1 = 0xEAAAD4DB,
206 .sdram_tim2 = 0x266B7FDA,
207 .sdram_tim3 = 0x107F8678,
208 .read_idle_ctrl = 0x00050000,
209 .zq_config = 0x50074BE4,
210 .temp_alert_config = 0x0,
211 .emif_ddr_phy_ctlr_1 = 0x0E004008,
212 .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
213 .emif_ddr_ext_phy_ctrl_2 = 0x00400040,
214 .emif_ddr_ext_phy_ctrl_3 = 0x00400040,
215 .emif_ddr_ext_phy_ctrl_4 = 0x00400040,
216 .emif_ddr_ext_phy_ctrl_5 = 0x00400040,
217 .emif_rd_wr_lvl_rmp_win = 0x0,
218 .emif_rd_wr_lvl_rmp_ctl = 0x0,
219 .emif_rd_wr_lvl_ctl = 0x0,
220 .emif_rd_wr_exec_thresh = 0x00000405
223 /* EMIF DDR3 Configurations are different for beta AM43X GP EVMs */
224 const struct emif_regs ddr3_emif_regs_400Mhz_beta = {
225 .sdram_config = 0x638413B2,
226 .ref_ctrl = 0x00000C30,
227 .sdram_tim1 = 0xEAAAD4DB,
228 .sdram_tim2 = 0x266B7FDA,
229 .sdram_tim3 = 0x107F8678,
230 .read_idle_ctrl = 0x00050000,
231 .zq_config = 0x50074BE4,
232 .temp_alert_config = 0x0,
233 .emif_ddr_phy_ctlr_1 = 0x0E004008,
234 .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
235 .emif_ddr_ext_phy_ctrl_2 = 0x00000065,
236 .emif_ddr_ext_phy_ctrl_3 = 0x00000091,
237 .emif_ddr_ext_phy_ctrl_4 = 0x000000B5,
238 .emif_ddr_ext_phy_ctrl_5 = 0x000000E5,
239 .emif_rd_wr_exec_thresh = 0x00000405
242 /* EMIF DDR3 Configurations are different for production AM43X GP EVMs */
243 const struct emif_regs ddr3_emif_regs_400Mhz_production = {
244 .sdram_config = 0x638413B2,
245 .ref_ctrl = 0x00000C30,
246 .sdram_tim1 = 0xEAAAD4DB,
247 .sdram_tim2 = 0x266B7FDA,
248 .sdram_tim3 = 0x107F8678,
249 .read_idle_ctrl = 0x00050000,
250 .zq_config = 0x50074BE4,
251 .temp_alert_config = 0x0,
252 .emif_ddr_phy_ctlr_1 = 0x0E004008,
253 .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
254 .emif_ddr_ext_phy_ctrl_2 = 0x00000066,
255 .emif_ddr_ext_phy_ctrl_3 = 0x00000091,
256 .emif_ddr_ext_phy_ctrl_4 = 0x000000B9,
257 .emif_ddr_ext_phy_ctrl_5 = 0x000000E6,
258 .emif_rd_wr_exec_thresh = 0x00000405
261 static const struct emif_regs ddr3_sk_emif_regs_400Mhz = {
262 .sdram_config = 0x638413b2,
263 .sdram_config2 = 0x00000000,
264 .ref_ctrl = 0x00000c30,
265 .sdram_tim1 = 0xeaaad4db,
266 .sdram_tim2 = 0x266b7fda,
267 .sdram_tim3 = 0x107f8678,
268 .read_idle_ctrl = 0x00050000,
269 .zq_config = 0x50074be4,
270 .temp_alert_config = 0x0,
271 .emif_ddr_phy_ctlr_1 = 0x0e084008,
272 .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
273 .emif_ddr_ext_phy_ctrl_2 = 0x89,
274 .emif_ddr_ext_phy_ctrl_3 = 0x90,
275 .emif_ddr_ext_phy_ctrl_4 = 0x8e,
276 .emif_ddr_ext_phy_ctrl_5 = 0x8d,
277 .emif_rd_wr_lvl_rmp_win = 0x0,
278 .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
279 .emif_rd_wr_lvl_ctl = 0x00000000,
280 .emif_rd_wr_exec_thresh = 0x00000000,
283 const u32 ext_phy_ctrl_const_base_ddr3[] = {
306 const u32 ext_phy_ctrl_const_base_ddr3_beta[] = {
329 const u32 ext_phy_ctrl_const_base_ddr3_production[] = {
352 static const u32 ext_phy_ctrl_const_base_ddr3_sk[] = {
353 /* first 5 are taken care by emif_regs */
394 void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
396 if (board_is_eposevm()) {
397 *regs = ext_phy_ctrl_const_base_lpddr2;
398 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2);
399 } else if (board_is_evm_14_or_later()) {
400 *regs = ext_phy_ctrl_const_base_ddr3_production;
401 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_production);
402 } else if (board_is_evm_12_or_later()) {
403 *regs = ext_phy_ctrl_const_base_ddr3_beta;
404 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_beta);
405 } else if (board_is_gpevm()) {
406 *regs = ext_phy_ctrl_const_base_ddr3;
407 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3);
408 } else if (board_is_sk()) {
409 *regs = ext_phy_ctrl_const_base_ddr3_sk;
410 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_sk);
416 const struct dpll_params *get_dpll_ddr_params(void)
418 if (board_is_eposevm())
419 return &epos_evm_dpll_ddr;
420 else if (board_is_gpevm() || board_is_sk())
421 return &gp_evm_dpll_ddr;
423 printf(" Board '%s' not supported\n", am43xx_board_name);
428 * get_sys_clk_index : returns the index of the sys_clk read from
429 * ctrl status register. This value is either
430 * read from efuse or sysboot pins.
432 static u32 get_sys_clk_index(void)
434 struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
435 u32 ind = readl(&ctrl->statusreg), src;
437 src = (ind & CTRL_CRYSTAL_FREQ_SRC_MASK) >> CTRL_CRYSTAL_FREQ_SRC_SHIFT;
438 if (src == CTRL_CRYSTAL_FREQ_SRC_EFUSE) /* Value read from EFUSE */
439 return ((ind & CTRL_CRYSTAL_FREQ_SELECTION_MASK) >>
440 CTRL_CRYSTAL_FREQ_SELECTION_SHIFT);
441 else /* Value read from SYS BOOT pins */
442 return ((ind & CTRL_SYSBOOT_15_14_MASK) >>
443 CTRL_SYSBOOT_15_14_SHIFT);
448 * Returns the index for safest OPP of the device to boot.
449 * max_off: Index of the MAX OPP in DEV ATTRIBUTE register.
450 * min_off: Index of the MIN OPP in DEV ATTRIBUTE register.
451 * This data is read from dev_attribute register which is e-fused.
452 * A'1' in bit indicates OPP disabled and not available, a '0' indicates
453 * OPP available. Lowest OPP starts with min_off. So returning the
454 * bit with rightmost '0'.
456 static int get_opp_offset(int max_off, int min_off)
458 struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
461 /* Bits 0:11 are defined to be the MPU_MAX_FREQ */
462 opp = readl(&ctrl->dev_attr) & ~0xFFFFF000;
464 for (i = max_off; i >= min_off; i--) {
465 offset = opp & (1 << i);
473 const struct dpll_params *get_dpll_mpu_params(void)
475 int opp = get_opp_offset(DEV_ATTR_MAX_OFFSET, DEV_ATTR_MIN_OFFSET);
476 u32 ind = get_sys_clk_index();
478 return &dpll_mpu[ind][opp];
481 const struct dpll_params *get_dpll_core_params(void)
483 int ind = get_sys_clk_index();
485 return &dpll_core[ind];
488 const struct dpll_params *get_dpll_per_params(void)
490 int ind = get_sys_clk_index();
492 return &dpll_per[ind];
495 void scale_vcores(void)
497 const struct dpll_params *mpu_params;
499 struct am43xx_board_id header;
501 enable_i2c0_pin_mux();
502 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
503 if (read_eeprom(&header) < 0)
504 puts("Could not get board ID.\n");
506 /* Get the frequency */
507 mpu_params = get_dpll_mpu_params();
509 if (i2c_probe(TPS65218_CHIP_PM))
512 if (mpu_params->m == 1000) {
513 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV;
514 } else if (mpu_params->m == 600) {
515 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV;
517 puts("Unknown MPU clock, not scaling\n");
521 /* Set DCDC1 (CORE) voltage to 1.1V */
522 if (tps65218_voltage_update(TPS65218_DCDC1,
523 TPS65218_DCDC_VOLT_SEL_1100MV)) {
524 puts("tps65218_voltage_update failure\n");
528 /* Set DCDC2 (MPU) voltage */
529 if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) {
530 puts("tps65218_voltage_update failure\n");
535 void set_uart_mux_conf(void)
537 enable_uart0_pin_mux();
540 void set_mux_conf_regs(void)
542 enable_board_pin_mux();
545 static void enable_vtt_regulator(void)
550 writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL);
552 /* enable output for GPIO5_7 */
553 writel(GPIO_SETDATAOUT(7),
554 AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT);
555 temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
556 temp = temp & ~(GPIO_OE_ENABLE(7));
557 writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
560 void sdram_init(void)
563 * EPOS EVM has 1GB LPDDR2 connected to EMIF.
564 * GP EMV has 1GB DDR3 connected to EMIF
565 * along with VTT regulator.
567 if (board_is_eposevm()) {
568 config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0);
569 } else if (board_is_evm_14_or_later()) {
570 enable_vtt_regulator();
571 config_ddr(0, &ioregs_ddr3, NULL, NULL,
572 &ddr3_emif_regs_400Mhz_production, 0);
573 } else if (board_is_evm_12_or_later()) {
574 enable_vtt_regulator();
575 config_ddr(0, &ioregs_ddr3, NULL, NULL,
576 &ddr3_emif_regs_400Mhz_beta, 0);
577 } else if (board_is_gpevm()) {
578 enable_vtt_regulator();
579 config_ddr(0, &ioregs_ddr3, NULL, NULL,
580 &ddr3_emif_regs_400Mhz, 0);
581 } else if (board_is_sk()) {
582 config_ddr(400, &ioregs_ddr3, NULL, NULL,
583 &ddr3_sk_emif_regs_400Mhz, 0);
590 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
595 #ifdef CONFIG_BOARD_LATE_INIT
596 int board_late_init(void)
598 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
599 char safe_string[HDR_NAME_LEN + 1];
600 struct am43xx_board_id header;
602 if (read_eeprom(&header) < 0)
603 puts("Could not get board ID.\n");
605 /* Now set variables based on the header. */
606 strncpy(safe_string, (char *)header.name, sizeof(header.name));
607 safe_string[sizeof(header.name)] = 0;
608 setenv("board_name", safe_string);
610 strncpy(safe_string, (char *)header.version, sizeof(header.version));
611 safe_string[sizeof(header.version)] = 0;
612 setenv("board_rev", safe_string);
618 #ifdef CONFIG_DRIVER_TI_CPSW
620 static void cpsw_control(int enabled)
622 /* Additional controls can be added here */
626 static struct cpsw_slave_data cpsw_slaves[] = {
628 .slave_reg_ofs = 0x208,
629 .sliver_reg_ofs = 0xd80,
633 .slave_reg_ofs = 0x308,
634 .sliver_reg_ofs = 0xdc0,
639 static struct cpsw_platform_data cpsw_data = {
640 .mdio_base = CPSW_MDIO_BASE,
641 .cpsw_base = CPSW_BASE,
644 .cpdma_reg_ofs = 0x800,
646 .slave_data = cpsw_slaves,
647 .ale_reg_ofs = 0xd00,
649 .host_port_reg_ofs = 0x108,
650 .hw_stats_reg_ofs = 0x900,
651 .bd_ram_ofs = 0x2000,
652 .mac_control = (1 << 5),
653 .control = cpsw_control,
655 .version = CPSW_CTRL_VERSION_2,
658 int board_eth_init(bd_t *bis)
662 uint32_t mac_hi, mac_lo;
664 /* try reading mac address from efuse */
665 mac_lo = readl(&cdev->macid0l);
666 mac_hi = readl(&cdev->macid0h);
667 mac_addr[0] = mac_hi & 0xFF;
668 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
669 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
670 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
671 mac_addr[4] = mac_lo & 0xFF;
672 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
674 if (!getenv("ethaddr")) {
675 puts("<ethaddr> not set. Validating first E-fuse MAC\n");
676 if (is_valid_ether_addr(mac_addr))
677 eth_setenv_enetaddr("ethaddr", mac_addr);
680 mac_lo = readl(&cdev->macid1l);
681 mac_hi = readl(&cdev->macid1h);
682 mac_addr[0] = mac_hi & 0xFF;
683 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
684 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
685 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
686 mac_addr[4] = mac_lo & 0xFF;
687 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
689 if (!getenv("eth1addr")) {
690 if (is_valid_ether_addr(mac_addr))
691 eth_setenv_enetaddr("eth1addr", mac_addr);
694 if (board_is_eposevm()) {
695 writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
696 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
697 cpsw_slaves[0].phy_addr = 16;
698 } else if (board_is_sk()) {
699 writel(RGMII_MODE_ENABLE, &cdev->miisel);
700 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
701 cpsw_slaves[0].phy_addr = 4;
702 cpsw_slaves[1].phy_addr = 5;
704 writel(RGMII_MODE_ENABLE, &cdev->miisel);
705 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
706 cpsw_slaves[0].phy_addr = 0;
709 rv = cpsw_register(&cpsw_data);
711 printf("Error %d registering CPSW switch\n", rv);