1 // SPDX-License-Identifier: GPL-2.0+
5 * Board functions for TI AM43XX based boards
7 * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
12 #include <dm/uclass.h>
16 #include <linux/errno.h>
19 #include <asm/omap_sec_common.h>
20 #include <asm/arch/clock.h>
21 #include <asm/arch/sys_proto.h>
22 #include <asm/arch/mux.h>
23 #include <asm/arch/ddr_defs.h>
24 #include <asm/arch/gpio.h>
26 #include <asm/omap_common.h>
27 #include "../common/board_detect.h"
29 #include <power/pmic.h>
30 #include <power/tps65218.h>
31 #include <power/tps62362.h>
32 #include <linux/usb/gadget.h>
33 #include <dwc3-uboot.h>
34 #include <dwc3-omap-uboot.h>
35 #include <ti-usb-phy-uboot.h>
37 DECLARE_GLOBAL_DATA_PTR;
39 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
42 * Read header information from EEPROM into global structure.
44 #ifdef CONFIG_TI_I2C_BOARD_DETECT
45 void do_board_detect(void)
47 /* Ensure I2C is initialized for EEPROM access*/
49 if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
50 CONFIG_EEPROM_CHIP_ADDRESS))
51 printf("ti_i2c_eeprom_init failed\n");
55 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
57 const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = {
59 {125, 3, 2, -1, -1, -1, -1}, /* OPP 50 */
60 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
61 {125, 3, 1, -1, -1, -1, -1}, /* OPP 100 */
62 {150, 3, 1, -1, -1, -1, -1}, /* OPP 120 */
63 {125, 2, 1, -1, -1, -1, -1}, /* OPP TB */
64 {625, 11, 1, -1, -1, -1, -1} /* OPP NT */
67 {300, 23, 1, -1, -1, -1, -1}, /* OPP 50 */
68 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
69 {600, 23, 1, -1, -1, -1, -1}, /* OPP 100 */
70 {720, 23, 1, -1, -1, -1, -1}, /* OPP 120 */
71 {800, 23, 1, -1, -1, -1, -1}, /* OPP TB */
72 {1000, 23, 1, -1, -1, -1, -1} /* OPP NT */
75 {300, 24, 1, -1, -1, -1, -1}, /* OPP 50 */
76 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
77 {600, 24, 1, -1, -1, -1, -1}, /* OPP 100 */
78 {720, 24, 1, -1, -1, -1, -1}, /* OPP 120 */
79 {800, 24, 1, -1, -1, -1, -1}, /* OPP TB */
80 {1000, 24, 1, -1, -1, -1, -1} /* OPP NT */
83 {300, 25, 1, -1, -1, -1, -1}, /* OPP 50 */
84 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
85 {600, 25, 1, -1, -1, -1, -1}, /* OPP 100 */
86 {720, 25, 1, -1, -1, -1, -1}, /* OPP 120 */
87 {800, 25, 1, -1, -1, -1, -1}, /* OPP TB */
88 {1000, 25, 1, -1, -1, -1, -1} /* OPP NT */
92 const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = {
93 {625, 11, -1, -1, 10, 8, 4}, /* 19.2 MHz */
94 {1000, 23, -1, -1, 10, 8, 4}, /* 24 MHz */
95 {1000, 24, -1, -1, 10, 8, 4}, /* 25 MHz */
96 {1000, 25, -1, -1, 10, 8, 4} /* 26 MHz */
99 const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = {
100 {400, 7, 5, -1, -1, -1, -1}, /* 19.2 MHz */
101 {400, 9, 5, -1, -1, -1, -1}, /* 24 MHz */
102 {384, 9, 5, -1, -1, -1, -1}, /* 25 MHz */
103 {480, 12, 5, -1, -1, -1, -1} /* 26 MHz */
106 const struct dpll_params epos_evm_dpll_ddr[NUM_CRYSTAL_FREQ] = {
107 {665, 47, 1, -1, 4, -1, -1}, /*19.2*/
108 {133, 11, 1, -1, 4, -1, -1}, /* 24 MHz */
109 {266, 24, 1, -1, 4, -1, -1}, /* 25 MHz */
110 {133, 12, 1, -1, 4, -1, -1} /* 26 MHz */
113 const struct dpll_params gp_evm_dpll_ddr = {
114 50, 2, 1, -1, 2, -1, -1};
116 static const struct dpll_params idk_dpll_ddr = {
117 400, 23, 1, -1, 2, -1, -1
120 static const u32 ext_phy_ctrl_const_base_lpddr2[] = {
143 const struct ctrl_ioregs ioregs_lpddr2 = {
144 .cm0ioctl = LPDDR2_ADDRCTRL_IOCTRL_VALUE,
145 .cm1ioctl = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE,
146 .cm2ioctl = LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE,
147 .dt0ioctl = LPDDR2_DATA0_IOCTRL_VALUE,
148 .dt1ioctl = LPDDR2_DATA0_IOCTRL_VALUE,
149 .dt2ioctrl = LPDDR2_DATA0_IOCTRL_VALUE,
150 .dt3ioctrl = LPDDR2_DATA0_IOCTRL_VALUE,
151 .emif_sdram_config_ext = 0x1,
154 const struct emif_regs emif_regs_lpddr2 = {
155 .sdram_config = 0x808012BA,
156 .ref_ctrl = 0x0000040D,
157 .sdram_tim1 = 0xEA86B411,
158 .sdram_tim2 = 0x103A094A,
159 .sdram_tim3 = 0x0F6BA37F,
160 .read_idle_ctrl = 0x00050000,
161 .zq_config = 0x50074BE4,
162 .temp_alert_config = 0x0,
163 .emif_rd_wr_lvl_rmp_win = 0x0,
164 .emif_rd_wr_lvl_rmp_ctl = 0x0,
165 .emif_rd_wr_lvl_ctl = 0x0,
166 .emif_ddr_phy_ctlr_1 = 0x0E284006,
167 .emif_rd_wr_exec_thresh = 0x80000405,
168 .emif_ddr_ext_phy_ctrl_1 = 0x04010040,
169 .emif_ddr_ext_phy_ctrl_2 = 0x00500050,
170 .emif_ddr_ext_phy_ctrl_3 = 0x00500050,
171 .emif_ddr_ext_phy_ctrl_4 = 0x00500050,
172 .emif_ddr_ext_phy_ctrl_5 = 0x00500050,
173 .emif_prio_class_serv_map = 0x80000001,
174 .emif_connect_id_serv_1_map = 0x80000094,
175 .emif_connect_id_serv_2_map = 0x00000000,
176 .emif_cos_config = 0x000FFFFF
179 const struct ctrl_ioregs ioregs_ddr3 = {
180 .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE,
181 .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
182 .cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
183 .dt0ioctl = DDR3_DATA0_IOCTRL_VALUE,
184 .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE,
185 .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE,
186 .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE,
187 .emif_sdram_config_ext = 0xc163,
190 const struct emif_regs ddr3_emif_regs_400Mhz = {
191 .sdram_config = 0x638413B2,
192 .ref_ctrl = 0x00000C30,
193 .sdram_tim1 = 0xEAAAD4DB,
194 .sdram_tim2 = 0x266B7FDA,
195 .sdram_tim3 = 0x107F8678,
196 .read_idle_ctrl = 0x00050000,
197 .zq_config = 0x50074BE4,
198 .temp_alert_config = 0x0,
199 .emif_ddr_phy_ctlr_1 = 0x0E004008,
200 .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
201 .emif_ddr_ext_phy_ctrl_2 = 0x00400040,
202 .emif_ddr_ext_phy_ctrl_3 = 0x00400040,
203 .emif_ddr_ext_phy_ctrl_4 = 0x00400040,
204 .emif_ddr_ext_phy_ctrl_5 = 0x00400040,
205 .emif_rd_wr_lvl_rmp_win = 0x0,
206 .emif_rd_wr_lvl_rmp_ctl = 0x0,
207 .emif_rd_wr_lvl_ctl = 0x0,
208 .emif_rd_wr_exec_thresh = 0x80000405,
209 .emif_prio_class_serv_map = 0x80000001,
210 .emif_connect_id_serv_1_map = 0x80000094,
211 .emif_connect_id_serv_2_map = 0x00000000,
212 .emif_cos_config = 0x000FFFFF
215 /* EMIF DDR3 Configurations are different for beta AM43X GP EVMs */
216 const struct emif_regs ddr3_emif_regs_400Mhz_beta = {
217 .sdram_config = 0x638413B2,
218 .ref_ctrl = 0x00000C30,
219 .sdram_tim1 = 0xEAAAD4DB,
220 .sdram_tim2 = 0x266B7FDA,
221 .sdram_tim3 = 0x107F8678,
222 .read_idle_ctrl = 0x00050000,
223 .zq_config = 0x50074BE4,
224 .temp_alert_config = 0x0,
225 .emif_ddr_phy_ctlr_1 = 0x0E004008,
226 .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
227 .emif_ddr_ext_phy_ctrl_2 = 0x00000065,
228 .emif_ddr_ext_phy_ctrl_3 = 0x00000091,
229 .emif_ddr_ext_phy_ctrl_4 = 0x000000B5,
230 .emif_ddr_ext_phy_ctrl_5 = 0x000000E5,
231 .emif_rd_wr_exec_thresh = 0x80000405,
232 .emif_prio_class_serv_map = 0x80000001,
233 .emif_connect_id_serv_1_map = 0x80000094,
234 .emif_connect_id_serv_2_map = 0x00000000,
235 .emif_cos_config = 0x000FFFFF
238 /* EMIF DDR3 Configurations are different for production AM43X GP EVMs */
239 const struct emif_regs ddr3_emif_regs_400Mhz_production = {
240 .sdram_config = 0x638413B2,
241 .ref_ctrl = 0x00000C30,
242 .sdram_tim1 = 0xEAAAD4DB,
243 .sdram_tim2 = 0x266B7FDA,
244 .sdram_tim3 = 0x107F8678,
245 .read_idle_ctrl = 0x00050000,
246 .zq_config = 0x50074BE4,
247 .temp_alert_config = 0x0,
248 .emif_ddr_phy_ctlr_1 = 0x00048008,
249 .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
250 .emif_ddr_ext_phy_ctrl_2 = 0x00000066,
251 .emif_ddr_ext_phy_ctrl_3 = 0x00000091,
252 .emif_ddr_ext_phy_ctrl_4 = 0x000000B9,
253 .emif_ddr_ext_phy_ctrl_5 = 0x000000E6,
254 .emif_rd_wr_exec_thresh = 0x80000405,
255 .emif_prio_class_serv_map = 0x80000001,
256 .emif_connect_id_serv_1_map = 0x80000094,
257 .emif_connect_id_serv_2_map = 0x00000000,
258 .emif_cos_config = 0x000FFFFF
261 static const struct emif_regs ddr3_sk_emif_regs_400Mhz = {
262 .sdram_config = 0x638413b2,
263 .sdram_config2 = 0x00000000,
264 .ref_ctrl = 0x00000c30,
265 .sdram_tim1 = 0xeaaad4db,
266 .sdram_tim2 = 0x266b7fda,
267 .sdram_tim3 = 0x107f8678,
268 .read_idle_ctrl = 0x00050000,
269 .zq_config = 0x50074be4,
270 .temp_alert_config = 0x0,
271 .emif_ddr_phy_ctlr_1 = 0x0e084008,
272 .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
273 .emif_ddr_ext_phy_ctrl_2 = 0x89,
274 .emif_ddr_ext_phy_ctrl_3 = 0x90,
275 .emif_ddr_ext_phy_ctrl_4 = 0x8e,
276 .emif_ddr_ext_phy_ctrl_5 = 0x8d,
277 .emif_rd_wr_lvl_rmp_win = 0x0,
278 .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
279 .emif_rd_wr_lvl_ctl = 0x00000000,
280 .emif_rd_wr_exec_thresh = 0x80000000,
281 .emif_prio_class_serv_map = 0x80000001,
282 .emif_connect_id_serv_1_map = 0x80000094,
283 .emif_connect_id_serv_2_map = 0x00000000,
284 .emif_cos_config = 0x000FFFFF
287 static const struct emif_regs ddr3_idk_emif_regs_400Mhz = {
288 .sdram_config = 0x61a11b32,
289 .sdram_config2 = 0x00000000,
290 .ref_ctrl = 0x00000c30,
291 .sdram_tim1 = 0xeaaad4db,
292 .sdram_tim2 = 0x266b7fda,
293 .sdram_tim3 = 0x107f8678,
294 .read_idle_ctrl = 0x00050000,
295 .zq_config = 0x50074be4,
296 .temp_alert_config = 0x00000000,
297 .emif_ddr_phy_ctlr_1 = 0x00008009,
298 .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
299 .emif_ddr_ext_phy_ctrl_2 = 0x00000040,
300 .emif_ddr_ext_phy_ctrl_3 = 0x0000003e,
301 .emif_ddr_ext_phy_ctrl_4 = 0x00000051,
302 .emif_ddr_ext_phy_ctrl_5 = 0x00000051,
303 .emif_rd_wr_lvl_rmp_win = 0x00000000,
304 .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
305 .emif_rd_wr_lvl_ctl = 0x00000000,
306 .emif_rd_wr_exec_thresh = 0x00000405,
307 .emif_prio_class_serv_map = 0x00000000,
308 .emif_connect_id_serv_1_map = 0x00000000,
309 .emif_connect_id_serv_2_map = 0x00000000,
310 .emif_cos_config = 0x00ffffff
313 void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
315 if (board_is_eposevm()) {
316 *regs = ext_phy_ctrl_const_base_lpddr2;
317 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2);
323 const struct dpll_params *get_dpll_ddr_params(void)
325 int ind = get_sys_clk_index();
327 if (board_is_eposevm())
328 return &epos_evm_dpll_ddr[ind];
329 else if (board_is_evm() || board_is_sk())
330 return &gp_evm_dpll_ddr;
331 else if (board_is_idk())
332 return &idk_dpll_ddr;
334 printf(" Board '%s' not supported\n", board_ti_get_name());
341 * Returns the index for safest OPP of the device to boot.
342 * max_off: Index of the MAX OPP in DEV ATTRIBUTE register.
343 * min_off: Index of the MIN OPP in DEV ATTRIBUTE register.
344 * This data is read from dev_attribute register which is e-fused.
345 * A'1' in bit indicates OPP disabled and not available, a '0' indicates
346 * OPP available. Lowest OPP starts with min_off. So returning the
347 * bit with rightmost '0'.
349 static int get_opp_offset(int max_off, int min_off)
351 struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
354 /* Bits 0:11 are defined to be the MPU_MAX_FREQ */
355 opp = readl(&ctrl->dev_attr) & ~0xFFFFF000;
357 for (i = max_off; i >= min_off; i--) {
358 offset = opp & (1 << i);
366 const struct dpll_params *get_dpll_mpu_params(void)
368 int opp = get_opp_offset(DEV_ATTR_MAX_OFFSET, DEV_ATTR_MIN_OFFSET);
369 u32 ind = get_sys_clk_index();
371 return &dpll_mpu[ind][opp];
374 const struct dpll_params *get_dpll_core_params(void)
376 int ind = get_sys_clk_index();
378 return &dpll_core[ind];
381 const struct dpll_params *get_dpll_per_params(void)
383 int ind = get_sys_clk_index();
385 return &dpll_per[ind];
388 void scale_vcores_generic(u32 m)
390 int mpu_vdd, ddr_volt;
392 #ifndef CONFIG_DM_I2C
393 if (i2c_probe(TPS65218_CHIP_PM))
396 if (power_tps65218_init(0))
402 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV;
405 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1260MV;
408 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1200MV;
411 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV;
414 mpu_vdd = TPS65218_DCDC_VOLT_SEL_0950MV;
417 puts("Unknown MPU clock, not scaling\n");
421 /* Set DCDC1 (CORE) voltage to 1.1V */
422 if (tps65218_voltage_update(TPS65218_DCDC1,
423 TPS65218_DCDC_VOLT_SEL_1100MV)) {
424 printf("%s failure\n", __func__);
428 /* Set DCDC2 (MPU) voltage */
429 if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) {
430 printf("%s failure\n", __func__);
434 if (board_is_eposevm())
435 ddr_volt = TPS65218_DCDC3_VOLT_SEL_1200MV;
437 ddr_volt = TPS65218_DCDC3_VOLT_SEL_1350MV;
439 /* Set DCDC3 (DDR) voltage */
440 if (tps65218_voltage_update(TPS65218_DCDC3, ddr_volt)) {
441 printf("%s failure\n", __func__);
446 void scale_vcores_idk(u32 m)
450 #ifndef CONFIG_DM_I2C
451 if (i2c_probe(TPS62362_I2C_ADDR))
454 if (power_tps62362_init(0))
460 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV;
463 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1260MV;
466 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1200MV;
469 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1100MV;
472 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV;
475 puts("Unknown MPU clock, not scaling\n");
478 /* Set VDD_MPU voltage */
479 if (tps62362_voltage_update(TPS62362_SET3, mpu_vdd)) {
480 printf("%s failure\n", __func__);
484 void gpi2c_init(void)
486 /* When needed to be invoked prior to BSS initialization */
487 static bool first_time = true;
490 enable_i2c0_pin_mux();
491 #ifndef CONFIG_DM_I2C
492 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
493 CONFIG_SYS_OMAP24_I2C_SLAVE);
499 void scale_vcores(void)
501 const struct dpll_params *mpu_params;
503 /* Ensure I2C is initialized for PMIC configuration */
506 /* Get the frequency */
507 mpu_params = get_dpll_mpu_params();
510 scale_vcores_idk(mpu_params->m);
512 scale_vcores_generic(mpu_params->m);
515 void set_uart_mux_conf(void)
517 enable_uart0_pin_mux();
520 void set_mux_conf_regs(void)
522 enable_board_pin_mux();
525 static void enable_vtt_regulator(void)
530 writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL);
532 /* enable output for GPIO5_7 */
533 writel(GPIO_SETDATAOUT(7),
534 AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT);
535 temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
536 temp = temp & ~(GPIO_OE_ENABLE(7));
537 writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
549 * In the rtc_only+DRR in self-refresh boot path we have the board type info
550 * in the rtc scratch pad register hence we bypass the costly i2c reads to
551 * eeprom and directly programthe board name string
553 void rtc_only_update_board_type(u32 btype)
555 const char *name = "";
556 const char *rev = "1.0";
562 case RTC_BOARD_EVM14:
566 case RTC_BOARD_EVM12:
570 case RTC_BOARD_GPEVM:
577 ti_i2c_eeprom_am_set(name, rev);
580 u32 rtc_only_get_board_type(void)
582 if (board_is_eposevm())
583 return RTC_BOARD_EPOS;
584 else if (board_is_evm_14_or_later())
585 return RTC_BOARD_EVM14;
586 else if (board_is_evm_12_or_later())
587 return RTC_BOARD_EVM12;
588 else if (board_is_gpevm())
589 return RTC_BOARD_GPEVM;
590 else if (board_is_sk())
596 void sdram_init(void)
599 * EPOS EVM has 1GB LPDDR2 connected to EMIF.
600 * GP EMV has 1GB DDR3 connected to EMIF
601 * along with VTT regulator.
603 if (board_is_eposevm()) {
604 config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0);
605 } else if (board_is_evm_14_or_later()) {
606 enable_vtt_regulator();
607 config_ddr(0, &ioregs_ddr3, NULL, NULL,
608 &ddr3_emif_regs_400Mhz_production, 0);
609 } else if (board_is_evm_12_or_later()) {
610 enable_vtt_regulator();
611 config_ddr(0, &ioregs_ddr3, NULL, NULL,
612 &ddr3_emif_regs_400Mhz_beta, 0);
613 } else if (board_is_evm()) {
614 enable_vtt_regulator();
615 config_ddr(0, &ioregs_ddr3, NULL, NULL,
616 &ddr3_emif_regs_400Mhz, 0);
617 } else if (board_is_sk()) {
618 config_ddr(400, &ioregs_ddr3, NULL, NULL,
619 &ddr3_sk_emif_regs_400Mhz, 0);
620 } else if (board_is_idk()) {
621 config_ddr(400, &ioregs_ddr3, NULL, NULL,
622 &ddr3_idk_emif_regs_400Mhz, 0);
627 /* setup board specific PMIC */
628 int power_init_board(void)
631 #ifndef CONFIG_DM_I2C
632 struct pmic *p = NULL;
634 if (board_is_idk()) {
635 rc = power_tps62362_init(0);
638 #ifndef CONFIG_DM_I2C
639 p = pmic_get("TPS62362");
640 if (!p || pmic_probe(p))
643 puts("PMIC: TPS62362\n");
645 rc = power_tps65218_init(0);
648 #ifndef CONFIG_DM_I2C
649 p = pmic_get("TPS65218_PMIC");
650 if (!p || pmic_probe(p))
653 puts("PMIC: TPS65218\n");
661 struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER;
662 u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional,
663 modena_init0_bw_integer, modena_init0_watermark_0;
665 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
669 * Call this to initialize *ctrl again
673 /* Clear all important bits for DSS errata that may need to be tweaked*/
674 mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK &
675 MREQPRIO_0_SAB_INIT0_MASK;
677 mreqprio_1 = readl(&cdev->mreqprio_1) & MREQPRIO_1_DSS_MASK;
679 modena_init0_bw_fractional = readl(&bwlimiter->modena_init0_bw_fractional) &
680 BW_LIMITER_BW_FRAC_MASK;
682 modena_init0_bw_integer = readl(&bwlimiter->modena_init0_bw_integer) &
683 BW_LIMITER_BW_INT_MASK;
685 modena_init0_watermark_0 = readl(&bwlimiter->modena_init0_watermark_0) &
686 BW_LIMITER_BW_WATERMARK_MASK;
688 /* Setting MReq Priority of the DSS*/
692 * Set L3 Fast Configuration Register
693 * Limiting bandwith for ARM core to 700 MBPS
695 modena_init0_bw_fractional |= 0x10;
696 modena_init0_bw_integer |= 0x3;
698 writel(mreqprio_0, &cdev->mreqprio_0);
699 writel(mreqprio_1, &cdev->mreqprio_1);
701 writel(modena_init0_bw_fractional, &bwlimiter->modena_init0_bw_fractional);
702 writel(modena_init0_bw_integer, &bwlimiter->modena_init0_bw_integer);
703 writel(modena_init0_watermark_0, &bwlimiter->modena_init0_watermark_0);
708 #ifdef CONFIG_BOARD_LATE_INIT
709 #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
710 static int device_okay(const char *path)
714 node = fdt_path_offset(gd->fdt_blob, path);
718 return fdtdec_get_is_enabled(gd->fdt_blob, node);
722 int board_late_init(void)
725 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
726 set_board_info_env(NULL);
729 * Default FIT boot on HS devices. Non FIT images are not allowed
732 if (get_device_type() == HS_DEVICE)
733 env_set("boot_fit", "1");
736 #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
737 if (device_okay("/ocp/omap_dwc3@48380000"))
738 enable_usb_clocks(0);
739 if (device_okay("/ocp/omap_dwc3@483c0000"))
740 enable_usb_clocks(1);
743 /* Just probe the potentially supported cdce913 device */
744 uclass_get_device(UCLASS_CLK, 0, &dev);
750 #if !CONFIG_IS_ENABLED(DM_USB_GADGET)
751 #ifdef CONFIG_USB_DWC3
752 static struct dwc3_device usb_otg_ss1 = {
753 .maximum_speed = USB_SPEED_HIGH,
754 .base = USB_OTG_SS1_BASE,
755 .tx_fifo_resize = false,
759 static struct dwc3_omap_device usb_otg_ss1_glue = {
760 .base = (void *)USB_OTG_SS1_GLUE_BASE,
761 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
765 static struct ti_usb_phy_device usb_phy1_device = {
766 .usb2_phy_power = (void *)USB2_PHY1_POWER,
770 static struct dwc3_device usb_otg_ss2 = {
771 .maximum_speed = USB_SPEED_HIGH,
772 .base = USB_OTG_SS2_BASE,
773 .tx_fifo_resize = false,
777 static struct dwc3_omap_device usb_otg_ss2_glue = {
778 .base = (void *)USB_OTG_SS2_GLUE_BASE,
779 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
783 static struct ti_usb_phy_device usb_phy2_device = {
784 .usb2_phy_power = (void *)USB2_PHY2_POWER,
788 int usb_gadget_handle_interrupts(int index)
792 status = dwc3_omap_uboot_interrupt_status(index);
794 dwc3_uboot_handle_interrupt(index);
798 #endif /* CONFIG_USB_DWC3 */
800 #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
801 int board_usb_init(int index, enum usb_init_type init)
803 enable_usb_clocks(index);
804 #ifdef CONFIG_USB_DWC3
807 if (init == USB_INIT_DEVICE) {
808 usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
809 usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
810 dwc3_omap_uboot_init(&usb_otg_ss1_glue);
811 ti_usb_phy_uboot_init(&usb_phy1_device);
812 dwc3_uboot_init(&usb_otg_ss1);
816 if (init == USB_INIT_DEVICE) {
817 usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
818 usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
819 ti_usb_phy_uboot_init(&usb_phy2_device);
820 dwc3_omap_uboot_init(&usb_otg_ss2_glue);
821 dwc3_uboot_init(&usb_otg_ss2);
825 printf("Invalid Controller Index\n");
832 int board_usb_cleanup(int index, enum usb_init_type init)
834 #ifdef CONFIG_USB_DWC3
838 if (init == USB_INIT_DEVICE) {
839 ti_usb_phy_uboot_exit(index);
840 dwc3_uboot_exit(index);
841 dwc3_omap_uboot_exit(index);
845 printf("Invalid Controller Index\n");
848 disable_usb_clocks(index);
852 #endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
853 #endif /* !CONFIG_IS_ENABLED(DM_USB_GADGET) */
855 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
856 int ft_board_setup(void *blob, bd_t *bd)
858 ft_cpu_setup(blob, bd);
864 #if defined(CONFIG_SPL_LOAD_FIT) || defined(CONFIG_DTB_RESELECT)
865 int board_fit_config_name_match(const char *name)
867 bool eeprom_read = board_ti_was_eeprom_read();
869 if (!strcmp(name, "am4372-generic") && !eeprom_read)
871 else if (board_is_evm() && !strcmp(name, "am437x-gp-evm"))
873 else if (board_is_sk() && !strcmp(name, "am437x-sk-evm"))
875 else if (board_is_eposevm() && !strcmp(name, "am43x-epos-evm"))
877 else if (board_is_idk() && !strcmp(name, "am437x-idk-evm"))
884 #ifdef CONFIG_DTB_RESELECT
885 int embedded_dtb_select(void)
894 #ifdef CONFIG_TI_SECURE_DEVICE
895 void board_fit_image_post_process(void **p_image, size_t *p_size)
897 secure_boot_verify_image(p_image, p_size);
900 void board_tee_image_process(ulong tee_image, size_t tee_size)
902 secure_tee_install((u32)tee_image);
905 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);