board/ti/am43xx/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * board.c
   4  *
   5  * Board functions for TI AM43XX based boards
   6  *
   7  * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
   8  */
   9
  10 #include <common.h>
  11 #include <eeprom.h>
  12 #include <dm/uclass.h>
  13 #include <env.h>
  14 #include <fdt_support.h>
  15 #include <i2c.h>
  16 #include <init.h>
  17 #include <net.h>
  18 #include <linux/errno.h>
  19 #include <spl.h>
  20 #include <usb.h>
  21 #include <asm/omap_sec_common.h>
  22 #include <asm/arch/clock.h>
  23 #include <asm/arch/sys_proto.h>
  24 #include <asm/arch/mux.h>
  25 #include <asm/arch/ddr_defs.h>
  26 #include <asm/arch/gpio.h>
  27 #include <asm/emif.h>
  28 #include <asm/omap_common.h>
  29 #include "../common/board_detect.h"
  30 #include "board.h"
  31 #include <power/pmic.h>
  32 #include <power/tps65218.h>
  33 #include <power/tps62362.h>
  34 #include <linux/usb/gadget.h>
  35 #include <dwc3-uboot.h>
  36 #include <dwc3-omap-uboot.h>
  37 #include <ti-usb-phy-uboot.h>
  38
  39 DECLARE_GLOBAL_DATA_PTR;
  40
  41 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  42
  43 /*
  44  * Read header information from EEPROM into global structure.
  45  */
  46 #ifdef CONFIG_TI_I2C_BOARD_DETECT
  47 void do_board_detect(void)
  48 {
  49         /* Ensure I2C is initialized for EEPROM access*/
  50         gpi2c_init();
  51         if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
  52                                  CONFIG_EEPROM_CHIP_ADDRESS))
  53                 printf("ti_i2c_eeprom_init failed\n");
  54 }
  55 #endif
  56
  57 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  58
  59 const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = {
  60         {       /* 19.2 MHz */
  61                 {125, 3, 2, -1, -1, -1, -1},    /* OPP 50 */
  62                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP RESERVED */
  63                 {125, 3, 1, -1, -1, -1, -1},    /* OPP 100 */
  64                 {150, 3, 1, -1, -1, -1, -1},    /* OPP 120 */
  65                 {125, 2, 1, -1, -1, -1, -1},    /* OPP TB */
  66                 {625, 11, 1, -1, -1, -1, -1}    /* OPP NT */
  67         },
  68         {       /* 24 MHz */
  69                 {300, 23, 1, -1, -1, -1, -1},   /* OPP 50 */
  70                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP RESERVED */
  71                 {600, 23, 1, -1, -1, -1, -1},   /* OPP 100 */
  72                 {720, 23, 1, -1, -1, -1, -1},   /* OPP 120 */
  73                 {800, 23, 1, -1, -1, -1, -1},   /* OPP TB */
  74                 {1000, 23, 1, -1, -1, -1, -1}   /* OPP NT */
  75         },
  76         {       /* 25 MHz */
  77                 {300, 24, 1, -1, -1, -1, -1},   /* OPP 50 */
  78                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP RESERVED */
  79                 {600, 24, 1, -1, -1, -1, -1},   /* OPP 100 */
  80                 {720, 24, 1, -1, -1, -1, -1},   /* OPP 120 */
  81                 {800, 24, 1, -1, -1, -1, -1},   /* OPP TB */
  82                 {1000, 24, 1, -1, -1, -1, -1}   /* OPP NT */
  83         },
  84         {       /* 26 MHz */
  85                 {300, 25, 1, -1, -1, -1, -1},   /* OPP 50 */
  86                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP RESERVED */
  87                 {600, 25, 1, -1, -1, -1, -1},   /* OPP 100 */
  88                 {720, 25, 1, -1, -1, -1, -1},   /* OPP 120 */
  89                 {800, 25, 1, -1, -1, -1, -1},   /* OPP TB */
  90                 {1000, 25, 1, -1, -1, -1, -1}   /* OPP NT */
  91         },
  92 };
  93
  94 const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = {
  95                 {625, 11, -1, -1, 10, 8, 4},    /* 19.2 MHz */
  96                 {1000, 23, -1, -1, 10, 8, 4},   /* 24 MHz */
  97                 {1000, 24, -1, -1, 10, 8, 4},   /* 25 MHz */
  98                 {1000, 25, -1, -1, 10, 8, 4}    /* 26 MHz */
  99 };
 100
 101 const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = {
 102                 {400, 7, 5, -1, -1, -1, -1},    /* 19.2 MHz */
 103                 {400, 9, 5, -1, -1, -1, -1},    /* 24 MHz */
 104                 {384, 9, 5, -1, -1, -1, -1},    /* 25 MHz */
 105                 {480, 12, 5, -1, -1, -1, -1}    /* 26 MHz */
 106 };
 107
 108 const struct dpll_params epos_evm_dpll_ddr[NUM_CRYSTAL_FREQ] = {
 109                 {665, 47, 1, -1, 4, -1, -1}, /*19.2*/
 110                 {133, 11, 1, -1, 4, -1, -1}, /* 24 MHz */
 111                 {266, 24, 1, -1, 4, -1, -1}, /* 25 MHz */
 112                 {133, 12, 1, -1, 4, -1, -1}  /* 26 MHz */
 113 };
 114
 115 const struct dpll_params gp_evm_dpll_ddr = {
 116                 50, 2, 1, -1, 2, -1, -1};
 117
 118 static const struct dpll_params idk_dpll_ddr = {
 119         400, 23, 1, -1, 2, -1, -1
 120 };
 121
 122 static const u32 ext_phy_ctrl_const_base_lpddr2[] = {
 123         0x00500050,
 124         0x00350035,
 125         0x00350035,
 126         0x00350035,
 127         0x00350035,
 128         0x00350035,
 129         0x00000000,
 130         0x00000000,
 131         0x00000000,
 132         0x00000000,
 133         0x00000000,
 134         0x00000000,
 135         0x00000000,
 136         0x00000000,
 137         0x00000000,
 138         0x00000000,
 139         0x00000000,
 140         0x00000000,
 141         0x40001000,
 142         0x08102040
 143 };
 144
 145 const struct ctrl_ioregs ioregs_lpddr2 = {
 146         .cm0ioctl               = LPDDR2_ADDRCTRL_IOCTRL_VALUE,
 147         .cm1ioctl               = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE,
 148         .cm2ioctl               = LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE,
 149         .dt0ioctl               = LPDDR2_DATA0_IOCTRL_VALUE,
 150         .dt1ioctl               = LPDDR2_DATA0_IOCTRL_VALUE,
 151         .dt2ioctrl              = LPDDR2_DATA0_IOCTRL_VALUE,
 152         .dt3ioctrl              = LPDDR2_DATA0_IOCTRL_VALUE,
 153         .emif_sdram_config_ext  = 0x1,
 154 };
 155
 156 const struct emif_regs emif_regs_lpddr2 = {
 157         .sdram_config                   = 0x808012BA,
 158         .ref_ctrl                       = 0x0000040D,
 159         .sdram_tim1                     = 0xEA86B411,
 160         .sdram_tim2                     = 0x103A094A,
 161         .sdram_tim3                     = 0x0F6BA37F,
 162         .read_idle_ctrl                 = 0x00050000,
 163         .zq_config                      = 0x50074BE4,
 164         .temp_alert_config              = 0x0,
 165         .emif_rd_wr_lvl_rmp_win         = 0x0,
 166         .emif_rd_wr_lvl_rmp_ctl         = 0x0,
 167         .emif_rd_wr_lvl_ctl             = 0x0,
 168         .emif_ddr_phy_ctlr_1            = 0x0E284006,
 169         .emif_rd_wr_exec_thresh         = 0x80000405,
 170         .emif_ddr_ext_phy_ctrl_1        = 0x04010040,
 171         .emif_ddr_ext_phy_ctrl_2        = 0x00500050,
 172         .emif_ddr_ext_phy_ctrl_3        = 0x00500050,
 173         .emif_ddr_ext_phy_ctrl_4        = 0x00500050,
 174         .emif_ddr_ext_phy_ctrl_5        = 0x00500050,
 175         .emif_prio_class_serv_map       = 0x80000001,
 176         .emif_connect_id_serv_1_map     = 0x80000094,
 177         .emif_connect_id_serv_2_map     = 0x00000000,
 178         .emif_cos_config                        = 0x000FFFFF
 179 };
 180
 181 const struct ctrl_ioregs ioregs_ddr3 = {
 182         .cm0ioctl               = DDR3_ADDRCTRL_IOCTRL_VALUE,
 183         .cm1ioctl               = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
 184         .cm2ioctl               = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
 185         .dt0ioctl               = DDR3_DATA0_IOCTRL_VALUE,
 186         .dt1ioctl               = DDR3_DATA0_IOCTRL_VALUE,
 187         .dt2ioctrl              = DDR3_DATA0_IOCTRL_VALUE,
 188         .dt3ioctrl              = DDR3_DATA0_IOCTRL_VALUE,
 189         .emif_sdram_config_ext  = 0xc163,
 190 };
 191
 192 const struct emif_regs ddr3_emif_regs_400Mhz = {
 193         .sdram_config                   = 0x638413B2,
 194         .ref_ctrl                       = 0x00000C30,
 195         .sdram_tim1                     = 0xEAAAD4DB,
 196         .sdram_tim2                     = 0x266B7FDA,
 197         .sdram_tim3                     = 0x107F8678,
 198         .read_idle_ctrl                 = 0x00050000,
 199         .zq_config                      = 0x50074BE4,
 200         .temp_alert_config              = 0x0,
 201         .emif_ddr_phy_ctlr_1            = 0x0E004008,
 202         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
 203         .emif_ddr_ext_phy_ctrl_2        = 0x00400040,
 204         .emif_ddr_ext_phy_ctrl_3        = 0x00400040,
 205         .emif_ddr_ext_phy_ctrl_4        = 0x00400040,
 206         .emif_ddr_ext_phy_ctrl_5        = 0x00400040,
 207         .emif_rd_wr_lvl_rmp_win         = 0x0,
 208         .emif_rd_wr_lvl_rmp_ctl         = 0x0,
 209         .emif_rd_wr_lvl_ctl             = 0x0,
 210         .emif_rd_wr_exec_thresh         = 0x80000405,
 211         .emif_prio_class_serv_map       = 0x80000001,
 212         .emif_connect_id_serv_1_map     = 0x80000094,
 213         .emif_connect_id_serv_2_map     = 0x00000000,
 214         .emif_cos_config                = 0x000FFFFF
 215 };
 216
 217 /* EMIF DDR3 Configurations are different for beta AM43X GP EVMs */
 218 const struct emif_regs ddr3_emif_regs_400Mhz_beta = {
 219         .sdram_config                   = 0x638413B2,
 220         .ref_ctrl                       = 0x00000C30,
 221         .sdram_tim1                     = 0xEAAAD4DB,
 222         .sdram_tim2                     = 0x266B7FDA,
 223         .sdram_tim3                     = 0x107F8678,
 224         .read_idle_ctrl                 = 0x00050000,
 225         .zq_config                      = 0x50074BE4,
 226         .temp_alert_config              = 0x0,
 227         .emif_ddr_phy_ctlr_1            = 0x0E004008,
 228         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
 229         .emif_ddr_ext_phy_ctrl_2        = 0x00000065,
 230         .emif_ddr_ext_phy_ctrl_3        = 0x00000091,
 231         .emif_ddr_ext_phy_ctrl_4        = 0x000000B5,
 232         .emif_ddr_ext_phy_ctrl_5        = 0x000000E5,
 233         .emif_rd_wr_exec_thresh         = 0x80000405,
 234         .emif_prio_class_serv_map       = 0x80000001,
 235         .emif_connect_id_serv_1_map     = 0x80000094,
 236         .emif_connect_id_serv_2_map     = 0x00000000,
 237         .emif_cos_config                = 0x000FFFFF
 238 };
 239
 240 /* EMIF DDR3 Configurations are different for production AM43X GP EVMs */
 241 const struct emif_regs ddr3_emif_regs_400Mhz_production = {
 242         .sdram_config                   = 0x638413B2,
 243         .ref_ctrl                       = 0x00000C30,
 244         .sdram_tim1                     = 0xEAAAD4DB,
 245         .sdram_tim2                     = 0x266B7FDA,
 246         .sdram_tim3                     = 0x107F8678,
 247         .read_idle_ctrl                 = 0x00050000,
 248         .zq_config                      = 0x50074BE4,
 249         .temp_alert_config              = 0x0,
 250         .emif_ddr_phy_ctlr_1            = 0x00048008,
 251         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
 252         .emif_ddr_ext_phy_ctrl_2        = 0x00000066,
 253         .emif_ddr_ext_phy_ctrl_3        = 0x00000091,
 254         .emif_ddr_ext_phy_ctrl_4        = 0x000000B9,
 255         .emif_ddr_ext_phy_ctrl_5        = 0x000000E6,
 256         .emif_rd_wr_exec_thresh         = 0x80000405,
 257         .emif_prio_class_serv_map       = 0x80000001,
 258         .emif_connect_id_serv_1_map     = 0x80000094,
 259         .emif_connect_id_serv_2_map     = 0x00000000,
 260         .emif_cos_config                = 0x000FFFFF
 261 };
 262
 263 static const struct emif_regs ddr3_sk_emif_regs_400Mhz = {
 264         .sdram_config                   = 0x638413b2,
 265         .sdram_config2                  = 0x00000000,
 266         .ref_ctrl                       = 0x00000c30,
 267         .sdram_tim1                     = 0xeaaad4db,
 268         .sdram_tim2                     = 0x266b7fda,
 269         .sdram_tim3                     = 0x107f8678,
 270         .read_idle_ctrl                 = 0x00050000,
 271         .zq_config                      = 0x50074be4,
 272         .temp_alert_config              = 0x0,
 273         .emif_ddr_phy_ctlr_1            = 0x0e084008,
 274         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
 275         .emif_ddr_ext_phy_ctrl_2        = 0x89,
 276         .emif_ddr_ext_phy_ctrl_3        = 0x90,
 277         .emif_ddr_ext_phy_ctrl_4        = 0x8e,
 278         .emif_ddr_ext_phy_ctrl_5        = 0x8d,
 279         .emif_rd_wr_lvl_rmp_win         = 0x0,
 280         .emif_rd_wr_lvl_rmp_ctl         = 0x00000000,
 281         .emif_rd_wr_lvl_ctl             = 0x00000000,
 282         .emif_rd_wr_exec_thresh         = 0x80000000,
 283         .emif_prio_class_serv_map       = 0x80000001,
 284         .emif_connect_id_serv_1_map     = 0x80000094,
 285         .emif_connect_id_serv_2_map     = 0x00000000,
 286         .emif_cos_config                = 0x000FFFFF
 287 };
 288
 289 static const struct emif_regs ddr3_idk_emif_regs_400Mhz = {
 290         .sdram_config                   = 0x61a11b32,
 291         .sdram_config2                  = 0x00000000,
 292         .ref_ctrl                       = 0x00000c30,
 293         .sdram_tim1                     = 0xeaaad4db,
 294         .sdram_tim2                     = 0x266b7fda,
 295         .sdram_tim3                     = 0x107f8678,
 296         .read_idle_ctrl                 = 0x00050000,
 297         .zq_config                      = 0x50074be4,
 298         .temp_alert_config              = 0x00000000,
 299         .emif_ddr_phy_ctlr_1            = 0x00008009,
 300         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
 301         .emif_ddr_ext_phy_ctrl_2        = 0x00000040,
 302         .emif_ddr_ext_phy_ctrl_3        = 0x0000003e,
 303         .emif_ddr_ext_phy_ctrl_4        = 0x00000051,
 304         .emif_ddr_ext_phy_ctrl_5        = 0x00000051,
 305         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 306         .emif_rd_wr_lvl_rmp_ctl         = 0x00000000,
 307         .emif_rd_wr_lvl_ctl             = 0x00000000,
 308         .emif_rd_wr_exec_thresh         = 0x00000405,
 309         .emif_prio_class_serv_map       = 0x00000000,
 310         .emif_connect_id_serv_1_map     = 0x00000000,
 311         .emif_connect_id_serv_2_map     = 0x00000000,
 312         .emif_cos_config                = 0x00ffffff
 313 };
 314
 315 void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
 316 {
 317         if (board_is_eposevm()) {
 318                 *regs = ext_phy_ctrl_const_base_lpddr2;
 319                 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2);
 320         }
 321
 322         return;
 323 }
 324
 325 const struct dpll_params *get_dpll_ddr_params(void)
 326 {
 327         int ind = get_sys_clk_index();
 328
 329         if (board_is_eposevm())
 330                 return &epos_evm_dpll_ddr[ind];
 331         else if (board_is_evm() || board_is_sk())
 332                 return &gp_evm_dpll_ddr;
 333         else if (board_is_idk())
 334                 return &idk_dpll_ddr;
 335
 336         printf(" Board '%s' not supported\n", board_ti_get_name());
 337         return NULL;
 338 }
 339
 340
 341 /*
 342  * get_opp_offset:
 343  * Returns the index for safest OPP of the device to boot.
 344  * max_off:     Index of the MAX OPP in DEV ATTRIBUTE register.
 345  * min_off:     Index of the MIN OPP in DEV ATTRIBUTE register.
 346  * This data is read from dev_attribute register which is e-fused.
 347  * A'1' in bit indicates OPP disabled and not available, a '0' indicates
 348  * OPP available. Lowest OPP starts with min_off. So returning the
 349  * bit with rightmost '0'.
 350  */
 351 static int get_opp_offset(int max_off, int min_off)
 352 {
 353         struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
 354         int opp, offset, i;
 355
 356         /* Bits 0:11 are defined to be the MPU_MAX_FREQ */
 357         opp = readl(&ctrl->dev_attr) & ~0xFFFFF000;
 358
 359         for (i = max_off; i >= min_off; i--) {
 360                 offset = opp & (1 << i);
 361                 if (!offset)
 362                         return i;
 363         }
 364
 365         return min_off;
 366 }
 367
 368 const struct dpll_params *get_dpll_mpu_params(void)
 369 {
 370         int opp = get_opp_offset(DEV_ATTR_MAX_OFFSET, DEV_ATTR_MIN_OFFSET);
 371         u32 ind = get_sys_clk_index();
 372
 373         return &dpll_mpu[ind][opp];
 374 }
 375
 376 const struct dpll_params *get_dpll_core_params(void)
 377 {
 378         int ind = get_sys_clk_index();
 379
 380         return &dpll_core[ind];
 381 }
 382
 383 const struct dpll_params *get_dpll_per_params(void)
 384 {
 385         int ind = get_sys_clk_index();
 386
 387         return &dpll_per[ind];
 388 }
 389
 390 void scale_vcores_generic(u32 m)
 391 {
 392         int mpu_vdd, ddr_volt;
 393
 394 #ifndef CONFIG_DM_I2C
 395         if (i2c_probe(TPS65218_CHIP_PM))
 396                 return;
 397 #else
 398         if (power_tps65218_init(0))
 399                 return;
 400 #endif
 401
 402         switch (m) {
 403         case 1000:
 404                 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV;
 405                 break;
 406         case 800:
 407                 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1260MV;
 408                 break;
 409         case 720:
 410                 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1200MV;
 411                 break;
 412         case 600:
 413                 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV;
 414                 break;
 415         case 300:
 416                 mpu_vdd = TPS65218_DCDC_VOLT_SEL_0950MV;
 417                 break;
 418         default:
 419                 puts("Unknown MPU clock, not scaling\n");
 420                 return;
 421         }
 422
 423         /* Set DCDC1 (CORE) voltage to 1.1V */
 424         if (tps65218_voltage_update(TPS65218_DCDC1,
 425                                     TPS65218_DCDC_VOLT_SEL_1100MV)) {
 426                 printf("%s failure\n", __func__);
 427                 return;
 428         }
 429
 430         /* Set DCDC2 (MPU) voltage */
 431         if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) {
 432                 printf("%s failure\n", __func__);
 433                 return;
 434         }
 435
 436         if (board_is_eposevm())
 437                 ddr_volt = TPS65218_DCDC3_VOLT_SEL_1200MV;
 438         else
 439                 ddr_volt = TPS65218_DCDC3_VOLT_SEL_1350MV;
 440
 441         /* Set DCDC3 (DDR) voltage */
 442         if (tps65218_voltage_update(TPS65218_DCDC3, ddr_volt)) {
 443                 printf("%s failure\n", __func__);
 444                 return;
 445         }
 446 }
 447
 448 void scale_vcores_idk(u32 m)
 449 {
 450         int mpu_vdd;
 451
 452 #ifndef CONFIG_DM_I2C
 453         if (i2c_probe(TPS62362_I2C_ADDR))
 454                 return;
 455 #else
 456         if (power_tps62362_init(0))
 457                 return;
 458 #endif
 459
 460         switch (m) {
 461         case 1000:
 462                 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV;
 463                 break;
 464         case 800:
 465                 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1260MV;
 466                 break;
 467         case 720:
 468                 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1200MV;
 469                 break;
 470         case 600:
 471                 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1100MV;
 472                 break;
 473         case 300:
 474                 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV;
 475                 break;
 476         default:
 477                 puts("Unknown MPU clock, not scaling\n");
 478                 return;
 479         }
 480         /* Set VDD_MPU voltage */
 481         if (tps62362_voltage_update(TPS62362_SET3, mpu_vdd)) {
 482                 printf("%s failure\n", __func__);
 483                 return;
 484         }
 485 }
 486 void gpi2c_init(void)
 487 {
 488         /* When needed to be invoked prior to BSS initialization */
 489         static bool first_time = true;
 490
 491         if (first_time) {
 492                 enable_i2c0_pin_mux();
 493 #ifndef CONFIG_DM_I2C
 494                 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
 495                          CONFIG_SYS_OMAP24_I2C_SLAVE);
 496 #endif
 497                 first_time = false;
 498         }
 499 }
 500
 501 void scale_vcores(void)
 502 {
 503         const struct dpll_params *mpu_params;
 504
 505         /* Ensure I2C is initialized for PMIC configuration */
 506         gpi2c_init();
 507
 508         /* Get the frequency */
 509         mpu_params = get_dpll_mpu_params();
 510
 511         if (board_is_idk())
 512                 scale_vcores_idk(mpu_params->m);
 513         else
 514                 scale_vcores_generic(mpu_params->m);
 515 }
 516
 517 void set_uart_mux_conf(void)
 518 {
 519         enable_uart0_pin_mux();
 520 }
 521
 522 void set_mux_conf_regs(void)
 523 {
 524         enable_board_pin_mux();
 525 }
 526
 527 static void enable_vtt_regulator(void)
 528 {
 529         u32 temp;
 530
 531         /* enable module */
 532         writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL);
 533
 534         /* enable output for GPIO5_7 */
 535         writel(GPIO_SETDATAOUT(7),
 536                AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT);
 537         temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
 538         temp = temp & ~(GPIO_OE_ENABLE(7));
 539         writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
 540 }
 541
 542 enum {
 543         RTC_BOARD_EPOS = 1,
 544         RTC_BOARD_EVM14,
 545         RTC_BOARD_EVM12,
 546         RTC_BOARD_GPEVM,
 547         RTC_BOARD_SK,
 548 };
 549
 550 /*
 551  * In the rtc_only+DRR in self-refresh boot path we have the board type info
 552  * in the rtc scratch pad register hence we bypass the costly i2c reads to
 553  * eeprom and directly programthe board name string
 554  */
 555 void rtc_only_update_board_type(u32 btype)
 556 {
 557         const char *name = "";
 558         const char *rev = "1.0";
 559
 560         switch (btype) {
 561         case RTC_BOARD_EPOS:
 562                 name = "AM43EPOS";
 563                 break;
 564         case RTC_BOARD_EVM14:
 565                 name = "AM43__GP";
 566                 rev = "1.4";
 567                 break;
 568         case RTC_BOARD_EVM12:
 569                 name = "AM43__GP";
 570                 rev = "1.2";
 571                 break;
 572         case RTC_BOARD_GPEVM:
 573                 name = "AM43__GP";
 574                 break;
 575         case RTC_BOARD_SK:
 576                 name = "AM43__SK";
 577                 break;
 578         }
 579         ti_i2c_eeprom_am_set(name, rev);
 580 }
 581
 582 u32 rtc_only_get_board_type(void)
 583 {
 584         if (board_is_eposevm())
 585                 return RTC_BOARD_EPOS;
 586         else if (board_is_evm_14_or_later())
 587                 return RTC_BOARD_EVM14;
 588         else if (board_is_evm_12_or_later())
 589                 return RTC_BOARD_EVM12;
 590         else if (board_is_gpevm())
 591                 return RTC_BOARD_GPEVM;
 592         else if (board_is_sk())
 593                 return RTC_BOARD_SK;
 594
 595         return 0;
 596 }
 597
 598 void sdram_init(void)
 599 {
 600         /*
 601          * EPOS EVM has 1GB LPDDR2 connected to EMIF.
 602          * GP EMV has 1GB DDR3 connected to EMIF
 603          * along with VTT regulator.
 604          */
 605         if (board_is_eposevm()) {
 606                 config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0);
 607         } else if (board_is_evm_14_or_later()) {
 608                 enable_vtt_regulator();
 609                 config_ddr(0, &ioregs_ddr3, NULL, NULL,
 610                            &ddr3_emif_regs_400Mhz_production, 0);
 611         } else if (board_is_evm_12_or_later()) {
 612                 enable_vtt_regulator();
 613                 config_ddr(0, &ioregs_ddr3, NULL, NULL,
 614                            &ddr3_emif_regs_400Mhz_beta, 0);
 615         } else if (board_is_evm()) {
 616                 enable_vtt_regulator();
 617                 config_ddr(0, &ioregs_ddr3, NULL, NULL,
 618                            &ddr3_emif_regs_400Mhz, 0);
 619         } else if (board_is_sk()) {
 620                 config_ddr(400, &ioregs_ddr3, NULL, NULL,
 621                            &ddr3_sk_emif_regs_400Mhz, 0);
 622         } else if (board_is_idk()) {
 623                 config_ddr(400, &ioregs_ddr3, NULL, NULL,
 624                            &ddr3_idk_emif_regs_400Mhz, 0);
 625         }
 626 }
 627 #endif
 628
 629 /* setup board specific PMIC */
 630 int power_init_board(void)
 631 {
 632         int rc;
 633 #ifndef CONFIG_DM_I2C
 634         struct pmic *p = NULL;
 635 #endif
 636         if (board_is_idk()) {
 637                 rc = power_tps62362_init(0);
 638                 if (rc)
 639                         goto done;
 640 #ifndef CONFIG_DM_I2C
 641                 p = pmic_get("TPS62362");
 642                 if (!p || pmic_probe(p))
 643                         goto done;
 644 #endif
 645                 puts("PMIC:  TPS62362\n");
 646         } else {
 647                 rc = power_tps65218_init(0);
 648                 if (rc)
 649                         goto done;
 650 #ifndef CONFIG_DM_I2C
 651                 p = pmic_get("TPS65218_PMIC");
 652                 if (!p || pmic_probe(p))
 653                         goto done;
 654 #endif
 655                 puts("PMIC:  TPS65218\n");
 656         }
 657 done:
 658         return 0;
 659 }
 660
 661 int board_init(void)
 662 {
 663         struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER;
 664         u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional,
 665             modena_init0_bw_integer, modena_init0_watermark_0;
 666
 667         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 668         gpmc_init();
 669
 670         /*
 671          * Call this to initialize *ctrl again
 672          */
 673         hw_data_init();
 674
 675         /* Clear all important bits for DSS errata that may need to be tweaked*/
 676         mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK &
 677                            MREQPRIO_0_SAB_INIT0_MASK;
 678
 679         mreqprio_1 = readl(&cdev->mreqprio_1) & MREQPRIO_1_DSS_MASK;
 680
 681         modena_init0_bw_fractional = readl(&bwlimiter->modena_init0_bw_fractional) &
 682                                            BW_LIMITER_BW_FRAC_MASK;
 683
 684         modena_init0_bw_integer = readl(&bwlimiter->modena_init0_bw_integer) &
 685                                         BW_LIMITER_BW_INT_MASK;
 686
 687         modena_init0_watermark_0 = readl(&bwlimiter->modena_init0_watermark_0) &
 688                                          BW_LIMITER_BW_WATERMARK_MASK;
 689
 690         /* Setting MReq Priority of the DSS*/
 691         mreqprio_0 |= 0x77;
 692
 693         /*
 694          * Set L3 Fast Configuration Register
 695          * Limiting bandwith for ARM core to 700 MBPS
 696          */
 697         modena_init0_bw_fractional |= 0x10;
 698         modena_init0_bw_integer |= 0x3;
 699
 700         writel(mreqprio_0, &cdev->mreqprio_0);
 701         writel(mreqprio_1, &cdev->mreqprio_1);
 702
 703         writel(modena_init0_bw_fractional, &bwlimiter->modena_init0_bw_fractional);
 704         writel(modena_init0_bw_integer, &bwlimiter->modena_init0_bw_integer);
 705         writel(modena_init0_watermark_0, &bwlimiter->modena_init0_watermark_0);
 706
 707         return 0;
 708 }
 709
 710 #ifdef CONFIG_BOARD_LATE_INIT
 711 #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
 712 static int device_okay(const char *path)
 713 {
 714         int node;
 715
 716         node = fdt_path_offset(gd->fdt_blob, path);
 717         if (node < 0)
 718                 return 0;
 719
 720         return fdtdec_get_is_enabled(gd->fdt_blob, node);
 721 }
 722 #endif
 723
 724 int board_late_init(void)
 725 {
 726         struct udevice *dev;
 727 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 728         set_board_info_env(NULL);
 729
 730         /*
 731          * Default FIT boot on HS devices. Non FIT images are not allowed
 732          * on HS devices.
 733          */
 734         if (get_device_type() == HS_DEVICE)
 735                 env_set("boot_fit", "1");
 736 #endif
 737
 738 #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
 739         if (device_okay("/ocp/omap_dwc3@48380000"))
 740                 enable_usb_clocks(0);
 741         if (device_okay("/ocp/omap_dwc3@483c0000"))
 742                 enable_usb_clocks(1);
 743 #endif
 744
 745         /* Just probe the potentially supported cdce913 device */
 746         uclass_get_device(UCLASS_CLK, 0, &dev);
 747
 748         return 0;
 749 }
 750 #endif
 751
 752 #if !CONFIG_IS_ENABLED(DM_USB_GADGET)
 753 #ifdef CONFIG_USB_DWC3
 754 static struct dwc3_device usb_otg_ss1 = {
 755         .maximum_speed = USB_SPEED_HIGH,
 756         .base = USB_OTG_SS1_BASE,
 757         .tx_fifo_resize = false,
 758         .index = 0,
 759 };
 760
 761 static struct dwc3_omap_device usb_otg_ss1_glue = {
 762         .base = (void *)USB_OTG_SS1_GLUE_BASE,
 763         .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
 764         .index = 0,
 765 };
 766
 767 static struct ti_usb_phy_device usb_phy1_device = {
 768         .usb2_phy_power = (void *)USB2_PHY1_POWER,
 769         .index = 0,
 770 };
 771
 772 static struct dwc3_device usb_otg_ss2 = {
 773         .maximum_speed = USB_SPEED_HIGH,
 774         .base = USB_OTG_SS2_BASE,
 775         .tx_fifo_resize = false,
 776         .index = 1,
 777 };
 778
 779 static struct dwc3_omap_device usb_otg_ss2_glue = {
 780         .base = (void *)USB_OTG_SS2_GLUE_BASE,
 781         .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
 782         .index = 1,
 783 };
 784
 785 static struct ti_usb_phy_device usb_phy2_device = {
 786         .usb2_phy_power = (void *)USB2_PHY2_POWER,
 787         .index = 1,
 788 };
 789
 790 int usb_gadget_handle_interrupts(int index)
 791 {
 792         u32 status;
 793
 794         status = dwc3_omap_uboot_interrupt_status(index);
 795         if (status)
 796                 dwc3_uboot_handle_interrupt(index);
 797
 798         return 0;
 799 }
 800 #endif /* CONFIG_USB_DWC3 */
 801
 802 #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
 803 int board_usb_init(int index, enum usb_init_type init)
 804 {
 805         enable_usb_clocks(index);
 806 #ifdef CONFIG_USB_DWC3
 807         switch (index) {
 808         case 0:
 809                 if (init == USB_INIT_DEVICE) {
 810                         usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
 811                         usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
 812                         dwc3_omap_uboot_init(&usb_otg_ss1_glue);
 813                         ti_usb_phy_uboot_init(&usb_phy1_device);
 814                         dwc3_uboot_init(&usb_otg_ss1);
 815                 }
 816                 break;
 817         case 1:
 818                 if (init == USB_INIT_DEVICE) {
 819                         usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
 820                         usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
 821                         ti_usb_phy_uboot_init(&usb_phy2_device);
 822                         dwc3_omap_uboot_init(&usb_otg_ss2_glue);
 823                         dwc3_uboot_init(&usb_otg_ss2);
 824                 }
 825                 break;
 826         default:
 827                 printf("Invalid Controller Index\n");
 828         }
 829 #endif
 830
 831         return 0;
 832 }
 833
 834 int board_usb_cleanup(int index, enum usb_init_type init)
 835 {
 836 #ifdef CONFIG_USB_DWC3
 837         switch (index) {
 838         case 0:
 839         case 1:
 840                 if (init == USB_INIT_DEVICE) {
 841                         ti_usb_phy_uboot_exit(index);
 842                         dwc3_uboot_exit(index);
 843                         dwc3_omap_uboot_exit(index);
 844                 }
 845                 break;
 846         default:
 847                 printf("Invalid Controller Index\n");
 848         }
 849 #endif
 850         disable_usb_clocks(index);
 851
 852         return 0;
 853 }
 854 #endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
 855 #endif /* !CONFIG_IS_ENABLED(DM_USB_GADGET) */
 856
 857 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 858 int ft_board_setup(void *blob, bd_t *bd)
 859 {
 860         ft_cpu_setup(blob, bd);
 861
 862         return 0;
 863 }
 864 #endif
 865
 866 #if defined(CONFIG_SPL_LOAD_FIT) || defined(CONFIG_DTB_RESELECT)
 867 int board_fit_config_name_match(const char *name)
 868 {
 869         bool eeprom_read = board_ti_was_eeprom_read();
 870
 871         if (!strcmp(name, "am4372-generic") && !eeprom_read)
 872                 return 0;
 873         else if (board_is_evm() && !strcmp(name, "am437x-gp-evm"))
 874                 return 0;
 875         else if (board_is_sk() && !strcmp(name, "am437x-sk-evm"))
 876                 return 0;
 877         else if (board_is_eposevm() && !strcmp(name, "am43x-epos-evm"))
 878                 return 0;
 879         else if (board_is_idk() && !strcmp(name, "am437x-idk-evm"))
 880                 return 0;
 881         else
 882                 return -1;
 883 }
 884 #endif
 885
 886 #ifdef CONFIG_DTB_RESELECT
 887 int embedded_dtb_select(void)
 888 {
 889         do_board_detect();
 890         fdtdec_setup();
 891
 892         return 0;
 893 }
 894 #endif
 895
 896 #ifdef CONFIG_TI_SECURE_DEVICE
 897 void board_fit_image_post_process(void **p_image, size_t *p_size)
 898 {
 899         secure_boot_verify_image(p_image, p_size);
 900 }
 901
 902 void board_tee_image_process(ulong tee_image, size_t tee_size)
 903 {
 904         secure_tee_install((u32)tee_image);
 905 }
 906
 907 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
 908 #endif