4 * Board functions for TI AM43XX based boards
6 * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
8 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/errno.h>
15 #include <asm/arch/clock.h>
16 #include <asm/arch/sys_proto.h>
17 #include <asm/arch/mux.h>
18 #include <asm/arch/ddr_defs.h>
19 #include <asm/arch/gpio.h>
22 #include <power/pmic.h>
23 #include <power/tps65218.h>
27 DECLARE_GLOBAL_DATA_PTR;
29 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
32 * Read header information from EEPROM into global structure.
34 static int read_eeprom(struct am43xx_board_id *header)
36 /* Check if baseboard eeprom is available */
37 if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
38 printf("Could not probe the EEPROM at 0x%x\n",
39 CONFIG_SYS_I2C_EEPROM_ADDR);
43 /* read the eeprom using i2c */
44 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,
45 sizeof(struct am43xx_board_id))) {
46 printf("Could not read the EEPROM\n");
50 if (header->magic != 0xEE3355AA) {
52 * read the eeprom using i2c again,
53 * but use only a 1 byte address
55 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
56 sizeof(struct am43xx_board_id))) {
57 printf("Could not read the EEPROM at 0x%x\n",
58 CONFIG_SYS_I2C_EEPROM_ADDR);
62 if (header->magic != 0xEE3355AA) {
63 printf("Incorrect magic number (0x%x) in EEPROM\n",
69 strncpy(am43xx_board_name, (char *)header->name, sizeof(header->name));
70 am43xx_board_name[sizeof(header->name)] = 0;
72 strncpy(am43xx_board_rev, (char *)header->version, sizeof(header->version));
73 am43xx_board_rev[sizeof(header->version)] = 0;
78 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
82 const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = {
84 {-1, -1, -1, -1, -1, -1, -1}, /* OPP 50 */
85 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
86 {-1, -1, -1, -1, -1, -1, -1}, /* OPP 100 */
87 {-1, -1, -1, -1, -1, -1, -1}, /* OPP 120 */
88 {-1, -1, -1, -1, -1, -1, -1}, /* OPP TB */
89 {-1, -1, -1, -1, -1, -1, -1} /* OPP NT */
92 {300, 23, 1, -1, -1, -1, -1}, /* OPP 50 */
93 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
94 {600, 23, 1, -1, -1, -1, -1}, /* OPP 100 */
95 {720, 23, 1, -1, -1, -1, -1}, /* OPP 120 */
96 {800, 23, 1, -1, -1, -1, -1}, /* OPP TB */
97 {1000, 23, 1, -1, -1, -1, -1} /* OPP NT */
100 {300, 24, 1, -1, -1, -1, -1}, /* OPP 50 */
101 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
102 {600, 24, 1, -1, -1, -1, -1}, /* OPP 100 */
103 {720, 24, 1, -1, -1, -1, -1}, /* OPP 120 */
104 {800, 24, 1, -1, -1, -1, -1}, /* OPP TB */
105 {1000, 24, 1, -1, -1, -1, -1} /* OPP NT */
108 {300, 25, 1, -1, -1, -1, -1}, /* OPP 50 */
109 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
110 {600, 25, 1, -1, -1, -1, -1}, /* OPP 100 */
111 {720, 25, 1, -1, -1, -1, -1}, /* OPP 120 */
112 {800, 25, 1, -1, -1, -1, -1}, /* OPP TB */
113 {1000, 25, 1, -1, -1, -1, -1} /* OPP NT */
117 const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = {
118 {-1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
119 {1000, 23, -1, -1, 10, 8, 4}, /* 24 MHz */
120 {1000, 24, -1, -1, 10, 8, 4}, /* 25 MHz */
121 {1000, 25, -1, -1, 10, 8, 4} /* 26 MHz */
124 const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = {
125 {-1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
126 {960, 23, 5, -1, -1, -1, -1}, /* 24 MHz */
127 {960, 24, 5, -1, -1, -1, -1}, /* 25 MHz */
128 {960, 25, 5, -1, -1, -1, -1} /* 26 MHz */
131 const struct dpll_params epos_evm_dpll_ddr = {
132 266, 24, 1, -1, 1, -1, -1};
134 const struct dpll_params gp_evm_dpll_ddr = {
135 400, 23, 1, -1, 1, -1, -1};
137 const struct ctrl_ioregs ioregs_lpddr2 = {
138 .cm0ioctl = LPDDR2_ADDRCTRL_IOCTRL_VALUE,
139 .cm1ioctl = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE,
140 .cm2ioctl = LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE,
141 .dt0ioctl = LPDDR2_DATA0_IOCTRL_VALUE,
142 .dt1ioctl = LPDDR2_DATA0_IOCTRL_VALUE,
143 .dt2ioctrl = LPDDR2_DATA0_IOCTRL_VALUE,
144 .dt3ioctrl = LPDDR2_DATA0_IOCTRL_VALUE,
145 .emif_sdram_config_ext = 0x1,
148 const struct emif_regs emif_regs_lpddr2 = {
149 .sdram_config = 0x808012BA,
150 .ref_ctrl = 0x0000040D,
151 .sdram_tim1 = 0xEA86B411,
152 .sdram_tim2 = 0x103A094A,
153 .sdram_tim3 = 0x0F6BA37F,
154 .read_idle_ctrl = 0x00050000,
155 .zq_config = 0x50074BE4,
156 .temp_alert_config = 0x0,
157 .emif_rd_wr_lvl_rmp_win = 0x0,
158 .emif_rd_wr_lvl_rmp_ctl = 0x0,
159 .emif_rd_wr_lvl_ctl = 0x0,
160 .emif_ddr_phy_ctlr_1 = 0x0E084006,
161 .emif_rd_wr_exec_thresh = 0x80000405,
162 .emif_ddr_ext_phy_ctrl_1 = 0x04010040,
163 .emif_ddr_ext_phy_ctrl_2 = 0x00500050,
164 .emif_ddr_ext_phy_ctrl_3 = 0x00500050,
165 .emif_ddr_ext_phy_ctrl_4 = 0x00500050,
166 .emif_ddr_ext_phy_ctrl_5 = 0x00500050,
167 .emif_prio_class_serv_map = 0x80000001,
168 .emif_connect_id_serv_1_map = 0x80000094,
169 .emif_connect_id_serv_2_map = 0x00000000,
170 .emif_cos_config = 0x000FFFFF
173 const u32 ext_phy_ctrl_const_base_lpddr2[] = {
196 const struct ctrl_ioregs ioregs_ddr3 = {
197 .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE,
198 .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
199 .cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
200 .dt0ioctl = DDR3_DATA0_IOCTRL_VALUE,
201 .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE,
202 .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE,
203 .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE,
204 .emif_sdram_config_ext = 0x0143,
207 const struct emif_regs ddr3_emif_regs_400Mhz = {
208 .sdram_config = 0x638413B2,
209 .ref_ctrl = 0x00000C30,
210 .sdram_tim1 = 0xEAAAD4DB,
211 .sdram_tim2 = 0x266B7FDA,
212 .sdram_tim3 = 0x107F8678,
213 .read_idle_ctrl = 0x00050000,
214 .zq_config = 0x50074BE4,
215 .temp_alert_config = 0x0,
216 .emif_ddr_phy_ctlr_1 = 0x0E004008,
217 .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
218 .emif_ddr_ext_phy_ctrl_2 = 0x00400040,
219 .emif_ddr_ext_phy_ctrl_3 = 0x00400040,
220 .emif_ddr_ext_phy_ctrl_4 = 0x00400040,
221 .emif_ddr_ext_phy_ctrl_5 = 0x00400040,
222 .emif_rd_wr_lvl_rmp_win = 0x0,
223 .emif_rd_wr_lvl_rmp_ctl = 0x0,
224 .emif_rd_wr_lvl_ctl = 0x0,
225 .emif_rd_wr_exec_thresh = 0x80000405,
226 .emif_prio_class_serv_map = 0x80000001,
227 .emif_connect_id_serv_1_map = 0x80000094,
228 .emif_connect_id_serv_2_map = 0x00000000,
229 .emif_cos_config = 0x000FFFFF
232 /* EMIF DDR3 Configurations are different for beta AM43X GP EVMs */
233 const struct emif_regs ddr3_emif_regs_400Mhz_beta = {
234 .sdram_config = 0x638413B2,
235 .ref_ctrl = 0x00000C30,
236 .sdram_tim1 = 0xEAAAD4DB,
237 .sdram_tim2 = 0x266B7FDA,
238 .sdram_tim3 = 0x107F8678,
239 .read_idle_ctrl = 0x00050000,
240 .zq_config = 0x50074BE4,
241 .temp_alert_config = 0x0,
242 .emif_ddr_phy_ctlr_1 = 0x0E004008,
243 .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
244 .emif_ddr_ext_phy_ctrl_2 = 0x00000065,
245 .emif_ddr_ext_phy_ctrl_3 = 0x00000091,
246 .emif_ddr_ext_phy_ctrl_4 = 0x000000B5,
247 .emif_ddr_ext_phy_ctrl_5 = 0x000000E5,
248 .emif_rd_wr_exec_thresh = 0x80000405,
249 .emif_prio_class_serv_map = 0x80000001,
250 .emif_connect_id_serv_1_map = 0x80000094,
251 .emif_connect_id_serv_2_map = 0x00000000,
252 .emif_cos_config = 0x000FFFFF
255 /* EMIF DDR3 Configurations are different for production AM43X GP EVMs */
256 const struct emif_regs ddr3_emif_regs_400Mhz_production = {
257 .sdram_config = 0x638413B2,
258 .ref_ctrl = 0x00000C30,
259 .sdram_tim1 = 0xEAAAD4DB,
260 .sdram_tim2 = 0x266B7FDA,
261 .sdram_tim3 = 0x107F8678,
262 .read_idle_ctrl = 0x00050000,
263 .zq_config = 0x50074BE4,
264 .temp_alert_config = 0x0,
265 .emif_ddr_phy_ctlr_1 = 0x0E004008,
266 .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
267 .emif_ddr_ext_phy_ctrl_2 = 0x00000066,
268 .emif_ddr_ext_phy_ctrl_3 = 0x00000091,
269 .emif_ddr_ext_phy_ctrl_4 = 0x000000B9,
270 .emif_ddr_ext_phy_ctrl_5 = 0x000000E6,
271 .emif_rd_wr_exec_thresh = 0x80000405,
272 .emif_prio_class_serv_map = 0x80000001,
273 .emif_connect_id_serv_1_map = 0x80000094,
274 .emif_connect_id_serv_2_map = 0x00000000,
275 .emif_cos_config = 0x000FFFFF
278 static const struct emif_regs ddr3_sk_emif_regs_400Mhz = {
279 .sdram_config = 0x638413b2,
280 .sdram_config2 = 0x00000000,
281 .ref_ctrl = 0x00000c30,
282 .sdram_tim1 = 0xeaaad4db,
283 .sdram_tim2 = 0x266b7fda,
284 .sdram_tim3 = 0x107f8678,
285 .read_idle_ctrl = 0x00050000,
286 .zq_config = 0x50074be4,
287 .temp_alert_config = 0x0,
288 .emif_ddr_phy_ctlr_1 = 0x0e084008,
289 .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
290 .emif_ddr_ext_phy_ctrl_2 = 0x89,
291 .emif_ddr_ext_phy_ctrl_3 = 0x90,
292 .emif_ddr_ext_phy_ctrl_4 = 0x8e,
293 .emif_ddr_ext_phy_ctrl_5 = 0x8d,
294 .emif_rd_wr_lvl_rmp_win = 0x0,
295 .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
296 .emif_rd_wr_lvl_ctl = 0x00000000,
297 .emif_rd_wr_exec_thresh = 0x80000000,
298 .emif_prio_class_serv_map = 0x80000001,
299 .emif_connect_id_serv_1_map = 0x80000094,
300 .emif_connect_id_serv_2_map = 0x00000000,
301 .emif_cos_config = 0x000FFFFF
304 const u32 ext_phy_ctrl_const_base_ddr3[] = {
327 const u32 ext_phy_ctrl_const_base_ddr3_beta[] = {
350 const u32 ext_phy_ctrl_const_base_ddr3_production[] = {
373 static const u32 ext_phy_ctrl_const_base_ddr3_sk[] = {
374 /* first 5 are taken care by emif_regs */
415 void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
417 if (board_is_eposevm()) {
418 *regs = ext_phy_ctrl_const_base_lpddr2;
419 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2);
420 } else if (board_is_evm_14_or_later()) {
421 *regs = ext_phy_ctrl_const_base_ddr3_production;
422 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_production);
423 } else if (board_is_evm_12_or_later()) {
424 *regs = ext_phy_ctrl_const_base_ddr3_beta;
425 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_beta);
426 } else if (board_is_gpevm()) {
427 *regs = ext_phy_ctrl_const_base_ddr3;
428 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3);
429 } else if (board_is_sk()) {
430 *regs = ext_phy_ctrl_const_base_ddr3_sk;
431 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_sk);
437 const struct dpll_params *get_dpll_ddr_params(void)
439 if (board_is_eposevm())
440 return &epos_evm_dpll_ddr;
441 else if (board_is_gpevm() || board_is_sk())
442 return &gp_evm_dpll_ddr;
444 printf(" Board '%s' not supported\n", am43xx_board_name);
449 * get_sys_clk_index : returns the index of the sys_clk read from
450 * ctrl status register. This value is either
451 * read from efuse or sysboot pins.
453 static u32 get_sys_clk_index(void)
455 struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
456 u32 ind = readl(&ctrl->statusreg), src;
458 src = (ind & CTRL_CRYSTAL_FREQ_SRC_MASK) >> CTRL_CRYSTAL_FREQ_SRC_SHIFT;
459 if (src == CTRL_CRYSTAL_FREQ_SRC_EFUSE) /* Value read from EFUSE */
460 return ((ind & CTRL_CRYSTAL_FREQ_SELECTION_MASK) >>
461 CTRL_CRYSTAL_FREQ_SELECTION_SHIFT);
462 else /* Value read from SYS BOOT pins */
463 return ((ind & CTRL_SYSBOOT_15_14_MASK) >>
464 CTRL_SYSBOOT_15_14_SHIFT);
469 * Returns the index for safest OPP of the device to boot.
470 * max_off: Index of the MAX OPP in DEV ATTRIBUTE register.
471 * min_off: Index of the MIN OPP in DEV ATTRIBUTE register.
472 * This data is read from dev_attribute register which is e-fused.
473 * A'1' in bit indicates OPP disabled and not available, a '0' indicates
474 * OPP available. Lowest OPP starts with min_off. So returning the
475 * bit with rightmost '0'.
477 static int get_opp_offset(int max_off, int min_off)
479 struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
482 /* Bits 0:11 are defined to be the MPU_MAX_FREQ */
483 opp = readl(&ctrl->dev_attr) & ~0xFFFFF000;
485 for (i = max_off; i >= min_off; i--) {
486 offset = opp & (1 << i);
494 const struct dpll_params *get_dpll_mpu_params(void)
496 int opp = get_opp_offset(DEV_ATTR_MAX_OFFSET, DEV_ATTR_MIN_OFFSET);
497 u32 ind = get_sys_clk_index();
499 return &dpll_mpu[ind][opp];
502 const struct dpll_params *get_dpll_core_params(void)
504 int ind = get_sys_clk_index();
506 return &dpll_core[ind];
509 const struct dpll_params *get_dpll_per_params(void)
511 int ind = get_sys_clk_index();
513 return &dpll_per[ind];
516 void scale_vcores(void)
518 const struct dpll_params *mpu_params;
520 struct am43xx_board_id header;
522 enable_i2c0_pin_mux();
523 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
524 if (read_eeprom(&header) < 0)
525 puts("Could not get board ID.\n");
527 /* Get the frequency */
528 mpu_params = get_dpll_mpu_params();
530 if (i2c_probe(TPS65218_CHIP_PM))
533 if (mpu_params->m == 1000) {
534 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV;
535 } else if (mpu_params->m == 600) {
536 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV;
538 puts("Unknown MPU clock, not scaling\n");
542 /* Set DCDC1 (CORE) voltage to 1.1V */
543 if (tps65218_voltage_update(TPS65218_DCDC1,
544 TPS65218_DCDC_VOLT_SEL_1100MV)) {
545 puts("tps65218_voltage_update failure\n");
549 /* Set DCDC2 (MPU) voltage */
550 if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) {
551 puts("tps65218_voltage_update failure\n");
556 void set_uart_mux_conf(void)
558 enable_uart0_pin_mux();
561 void set_mux_conf_regs(void)
563 enable_board_pin_mux();
566 static void enable_vtt_regulator(void)
571 writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL);
573 /* enable output for GPIO5_7 */
574 writel(GPIO_SETDATAOUT(7),
575 AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT);
576 temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
577 temp = temp & ~(GPIO_OE_ENABLE(7));
578 writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
581 void sdram_init(void)
584 * EPOS EVM has 1GB LPDDR2 connected to EMIF.
585 * GP EMV has 1GB DDR3 connected to EMIF
586 * along with VTT regulator.
588 if (board_is_eposevm()) {
589 config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0);
590 } else if (board_is_evm_14_or_later()) {
591 enable_vtt_regulator();
592 config_ddr(0, &ioregs_ddr3, NULL, NULL,
593 &ddr3_emif_regs_400Mhz_production, 0);
594 } else if (board_is_evm_12_or_later()) {
595 enable_vtt_regulator();
596 config_ddr(0, &ioregs_ddr3, NULL, NULL,
597 &ddr3_emif_regs_400Mhz_beta, 0);
598 } else if (board_is_gpevm()) {
599 enable_vtt_regulator();
600 config_ddr(0, &ioregs_ddr3, NULL, NULL,
601 &ddr3_emif_regs_400Mhz, 0);
602 } else if (board_is_sk()) {
603 config_ddr(400, &ioregs_ddr3, NULL, NULL,
604 &ddr3_sk_emif_regs_400Mhz, 0);
609 /* setup board specific PMIC */
610 int power_init_board(void)
614 power_tps65218_init(I2C_PMIC);
615 p = pmic_get("TPS65218_PMIC");
616 if (p && !pmic_probe(p))
617 puts("PMIC: TPS65218\n");
624 struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER;
625 u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional,
626 modena_init0_bw_integer, modena_init0_watermark_0;
628 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
630 /* Clear all important bits for DSS errata that may need to be tweaked*/
631 mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK &
632 MREQPRIO_0_SAB_INIT0_MASK;
634 mreqprio_1 = readl(&cdev->mreqprio_1) & MREQPRIO_1_DSS_MASK;
636 modena_init0_bw_fractional = readl(&bwlimiter->modena_init0_bw_fractional) &
637 BW_LIMITER_BW_FRAC_MASK;
639 modena_init0_bw_integer = readl(&bwlimiter->modena_init0_bw_integer) &
640 BW_LIMITER_BW_INT_MASK;
642 modena_init0_watermark_0 = readl(&bwlimiter->modena_init0_watermark_0) &
643 BW_LIMITER_BW_WATERMARK_MASK;
645 /* Setting MReq Priority of the DSS*/
649 * Set L3 Fast Configuration Register
650 * Limiting bandwith for ARM core to 700 MBPS
652 modena_init0_bw_fractional |= 0x10;
653 modena_init0_bw_integer |= 0x3;
655 writel(mreqprio_0, &cdev->mreqprio_0);
656 writel(mreqprio_1, &cdev->mreqprio_1);
658 writel(modena_init0_bw_fractional, &bwlimiter->modena_init0_bw_fractional);
659 writel(modena_init0_bw_integer, &bwlimiter->modena_init0_bw_integer);
660 writel(modena_init0_watermark_0, &bwlimiter->modena_init0_watermark_0);
665 #ifdef CONFIG_BOARD_LATE_INIT
666 int board_late_init(void)
668 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
669 char safe_string[HDR_NAME_LEN + 1];
670 struct am43xx_board_id header;
672 if (read_eeprom(&header) < 0)
673 puts("Could not get board ID.\n");
675 /* Now set variables based on the header. */
676 strncpy(safe_string, (char *)header.name, sizeof(header.name));
677 safe_string[sizeof(header.name)] = 0;
678 setenv("board_name", safe_string);
680 strncpy(safe_string, (char *)header.version, sizeof(header.version));
681 safe_string[sizeof(header.version)] = 0;
682 setenv("board_rev", safe_string);
688 #ifdef CONFIG_DRIVER_TI_CPSW
690 static void cpsw_control(int enabled)
692 /* Additional controls can be added here */
696 static struct cpsw_slave_data cpsw_slaves[] = {
698 .slave_reg_ofs = 0x208,
699 .sliver_reg_ofs = 0xd80,
703 .slave_reg_ofs = 0x308,
704 .sliver_reg_ofs = 0xdc0,
709 static struct cpsw_platform_data cpsw_data = {
710 .mdio_base = CPSW_MDIO_BASE,
711 .cpsw_base = CPSW_BASE,
714 .cpdma_reg_ofs = 0x800,
716 .slave_data = cpsw_slaves,
717 .ale_reg_ofs = 0xd00,
719 .host_port_reg_ofs = 0x108,
720 .hw_stats_reg_ofs = 0x900,
721 .bd_ram_ofs = 0x2000,
722 .mac_control = (1 << 5),
723 .control = cpsw_control,
725 .version = CPSW_CTRL_VERSION_2,
728 int board_eth_init(bd_t *bis)
732 uint32_t mac_hi, mac_lo;
734 /* try reading mac address from efuse */
735 mac_lo = readl(&cdev->macid0l);
736 mac_hi = readl(&cdev->macid0h);
737 mac_addr[0] = mac_hi & 0xFF;
738 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
739 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
740 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
741 mac_addr[4] = mac_lo & 0xFF;
742 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
744 if (!getenv("ethaddr")) {
745 puts("<ethaddr> not set. Validating first E-fuse MAC\n");
746 if (is_valid_ether_addr(mac_addr))
747 eth_setenv_enetaddr("ethaddr", mac_addr);
750 mac_lo = readl(&cdev->macid1l);
751 mac_hi = readl(&cdev->macid1h);
752 mac_addr[0] = mac_hi & 0xFF;
753 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
754 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
755 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
756 mac_addr[4] = mac_lo & 0xFF;
757 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
759 if (!getenv("eth1addr")) {
760 if (is_valid_ether_addr(mac_addr))
761 eth_setenv_enetaddr("eth1addr", mac_addr);
764 if (board_is_eposevm()) {
765 writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
766 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
767 cpsw_slaves[0].phy_addr = 16;
768 } else if (board_is_sk()) {
769 writel(RGMII_MODE_ENABLE, &cdev->miisel);
770 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
771 cpsw_slaves[0].phy_addr = 4;
772 cpsw_slaves[1].phy_addr = 5;
774 writel(RGMII_MODE_ENABLE, &cdev->miisel);
775 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
776 cpsw_slaves[0].phy_addr = 0;
779 rv = cpsw_register(&cpsw_data);
781 printf("Error %d registering CPSW switch\n", rv);