4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #include <asm/arch/sys_proto.h>
18 #include <asm/arch/hardware.h>
23 #define MUX_CFG(value, offset) \
24 __raw_writel(value, (CTRL_BASE + offset));
26 /* PAD Control Fields */
27 #define SLEWCTRL (0x1 << 6)
28 #define RXACTIVE (0x1 << 5)
29 #define PULLUP_EN (0x1 << 4) /* Pull UP Selection */
30 #define PULLUDEN (0x0 << 3) /* Pull up enabled */
31 #define PULLUDDIS (0x1 << 3) /* Pull up disabled */
32 #define MODE(val) val /* used for Readability */
36 * Field names corresponds to the pad signal name
128 int ecap0_in_pwm0_out;
147 int xdma_event_intr0;
148 int xdma_event_intr1;
247 struct module_pin_mux {
252 /* Pad control register offset */
253 #define PAD_CTRL_BASE 0x800
254 #define OFFSET(x) (unsigned int) (&((struct pad_signals *) \
257 static struct module_pin_mux uart0_pin_mux[] = {
258 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
259 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
263 static struct module_pin_mux mmc0_pin_mux[] = {
264 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
265 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
266 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
267 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
268 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
269 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
270 {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */
271 {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
275 static struct module_pin_mux mmc0_pin_mux_sk_evm[] = {
276 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
277 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
278 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
279 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
280 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
281 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
282 {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
286 static struct module_pin_mux mmc1_pin_mux[] = {
287 {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
288 {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
289 {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
290 {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */
291 {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */
292 {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
293 {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */
294 {OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_CD */
298 static struct module_pin_mux i2c0_pin_mux[] = {
299 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
300 PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
301 {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
302 PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
306 static struct module_pin_mux i2c1_pin_mux[] = {
307 {OFFSET(spi0_d1), (MODE(2) | RXACTIVE |
308 PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
309 {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE |
310 PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
314 static struct module_pin_mux spi0_pin_mux[] = {
315 {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_SCLK */
316 {OFFSET(spi0_d0), (MODE(0) | RXACTIVE |
317 PULLUDEN | PULLUP_EN)}, /* SPI0_D0 */
318 {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_D1 */
319 {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE |
320 PULLUDEN | PULLUP_EN)}, /* SPI0_CS0 */
324 static struct module_pin_mux gpio0_7_pin_mux[] = {
325 {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN)}, /* GPIO0_7 */
329 static struct module_pin_mux rgmii1_pin_mux[] = {
330 {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
331 {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
332 {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */
333 {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */
334 {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */
335 {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */
336 {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */
337 {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */
338 {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
339 {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */
340 {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */
341 {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */
342 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
343 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
347 static struct module_pin_mux mii1_pin_mux[] = {
348 {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
349 {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
350 {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
351 {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
352 {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
353 {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
354 {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */
355 {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */
356 {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */
357 {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */
358 {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */
359 {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */
360 {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */
361 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
362 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
367 * Configure the pin mux for the module
369 static void configure_module_pin_mux(struct module_pin_mux *mod_pin_mux)
376 for (i = 0; mod_pin_mux[i].reg_offset != -1; i++)
377 MUX_CFG(mod_pin_mux[i].val, mod_pin_mux[i].reg_offset);
380 void enable_uart0_pin_mux(void)
382 configure_module_pin_mux(uart0_pin_mux);
386 void enable_i2c0_pin_mux(void)
388 configure_module_pin_mux(i2c0_pin_mux);
392 * The AM335x GP EVM, if daughter card(s) are connected, can have 8
393 * different profiles. These profiles determine what peripherals are
394 * valid and need pinmux to be configured.
396 #define PROFILE_NONE 0x0
397 #define PROFILE_0 (1 << 0)
398 #define PROFILE_1 (1 << 1)
399 #define PROFILE_2 (1 << 2)
400 #define PROFILE_3 (1 << 3)
401 #define PROFILE_4 (1 << 4)
402 #define PROFILE_5 (1 << 5)
403 #define PROFILE_6 (1 << 6)
404 #define PROFILE_7 (1 << 7)
405 #define PROFILE_MASK 0x7
406 #define PROFILE_ALL 0xFF
409 #define I2C_CPLD_ADDR 0x35
412 static unsigned short detect_daughter_board_profile(void)
416 if (i2c_probe(I2C_CPLD_ADDR))
419 if (i2c_read(I2C_CPLD_ADDR, CFG_REG, 1, (unsigned char *)(&val), 2))
422 return (1 << (val & PROFILE_MASK));
425 void enable_board_pin_mux(struct am335x_baseboard_id *header)
427 /* Do board-specific muxes. */
428 if (!strncmp(header->name, "A335BONE", HDR_NAME_LEN)) {
429 /* Beaglebone pinmux */
430 configure_module_pin_mux(i2c1_pin_mux);
431 configure_module_pin_mux(mii1_pin_mux);
432 configure_module_pin_mux(mmc0_pin_mux);
433 configure_module_pin_mux(mmc1_pin_mux);
434 } else if (!strncmp(header->config, "SKU#01", 6)) {
435 /* General Purpose EVM */
436 unsigned short profile = detect_daughter_board_profile();
437 configure_module_pin_mux(rgmii1_pin_mux);
438 configure_module_pin_mux(mmc0_pin_mux);
439 /* In profile #2 i2c1 and spi0 conflict. */
440 if (profile & ~PROFILE_2)
441 configure_module_pin_mux(i2c1_pin_mux);
442 else if (profile == PROFILE_2) {
443 configure_module_pin_mux(mmc1_pin_mux);
444 configure_module_pin_mux(spi0_pin_mux);
446 } else if (!strncmp(header->name, "A335X_SK", HDR_NAME_LEN)) {
447 /* Starter Kit EVM */
448 configure_module_pin_mux(i2c1_pin_mux);
449 configure_module_pin_mux(gpio0_7_pin_mux);
450 configure_module_pin_mux(rgmii1_pin_mux);
451 configure_module_pin_mux(mmc0_pin_mux_sk_evm);
453 puts("Unknown board, cannot configure pinmux.");