board/ti/am335x/board.c

   1 /*
   2  * board.c
   3  *
   4  * Board functions for TI AM335X based boards
   5  *
   6  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <dm.h>
  13 #include <errno.h>
  14 #include <spl.h>
  15 #include <serial.h>
  16 #include <asm/arch/cpu.h>
  17 #include <asm/arch/hardware.h>
  18 #include <asm/arch/omap.h>
  19 #include <asm/arch/ddr_defs.h>
  20 #include <asm/arch/clock.h>
  21 #include <asm/arch/clk_synthesizer.h>
  22 #include <asm/arch/gpio.h>
  23 #include <asm/arch/mmc_host_def.h>
  24 #include <asm/arch/sys_proto.h>
  25 #include <asm/arch/mem.h>
  26 #include <asm/io.h>
  27 #include <asm/emif.h>
  28 #include <asm/gpio.h>
  29 #include <asm/omap_sec_common.h>
  30 #include <asm/omap_mmc.h>
  31 #include <i2c.h>
  32 #include <miiphy.h>
  33 #include <cpsw.h>
  34 #include <power/tps65217.h>
  35 #include <power/tps65910.h>
  36 #include <environment.h>
  37 #include <watchdog.h>
  38 #include <environment.h>
  39 #include "../common/board_detect.h"
  40 #include "board.h"
  41
  42 DECLARE_GLOBAL_DATA_PTR;
  43
  44 /* GPIO that controls power to DDR on EVM-SK */
  45 #define GPIO_TO_PIN(bank, gpio)         (32 * (bank) + (gpio))
  46 #define GPIO_DDR_VTT_EN         GPIO_TO_PIN(0, 7)
  47 #define ICE_GPIO_DDR_VTT_EN     GPIO_TO_PIN(0, 18)
  48 #define GPIO_PR1_MII_CTRL       GPIO_TO_PIN(3, 4)
  49 #define GPIO_MUX_MII_CTRL       GPIO_TO_PIN(3, 10)
  50 #define GPIO_FET_SWITCH_CTRL    GPIO_TO_PIN(0, 7)
  51 #define GPIO_PHY_RESET          GPIO_TO_PIN(2, 5)
  52 #define GPIO_ETH0_MODE          GPIO_TO_PIN(0, 11)
  53 #define GPIO_ETH1_MODE          GPIO_TO_PIN(1, 26)
  54
  55 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  56
  57 #define GPIO0_RISINGDETECT      (AM33XX_GPIO0_BASE + OMAP_GPIO_RISINGDETECT)
  58 #define GPIO1_RISINGDETECT      (AM33XX_GPIO1_BASE + OMAP_GPIO_RISINGDETECT)
  59
  60 #define GPIO0_IRQSTATUS1        (AM33XX_GPIO0_BASE + OMAP_GPIO_IRQSTATUS1)
  61 #define GPIO1_IRQSTATUS1        (AM33XX_GPIO1_BASE + OMAP_GPIO_IRQSTATUS1)
  62
  63 #define GPIO0_IRQSTATUSRAW      (AM33XX_GPIO0_BASE + 0x024)
  64 #define GPIO1_IRQSTATUSRAW      (AM33XX_GPIO1_BASE + 0x024)
  65
  66 /*
  67  * Read header information from EEPROM into global structure.
  68  */
  69 #ifdef CONFIG_TI_I2C_BOARD_DETECT
  70 void do_board_detect(void)
  71 {
  72         enable_i2c0_pin_mux();
  73         i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
  74
  75         if (ti_i2c_eeprom_am_get(-1, CONFIG_SYS_I2C_EEPROM_ADDR))
  76                 printf("ti_i2c_eeprom_init failed\n");
  77 }
  78 #endif
  79
  80 #ifndef CONFIG_DM_SERIAL
  81 struct serial_device *default_serial_console(void)
  82 {
  83         if (board_is_icev2())
  84                 return &eserial4_device;
  85         else
  86                 return &eserial1_device;
  87 }
  88 #endif
  89
  90 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  91 static const struct ddr_data ddr2_data = {
  92         .datardsratio0 = MT47H128M16RT25E_RD_DQS,
  93         .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
  94         .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
  95 };
  96
  97 static const struct cmd_control ddr2_cmd_ctrl_data = {
  98         .cmd0csratio = MT47H128M16RT25E_RATIO,
  99
 100         .cmd1csratio = MT47H128M16RT25E_RATIO,
 101
 102         .cmd2csratio = MT47H128M16RT25E_RATIO,
 103 };
 104
 105 static const struct emif_regs ddr2_emif_reg_data = {
 106         .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
 107         .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
 108         .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
 109         .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
 110         .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
 111         .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
 112 };
 113
 114 static const struct emif_regs ddr2_evm_emif_reg_data = {
 115         .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
 116         .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
 117         .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
 118         .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
 119         .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
 120         .ocp_config = EMIF_OCP_CONFIG_AM335X_EVM,
 121         .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
 122 };
 123
 124 static const struct ddr_data ddr3_data = {
 125         .datardsratio0 = MT41J128MJT125_RD_DQS,
 126         .datawdsratio0 = MT41J128MJT125_WR_DQS,
 127         .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
 128         .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
 129 };
 130
 131 static const struct ddr_data ddr3_beagleblack_data = {
 132         .datardsratio0 = MT41K256M16HA125E_RD_DQS,
 133         .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
 134         .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
 135         .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
 136 };
 137
 138 static const struct ddr_data ddr3_evm_data = {
 139         .datardsratio0 = MT41J512M8RH125_RD_DQS,
 140         .datawdsratio0 = MT41J512M8RH125_WR_DQS,
 141         .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
 142         .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
 143 };
 144
 145 static const struct ddr_data ddr3_icev2_data = {
 146         .datardsratio0 = MT41J128MJT125_RD_DQS_400MHz,
 147         .datawdsratio0 = MT41J128MJT125_WR_DQS_400MHz,
 148         .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE_400MHz,
 149         .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA_400MHz,
 150 };
 151
 152 static const struct cmd_control ddr3_cmd_ctrl_data = {
 153         .cmd0csratio = MT41J128MJT125_RATIO,
 154         .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
 155
 156         .cmd1csratio = MT41J128MJT125_RATIO,
 157         .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
 158
 159         .cmd2csratio = MT41J128MJT125_RATIO,
 160         .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
 161 };
 162
 163 static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
 164         .cmd0csratio = MT41K256M16HA125E_RATIO,
 165         .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 166
 167         .cmd1csratio = MT41K256M16HA125E_RATIO,
 168         .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 169
 170         .cmd2csratio = MT41K256M16HA125E_RATIO,
 171         .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 172 };
 173
 174 static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
 175         .cmd0csratio = MT41J512M8RH125_RATIO,
 176         .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,
 177
 178         .cmd1csratio = MT41J512M8RH125_RATIO,
 179         .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,
 180
 181         .cmd2csratio = MT41J512M8RH125_RATIO,
 182         .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
 183 };
 184
 185 static const struct cmd_control ddr3_icev2_cmd_ctrl_data = {
 186         .cmd0csratio = MT41J128MJT125_RATIO_400MHz,
 187         .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
 188
 189         .cmd1csratio = MT41J128MJT125_RATIO_400MHz,
 190         .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
 191
 192         .cmd2csratio = MT41J128MJT125_RATIO_400MHz,
 193         .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
 194 };
 195
 196 static struct emif_regs ddr3_emif_reg_data = {
 197         .sdram_config = MT41J128MJT125_EMIF_SDCFG,
 198         .ref_ctrl = MT41J128MJT125_EMIF_SDREF,
 199         .sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
 200         .sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
 201         .sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
 202         .zq_config = MT41J128MJT125_ZQ_CFG,
 203         .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
 204                                 PHY_EN_DYN_PWRDN,
 205 };
 206
 207 static struct emif_regs ddr3_beagleblack_emif_reg_data = {
 208         .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
 209         .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
 210         .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
 211         .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
 212         .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
 213         .ocp_config = EMIF_OCP_CONFIG_BEAGLEBONE_BLACK,
 214         .zq_config = MT41K256M16HA125E_ZQ_CFG,
 215         .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
 216 };
 217
 218 static struct emif_regs ddr3_evm_emif_reg_data = {
 219         .sdram_config = MT41J512M8RH125_EMIF_SDCFG,
 220         .ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
 221         .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
 222         .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
 223         .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
 224         .ocp_config = EMIF_OCP_CONFIG_AM335X_EVM,
 225         .zq_config = MT41J512M8RH125_ZQ_CFG,
 226         .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
 227                                 PHY_EN_DYN_PWRDN,
 228 };
 229
 230 static struct emif_regs ddr3_icev2_emif_reg_data = {
 231         .sdram_config = MT41J128MJT125_EMIF_SDCFG_400MHz,
 232         .ref_ctrl = MT41J128MJT125_EMIF_SDREF_400MHz,
 233         .sdram_tim1 = MT41J128MJT125_EMIF_TIM1_400MHz,
 234         .sdram_tim2 = MT41J128MJT125_EMIF_TIM2_400MHz,
 235         .sdram_tim3 = MT41J128MJT125_EMIF_TIM3_400MHz,
 236         .zq_config = MT41J128MJT125_ZQ_CFG_400MHz,
 237         .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY_400MHz |
 238                                 PHY_EN_DYN_PWRDN,
 239 };
 240
 241 #ifdef CONFIG_SPL_OS_BOOT
 242 int spl_start_uboot(void)
 243 {
 244         /* break into full u-boot on 'c' */
 245         if (serial_tstc() && serial_getc() == 'c')
 246                 return 1;
 247
 248 #ifdef CONFIG_SPL_ENV_SUPPORT
 249         env_init();
 250         env_relocate_spec();
 251         if (getenv_yesno("boot_os") != 1)
 252                 return 1;
 253 #endif
 254
 255         return 0;
 256 }
 257 #endif
 258
 259 #define OSC     (V_OSCK/1000000)
 260 const struct dpll_params dpll_ddr = {
 261                 266, OSC-1, 1, -1, -1, -1, -1};
 262 const struct dpll_params dpll_ddr_evm_sk = {
 263                 303, OSC-1, 1, -1, -1, -1, -1};
 264 const struct dpll_params dpll_ddr_bone_black = {
 265                 400, OSC-1, 1, -1, -1, -1, -1};
 266
 267 void am33xx_spl_board_init(void)
 268 {
 269         int mpu_vdd;
 270
 271         /* Get the frequency */
 272         dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
 273
 274         if (board_is_bone() || board_is_bone_lt()) {
 275                 /* BeagleBone PMIC Code */
 276                 int usb_cur_lim;
 277
 278                 /*
 279                  * Only perform PMIC configurations if board rev > A1
 280                  * on Beaglebone White
 281                  */
 282                 if (board_is_bone() && !strncmp(board_ti_get_rev(), "00A1", 4))
 283                         return;
 284
 285                 if (i2c_probe(TPS65217_CHIP_PM))
 286                         return;
 287
 288                 /*
 289                  * On Beaglebone White we need to ensure we have AC power
 290                  * before increasing the frequency.
 291                  */
 292                 if (board_is_bone()) {
 293                         uchar pmic_status_reg;
 294                         if (tps65217_reg_read(TPS65217_STATUS,
 295                                               &pmic_status_reg))
 296                                 return;
 297                         if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) {
 298                                 puts("No AC power, disabling frequency switch\n");
 299                                 return;
 300                         }
 301                 }
 302
 303                 /*
 304                  * Override what we have detected since we know if we have
 305                  * a Beaglebone Black it supports 1GHz.
 306                  */
 307                 if (board_is_bone_lt())
 308                         dpll_mpu_opp100.m = MPUPLL_M_1000;
 309
 310                 /*
 311                  * Increase USB current limit to 1300mA or 1800mA and set
 312                  * the MPU voltage controller as needed.
 313                  */
 314                 if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
 315                         usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
 316                         mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
 317                 } else {
 318                         usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
 319                         mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
 320                 }
 321
 322                 if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
 323                                        TPS65217_POWER_PATH,
 324                                        usb_cur_lim,
 325                                        TPS65217_USB_INPUT_CUR_LIMIT_MASK))
 326                         puts("tps65217_reg_write failure\n");
 327
 328                 /* Set DCDC3 (CORE) voltage to 1.125V */
 329                 if (tps65217_voltage_update(TPS65217_DEFDCDC3,
 330                                             TPS65217_DCDC_VOLT_SEL_1125MV)) {
 331                         puts("tps65217_voltage_update failure\n");
 332                         return;
 333                 }
 334
 335                 /* Set CORE Frequencies to OPP100 */
 336                 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
 337
 338                 /* Set DCDC2 (MPU) voltage */
 339                 if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
 340                         puts("tps65217_voltage_update failure\n");
 341                         return;
 342                 }
 343
 344                 /*
 345                  * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
 346                  * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
 347                  */
 348                 if (board_is_bone()) {
 349                         if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
 350                                                TPS65217_DEFLS1,
 351                                                TPS65217_LDO_VOLTAGE_OUT_3_3,
 352                                                TPS65217_LDO_MASK))
 353                                 puts("tps65217_reg_write failure\n");
 354                 } else {
 355                         if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
 356                                                TPS65217_DEFLS1,
 357                                                TPS65217_LDO_VOLTAGE_OUT_1_8,
 358                                                TPS65217_LDO_MASK))
 359                                 puts("tps65217_reg_write failure\n");
 360                 }
 361
 362                 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
 363                                        TPS65217_DEFLS2,
 364                                        TPS65217_LDO_VOLTAGE_OUT_3_3,
 365                                        TPS65217_LDO_MASK))
 366                         puts("tps65217_reg_write failure\n");
 367         } else {
 368                 int sil_rev;
 369
 370                 /*
 371                  * The GP EVM, IDK and EVM SK use a TPS65910 PMIC.  For all
 372                  * MPU frequencies we support we use a CORE voltage of
 373                  * 1.1375V.  For MPU voltage we need to switch based on
 374                  * the frequency we are running at.
 375                  */
 376                 if (i2c_probe(TPS65910_CTRL_I2C_ADDR))
 377                         return;
 378
 379                 /*
 380                  * Depending on MPU clock and PG we will need a different
 381                  * VDD to drive at that speed.
 382                  */
 383                 sil_rev = readl(&cdev->deviceid) >> 28;
 384                 mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev,
 385                                                       dpll_mpu_opp100.m);
 386
 387                 /* Tell the TPS65910 to use i2c */
 388                 tps65910_set_i2c_control();
 389
 390                 /* First update MPU voltage. */
 391                 if (tps65910_voltage_update(MPU, mpu_vdd))
 392                         return;
 393
 394                 /* Second, update the CORE voltage. */
 395                 if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3))
 396                         return;
 397
 398                 /* Set CORE Frequencies to OPP100 */
 399                 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
 400         }
 401
 402         /* Set MPU Frequency to what we detected now that voltages are set */
 403         do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
 404 }
 405
 406 const struct dpll_params *get_dpll_ddr_params(void)
 407 {
 408         if (board_is_evm_sk())
 409                 return &dpll_ddr_evm_sk;
 410         else if (board_is_bone_lt() || board_is_icev2())
 411                 return &dpll_ddr_bone_black;
 412         else if (board_is_evm_15_or_later())
 413                 return &dpll_ddr_evm_sk;
 414         else
 415                 return &dpll_ddr;
 416 }
 417
 418 void set_uart_mux_conf(void)
 419 {
 420 #if CONFIG_CONS_INDEX == 1
 421         enable_uart0_pin_mux();
 422 #elif CONFIG_CONS_INDEX == 2
 423         enable_uart1_pin_mux();
 424 #elif CONFIG_CONS_INDEX == 3
 425         enable_uart2_pin_mux();
 426 #elif CONFIG_CONS_INDEX == 4
 427         enable_uart3_pin_mux();
 428 #elif CONFIG_CONS_INDEX == 5
 429         enable_uart4_pin_mux();
 430 #elif CONFIG_CONS_INDEX == 6
 431         enable_uart5_pin_mux();
 432 #endif
 433 }
 434
 435 void set_mux_conf_regs(void)
 436 {
 437         enable_board_pin_mux();
 438 }
 439
 440 const struct ctrl_ioregs ioregs_evmsk = {
 441         .cm0ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 442         .cm1ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 443         .cm2ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 444         .dt0ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 445         .dt1ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 446 };
 447
 448 const struct ctrl_ioregs ioregs_bonelt = {
 449         .cm0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 450         .cm1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 451         .cm2ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 452         .dt0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 453         .dt1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 454 };
 455
 456 const struct ctrl_ioregs ioregs_evm15 = {
 457         .cm0ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 458         .cm1ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 459         .cm2ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 460         .dt0ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 461         .dt1ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 462 };
 463
 464 const struct ctrl_ioregs ioregs = {
 465         .cm0ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 466         .cm1ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 467         .cm2ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 468         .dt0ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 469         .dt1ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 470 };
 471
 472 void sdram_init(void)
 473 {
 474         if (board_is_evm_sk()) {
 475                 /*
 476                  * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
 477                  * This is safe enough to do on older revs.
 478                  */
 479                 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
 480                 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
 481         }
 482
 483         if (board_is_icev2()) {
 484                 gpio_request(ICE_GPIO_DDR_VTT_EN, "ddr_vtt_en");
 485                 gpio_direction_output(ICE_GPIO_DDR_VTT_EN, 1);
 486         }
 487
 488         if (board_is_evm_sk())
 489                 config_ddr(303, &ioregs_evmsk, &ddr3_data,
 490                            &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
 491         else if (board_is_bone_lt())
 492                 config_ddr(400, &ioregs_bonelt,
 493                            &ddr3_beagleblack_data,
 494                            &ddr3_beagleblack_cmd_ctrl_data,
 495                            &ddr3_beagleblack_emif_reg_data, 0);
 496         else if (board_is_evm_15_or_later())
 497                 config_ddr(303, &ioregs_evm15, &ddr3_evm_data,
 498                            &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
 499         else if (board_is_icev2())
 500                 config_ddr(400, &ioregs_evmsk, &ddr3_icev2_data,
 501                            &ddr3_icev2_cmd_ctrl_data, &ddr3_icev2_emif_reg_data,
 502                            0);
 503         else if (board_is_gp_evm())
 504                 config_ddr(266, &ioregs, &ddr2_data,
 505                            &ddr2_cmd_ctrl_data, &ddr2_evm_emif_reg_data, 0);
 506         else
 507                 config_ddr(266, &ioregs, &ddr2_data,
 508                            &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
 509 }
 510 #endif
 511
 512 #if !defined(CONFIG_SPL_BUILD) || \
 513         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 514 static void request_and_set_gpio(int gpio, char *name, int val)
 515 {
 516         int ret;
 517
 518         ret = gpio_request(gpio, name);
 519         if (ret < 0) {
 520                 printf("%s: Unable to request %s\n", __func__, name);
 521                 return;
 522         }
 523
 524         ret = gpio_direction_output(gpio, 0);
 525         if (ret < 0) {
 526                 printf("%s: Unable to set %s  as output\n", __func__, name);
 527                 goto err_free_gpio;
 528         }
 529
 530         gpio_set_value(gpio, val);
 531
 532         return;
 533
 534 err_free_gpio:
 535         gpio_free(gpio);
 536 }
 537
 538 #define REQUEST_AND_SET_GPIO(N) request_and_set_gpio(N, #N, 1);
 539 #define REQUEST_AND_CLR_GPIO(N) request_and_set_gpio(N, #N, 0);
 540
 541 /**
 542  * RMII mode on ICEv2 board needs 50MHz clock. Given the clock
 543  * synthesizer With a capacitor of 18pF, and 25MHz input clock cycle
 544  * PLL1 gives an output of 100MHz. So, configuring the div2/3 as 2 to
 545  * give 50MHz output for Eth0 and 1.
 546  */
 547 static struct clk_synth cdce913_data = {
 548         .id = 0x81,
 549         .capacitor = 0x90,
 550         .mux = 0x6d,
 551         .pdiv2 = 0x2,
 552         .pdiv3 = 0x2,
 553 };
 554 #endif
 555
 556 /*
 557  * Basic board specific setup.  Pinmux has been handled already.
 558  */
 559 int board_init(void)
 560 {
 561 #if defined(CONFIG_HW_WATCHDOG)
 562         hw_watchdog_init();
 563 #endif
 564
 565         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 566 #if defined(CONFIG_NOR) || defined(CONFIG_NAND)
 567         gpmc_init();
 568 #endif
 569
 570 #if !defined(CONFIG_SPL_BUILD) || \
 571         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 572         if (board_is_icev2()) {
 573                 int rv;
 574                 u32 reg;
 575
 576                 REQUEST_AND_SET_GPIO(GPIO_PR1_MII_CTRL);
 577                 /* Make J19 status available on GPIO1_26 */
 578                 REQUEST_AND_CLR_GPIO(GPIO_MUX_MII_CTRL);
 579
 580                 REQUEST_AND_SET_GPIO(GPIO_FET_SWITCH_CTRL);
 581                 /*
 582                  * Both ports can be set as RMII-CPSW or MII-PRU-ETH using
 583                  * jumpers near the port. Read the jumper value and set
 584                  * the pinmux, external mux and PHY clock accordingly.
 585                  * As jumper line is overridden by PHY RX_DV pin immediately
 586                  * after bootstrap (power-up/reset), we need to sample
 587                  * it during PHY reset using GPIO rising edge detection.
 588                  */
 589                 REQUEST_AND_SET_GPIO(GPIO_PHY_RESET);
 590                 /* Enable rising edge IRQ on GPIO0_11 and GPIO 1_26 */
 591                 reg = readl(GPIO0_RISINGDETECT) | BIT(11);
 592                 writel(reg, GPIO0_RISINGDETECT);
 593                 reg = readl(GPIO1_RISINGDETECT) | BIT(26);
 594                 writel(reg, GPIO1_RISINGDETECT);
 595                 /* Reset PHYs to capture the Jumper setting */
 596                 gpio_set_value(GPIO_PHY_RESET, 0);
 597                 udelay(2);      /* PHY datasheet states 1uS min. */
 598                 gpio_set_value(GPIO_PHY_RESET, 1);
 599
 600                 reg = readl(GPIO0_IRQSTATUSRAW) & BIT(11);
 601                 if (reg) {
 602                         writel(reg, GPIO0_IRQSTATUS1); /* clear irq */
 603                         /* RMII mode */
 604                         printf("ETH0, CPSW\n");
 605                 } else {
 606                         /* MII mode */
 607                         printf("ETH0, PRU\n");
 608                         cdce913_data.pdiv3 = 4; /* 25MHz PHY clk */
 609                 }
 610
 611                 reg = readl(GPIO1_IRQSTATUSRAW) & BIT(26);
 612                 if (reg) {
 613                         writel(reg, GPIO1_IRQSTATUS1); /* clear irq */
 614                         /* RMII mode */
 615                         printf("ETH1, CPSW\n");
 616                         gpio_set_value(GPIO_MUX_MII_CTRL, 1);
 617                 } else {
 618                         /* MII mode */
 619                         printf("ETH1, PRU\n");
 620                         cdce913_data.pdiv2 = 4; /* 25MHz PHY clk */
 621                 }
 622
 623                 /* disable rising edge IRQs */
 624                 reg = readl(GPIO0_RISINGDETECT) & ~BIT(11);
 625                 writel(reg, GPIO0_RISINGDETECT);
 626                 reg = readl(GPIO1_RISINGDETECT) & ~BIT(26);
 627                 writel(reg, GPIO1_RISINGDETECT);
 628
 629                 rv = setup_clock_synthesizer(&cdce913_data);
 630                 if (rv) {
 631                         printf("Clock synthesizer setup failed %d\n", rv);
 632                         return rv;
 633                 }
 634
 635                 /* reset PHYs */
 636                 gpio_set_value(GPIO_PHY_RESET, 0);
 637                 udelay(2);      /* PHY datasheet states 1uS min. */
 638                 gpio_set_value(GPIO_PHY_RESET, 1);
 639         }
 640 #endif
 641
 642         return 0;
 643 }
 644
 645 #ifdef CONFIG_BOARD_LATE_INIT
 646 int board_late_init(void)
 647 {
 648 #if !defined(CONFIG_SPL_BUILD)
 649         uint8_t mac_addr[6];
 650         uint32_t mac_hi, mac_lo;
 651 #endif
 652
 653 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 654         char *name = NULL;
 655
 656         if (board_is_bone_lt()) {
 657                 /* BeagleBoard.org BeagleBone Black Wireless: */
 658                 if (!strncmp(board_ti_get_rev(), "BWA", 3)) {
 659                         name = "BBBW";
 660                 }
 661                 /* SeeedStudio BeagleBone Green Wireless */
 662                 if (!strncmp(board_ti_get_rev(), "GW1", 3)) {
 663                         name = "BBGW";
 664                 }
 665                 /* BeagleBoard.org BeagleBone Blue */
 666                 if (!strncmp(board_ti_get_rev(), "BLA", 3)) {
 667                         name = "BBBL";
 668                 }
 669         }
 670
 671         if (board_is_bbg1())
 672                 name = "BBG1";
 673         set_board_info_env(name);
 674
 675         /*
 676          * Default FIT boot on HS devices. Non FIT images are not allowed
 677          * on HS devices.
 678          */
 679         if (get_device_type() == HS_DEVICE)
 680                 setenv("boot_fit", "1");
 681 #endif
 682
 683 #if !defined(CONFIG_SPL_BUILD)
 684         /* try reading mac address from efuse */
 685         mac_lo = readl(&cdev->macid0l);
 686         mac_hi = readl(&cdev->macid0h);
 687         mac_addr[0] = mac_hi & 0xFF;
 688         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 689         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 690         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 691         mac_addr[4] = mac_lo & 0xFF;
 692         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 693
 694         if (!getenv("ethaddr")) {
 695                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
 696
 697                 if (is_valid_ethaddr(mac_addr))
 698                         eth_setenv_enetaddr("ethaddr", mac_addr);
 699         }
 700
 701         mac_lo = readl(&cdev->macid1l);
 702         mac_hi = readl(&cdev->macid1h);
 703         mac_addr[0] = mac_hi & 0xFF;
 704         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 705         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 706         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 707         mac_addr[4] = mac_lo & 0xFF;
 708         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 709
 710         if (!getenv("eth1addr")) {
 711                 if (is_valid_ethaddr(mac_addr))
 712                         eth_setenv_enetaddr("eth1addr", mac_addr);
 713         }
 714 #endif
 715
 716         return 0;
 717 }
 718 #endif
 719
 720 #ifndef CONFIG_DM_ETH
 721
 722 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
 723         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 724 static void cpsw_control(int enabled)
 725 {
 726         /* VTP can be added here */
 727
 728         return;
 729 }
 730
 731 static struct cpsw_slave_data cpsw_slaves[] = {
 732         {
 733                 .slave_reg_ofs  = 0x208,
 734                 .sliver_reg_ofs = 0xd80,
 735                 .phy_addr       = 0,
 736         },
 737         {
 738                 .slave_reg_ofs  = 0x308,
 739                 .sliver_reg_ofs = 0xdc0,
 740                 .phy_addr       = 1,
 741         },
 742 };
 743
 744 static struct cpsw_platform_data cpsw_data = {
 745         .mdio_base              = CPSW_MDIO_BASE,
 746         .cpsw_base              = CPSW_BASE,
 747         .mdio_div               = 0xff,
 748         .channels               = 8,
 749         .cpdma_reg_ofs          = 0x800,
 750         .slaves                 = 1,
 751         .slave_data             = cpsw_slaves,
 752         .ale_reg_ofs            = 0xd00,
 753         .ale_entries            = 1024,
 754         .host_port_reg_ofs      = 0x108,
 755         .hw_stats_reg_ofs       = 0x900,
 756         .bd_ram_ofs             = 0x2000,
 757         .mac_control            = (1 << 5),
 758         .control                = cpsw_control,
 759         .host_port_num          = 0,
 760         .version                = CPSW_CTRL_VERSION_2,
 761 };
 762 #endif
 763
 764 #if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) &&\
 765         defined(CONFIG_SPL_BUILD)) || \
 766         ((defined(CONFIG_DRIVER_TI_CPSW) || \
 767           defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \
 768          !defined(CONFIG_SPL_BUILD))
 769
 770 /*
 771  * This function will:
 772  * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
 773  * in the environment
 774  * Perform fixups to the PHY present on certain boards.  We only need this
 775  * function in:
 776  * - SPL with either CPSW or USB ethernet support
 777  * - Full U-Boot, with either CPSW or USB ethernet
 778  * Build in only these cases to avoid warnings about unused variables
 779  * when we build an SPL that has neither option but full U-Boot will.
 780  */
 781 int board_eth_init(bd_t *bis)
 782 {
 783         int rv, n = 0;
 784 #if defined(CONFIG_USB_ETHER) && \
 785         (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
 786         uint8_t mac_addr[6];
 787         uint32_t mac_hi, mac_lo;
 788
 789         /*
 790          * use efuse mac address for USB ethernet as we know that
 791          * both CPSW and USB ethernet will never be active at the same time
 792          */
 793         mac_lo = readl(&cdev->macid0l);
 794         mac_hi = readl(&cdev->macid0h);
 795         mac_addr[0] = mac_hi & 0xFF;
 796         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 797         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 798         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 799         mac_addr[4] = mac_lo & 0xFF;
 800         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 801 #endif
 802
 803
 804 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
 805         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 806
 807 #ifdef CONFIG_DRIVER_TI_CPSW
 808         if (board_is_bone() || board_is_bone_lt() ||
 809             board_is_idk()) {
 810                 writel(MII_MODE_ENABLE, &cdev->miisel);
 811                 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
 812                                 PHY_INTERFACE_MODE_MII;
 813         } else if (board_is_icev2()) {
 814                 writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
 815                 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
 816                 cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RMII;
 817                 cpsw_slaves[0].phy_addr = 1;
 818                 cpsw_slaves[1].phy_addr = 3;
 819         } else {
 820                 writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
 821                 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
 822                                 PHY_INTERFACE_MODE_RGMII;
 823         }
 824
 825         rv = cpsw_register(&cpsw_data);
 826         if (rv < 0)
 827                 printf("Error %d registering CPSW switch\n", rv);
 828         else
 829                 n += rv;
 830 #endif
 831
 832         /*
 833          *
 834          * CPSW RGMII Internal Delay Mode is not supported in all PVT
 835          * operating points.  So we must set the TX clock delay feature
 836          * in the AR8051 PHY.  Since we only support a single ethernet
 837          * device in U-Boot, we only do this for the first instance.
 838          */
 839 #define AR8051_PHY_DEBUG_ADDR_REG       0x1d
 840 #define AR8051_PHY_DEBUG_DATA_REG       0x1e
 841 #define AR8051_DEBUG_RGMII_CLK_DLY_REG  0x5
 842 #define AR8051_RGMII_TX_CLK_DLY         0x100
 843
 844         if (board_is_evm_sk() || board_is_gp_evm()) {
 845                 const char *devname;
 846                 devname = miiphy_get_current_dev();
 847
 848                 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
 849                                 AR8051_DEBUG_RGMII_CLK_DLY_REG);
 850                 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
 851                                 AR8051_RGMII_TX_CLK_DLY);
 852         }
 853 #endif
 854 #if defined(CONFIG_USB_ETHER) && \
 855         (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
 856         if (is_valid_ethaddr(mac_addr))
 857                 eth_setenv_enetaddr("usbnet_devaddr", mac_addr);
 858
 859         rv = usb_eth_initialize(bis);
 860         if (rv < 0)
 861                 printf("Error %d registering USB_ETHER\n", rv);
 862         else
 863                 n += rv;
 864 #endif
 865         return n;
 866 }
 867 #endif
 868
 869 #endif /* CONFIG_DM_ETH */
 870
 871 #ifdef CONFIG_SPL_LOAD_FIT
 872 int board_fit_config_name_match(const char *name)
 873 {
 874         if (board_is_gp_evm() && !strcmp(name, "am335x-evm"))
 875                 return 0;
 876         else if (board_is_bone() && !strcmp(name, "am335x-bone"))
 877                 return 0;
 878         else if (board_is_bone_lt() && !strcmp(name, "am335x-boneblack"))
 879                 return 0;
 880         else if (board_is_evm_sk() && !strcmp(name, "am335x-evmsk"))
 881                 return 0;
 882         else if (board_is_bbg1() && !strcmp(name, "am335x-bonegreen"))
 883                 return 0;
 884         else if (board_is_icev2() && !strcmp(name, "am335x-icev2"))
 885                 return 0;
 886         else
 887                 return -1;
 888 }
 889 #endif
 890
 891 #ifdef CONFIG_TI_SECURE_DEVICE
 892 void board_fit_image_post_process(void **p_image, size_t *p_size)
 893 {
 894         secure_boot_verify_image(p_image, p_size);
 895 }
 896 #endif
 897
 898 #if !CONFIG_IS_ENABLED(OF_CONTROL)
 899 static const struct omap_hsmmc_plat am335x_mmc0_platdata = {
 900         .base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE,
 901         .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_4BIT,
 902         .cfg.f_min = 400000,
 903         .cfg.f_max = 52000000,
 904         .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195,
 905         .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
 906 };
 907
 908 U_BOOT_DEVICE(am335x_mmc0) = {
 909         .name = "omap_hsmmc",
 910         .platdata = &am335x_mmc0_platdata,
 911 };
 912
 913 static const struct omap_hsmmc_plat am335x_mmc1_platdata = {
 914         .base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE,
 915         .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_8BIT,
 916         .cfg.f_min = 400000,
 917         .cfg.f_max = 52000000,
 918         .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195,
 919         .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
 920 };
 921
 922 U_BOOT_DEVICE(am335x_mmc1) = {
 923         .name = "omap_hsmmc",
 924         .platdata = &am335x_mmc1_platdata,
 925 };
 926 #endif