board/ti/am335x/board.c

   1 /*
   2  * board.c
   3  *
   4  * Board functions for TI AM335X based boards
   5  *
   6  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <dm.h>
  13 #include <errno.h>
  14 #include <spl.h>
  15 #include <serial.h>
  16 #include <asm/arch/cpu.h>
  17 #include <asm/arch/hardware.h>
  18 #include <asm/arch/omap.h>
  19 #include <asm/arch/ddr_defs.h>
  20 #include <asm/arch/clock.h>
  21 #include <asm/arch/clk_synthesizer.h>
  22 #include <asm/arch/gpio.h>
  23 #include <asm/arch/mmc_host_def.h>
  24 #include <asm/arch/sys_proto.h>
  25 #include <asm/arch/mem.h>
  26 #include <asm/io.h>
  27 #include <asm/emif.h>
  28 #include <asm/gpio.h>
  29 #include <asm/omap_common.h>
  30 #include <asm/omap_sec_common.h>
  31 #include <asm/omap_mmc.h>
  32 #include <i2c.h>
  33 #include <miiphy.h>
  34 #include <cpsw.h>
  35 #include <power/tps65217.h>
  36 #include <power/tps65910.h>
  37 #include <environment.h>
  38 #include <watchdog.h>
  39 #include <environment.h>
  40 #include "../common/board_detect.h"
  41 #include "board.h"
  42
  43 DECLARE_GLOBAL_DATA_PTR;
  44
  45 /* GPIO that controls power to DDR on EVM-SK */
  46 #define GPIO_TO_PIN(bank, gpio)         (32 * (bank) + (gpio))
  47 #define GPIO_DDR_VTT_EN         GPIO_TO_PIN(0, 7)
  48 #define ICE_GPIO_DDR_VTT_EN     GPIO_TO_PIN(0, 18)
  49 #define GPIO_PR1_MII_CTRL       GPIO_TO_PIN(3, 4)
  50 #define GPIO_MUX_MII_CTRL       GPIO_TO_PIN(3, 10)
  51 #define GPIO_FET_SWITCH_CTRL    GPIO_TO_PIN(0, 7)
  52 #define GPIO_PHY_RESET          GPIO_TO_PIN(2, 5)
  53 #define GPIO_ETH0_MODE          GPIO_TO_PIN(0, 11)
  54 #define GPIO_ETH1_MODE          GPIO_TO_PIN(1, 26)
  55
  56 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  57
  58 #define GPIO0_RISINGDETECT      (AM33XX_GPIO0_BASE + OMAP_GPIO_RISINGDETECT)
  59 #define GPIO1_RISINGDETECT      (AM33XX_GPIO1_BASE + OMAP_GPIO_RISINGDETECT)
  60
  61 #define GPIO0_IRQSTATUS1        (AM33XX_GPIO0_BASE + OMAP_GPIO_IRQSTATUS1)
  62 #define GPIO1_IRQSTATUS1        (AM33XX_GPIO1_BASE + OMAP_GPIO_IRQSTATUS1)
  63
  64 #define GPIO0_IRQSTATUSRAW      (AM33XX_GPIO0_BASE + 0x024)
  65 #define GPIO1_IRQSTATUSRAW      (AM33XX_GPIO1_BASE + 0x024)
  66
  67 /*
  68  * Read header information from EEPROM into global structure.
  69  */
  70 #ifdef CONFIG_TI_I2C_BOARD_DETECT
  71 void do_board_detect(void)
  72 {
  73         enable_i2c0_pin_mux();
  74         i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
  75
  76         if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
  77                                  CONFIG_EEPROM_CHIP_ADDRESS))
  78                 printf("ti_i2c_eeprom_init failed\n");
  79 }
  80 #endif
  81
  82 #ifndef CONFIG_DM_SERIAL
  83 struct serial_device *default_serial_console(void)
  84 {
  85         if (board_is_icev2())
  86                 return &eserial4_device;
  87         else
  88                 return &eserial1_device;
  89 }
  90 #endif
  91
  92 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  93 static const struct ddr_data ddr2_data = {
  94         .datardsratio0 = MT47H128M16RT25E_RD_DQS,
  95         .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
  96         .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
  97 };
  98
  99 static const struct cmd_control ddr2_cmd_ctrl_data = {
 100         .cmd0csratio = MT47H128M16RT25E_RATIO,
 101
 102         .cmd1csratio = MT47H128M16RT25E_RATIO,
 103
 104         .cmd2csratio = MT47H128M16RT25E_RATIO,
 105 };
 106
 107 static const struct emif_regs ddr2_emif_reg_data = {
 108         .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
 109         .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
 110         .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
 111         .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
 112         .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
 113         .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
 114 };
 115
 116 static const struct emif_regs ddr2_evm_emif_reg_data = {
 117         .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
 118         .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
 119         .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
 120         .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
 121         .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
 122         .ocp_config = EMIF_OCP_CONFIG_AM335X_EVM,
 123         .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
 124 };
 125
 126 static const struct ddr_data ddr3_data = {
 127         .datardsratio0 = MT41J128MJT125_RD_DQS,
 128         .datawdsratio0 = MT41J128MJT125_WR_DQS,
 129         .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
 130         .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
 131 };
 132
 133 static const struct ddr_data ddr3_beagleblack_data = {
 134         .datardsratio0 = MT41K256M16HA125E_RD_DQS,
 135         .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
 136         .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
 137         .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
 138 };
 139
 140 static const struct ddr_data ddr3_evm_data = {
 141         .datardsratio0 = MT41J512M8RH125_RD_DQS,
 142         .datawdsratio0 = MT41J512M8RH125_WR_DQS,
 143         .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
 144         .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
 145 };
 146
 147 static const struct ddr_data ddr3_icev2_data = {
 148         .datardsratio0 = MT41J128MJT125_RD_DQS_400MHz,
 149         .datawdsratio0 = MT41J128MJT125_WR_DQS_400MHz,
 150         .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE_400MHz,
 151         .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA_400MHz,
 152 };
 153
 154 static const struct cmd_control ddr3_cmd_ctrl_data = {
 155         .cmd0csratio = MT41J128MJT125_RATIO,
 156         .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
 157
 158         .cmd1csratio = MT41J128MJT125_RATIO,
 159         .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
 160
 161         .cmd2csratio = MT41J128MJT125_RATIO,
 162         .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
 163 };
 164
 165 static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
 166         .cmd0csratio = MT41K256M16HA125E_RATIO,
 167         .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 168
 169         .cmd1csratio = MT41K256M16HA125E_RATIO,
 170         .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 171
 172         .cmd2csratio = MT41K256M16HA125E_RATIO,
 173         .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 174 };
 175
 176 static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
 177         .cmd0csratio = MT41J512M8RH125_RATIO,
 178         .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,
 179
 180         .cmd1csratio = MT41J512M8RH125_RATIO,
 181         .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,
 182
 183         .cmd2csratio = MT41J512M8RH125_RATIO,
 184         .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
 185 };
 186
 187 static const struct cmd_control ddr3_icev2_cmd_ctrl_data = {
 188         .cmd0csratio = MT41J128MJT125_RATIO_400MHz,
 189         .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
 190
 191         .cmd1csratio = MT41J128MJT125_RATIO_400MHz,
 192         .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
 193
 194         .cmd2csratio = MT41J128MJT125_RATIO_400MHz,
 195         .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
 196 };
 197
 198 static struct emif_regs ddr3_emif_reg_data = {
 199         .sdram_config = MT41J128MJT125_EMIF_SDCFG,
 200         .ref_ctrl = MT41J128MJT125_EMIF_SDREF,
 201         .sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
 202         .sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
 203         .sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
 204         .zq_config = MT41J128MJT125_ZQ_CFG,
 205         .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
 206                                 PHY_EN_DYN_PWRDN,
 207 };
 208
 209 static struct emif_regs ddr3_beagleblack_emif_reg_data = {
 210         .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
 211         .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
 212         .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
 213         .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
 214         .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
 215         .ocp_config = EMIF_OCP_CONFIG_BEAGLEBONE_BLACK,
 216         .zq_config = MT41K256M16HA125E_ZQ_CFG,
 217         .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
 218 };
 219
 220 static struct emif_regs ddr3_evm_emif_reg_data = {
 221         .sdram_config = MT41J512M8RH125_EMIF_SDCFG,
 222         .ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
 223         .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
 224         .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
 225         .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
 226         .ocp_config = EMIF_OCP_CONFIG_AM335X_EVM,
 227         .zq_config = MT41J512M8RH125_ZQ_CFG,
 228         .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
 229                                 PHY_EN_DYN_PWRDN,
 230 };
 231
 232 static struct emif_regs ddr3_icev2_emif_reg_data = {
 233         .sdram_config = MT41J128MJT125_EMIF_SDCFG_400MHz,
 234         .ref_ctrl = MT41J128MJT125_EMIF_SDREF_400MHz,
 235         .sdram_tim1 = MT41J128MJT125_EMIF_TIM1_400MHz,
 236         .sdram_tim2 = MT41J128MJT125_EMIF_TIM2_400MHz,
 237         .sdram_tim3 = MT41J128MJT125_EMIF_TIM3_400MHz,
 238         .zq_config = MT41J128MJT125_ZQ_CFG_400MHz,
 239         .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY_400MHz |
 240                                 PHY_EN_DYN_PWRDN,
 241 };
 242
 243 #ifdef CONFIG_SPL_OS_BOOT
 244 int spl_start_uboot(void)
 245 {
 246         /* break into full u-boot on 'c' */
 247         if (serial_tstc() && serial_getc() == 'c')
 248                 return 1;
 249
 250 #ifdef CONFIG_SPL_ENV_SUPPORT
 251         env_init();
 252         env_relocate_spec();
 253         if (getenv_yesno("boot_os") != 1)
 254                 return 1;
 255 #endif
 256
 257         return 0;
 258 }
 259 #endif
 260
 261 const struct dpll_params *get_dpll_ddr_params(void)
 262 {
 263         int ind = get_sys_clk_index();
 264
 265         if (board_is_evm_sk())
 266                 return &dpll_ddr3_303MHz[ind];
 267         else if (board_is_bone_lt() || board_is_icev2())
 268                 return &dpll_ddr3_400MHz[ind];
 269         else if (board_is_evm_15_or_later())
 270                 return &dpll_ddr3_303MHz[ind];
 271         else
 272                 return &dpll_ddr2_266MHz[ind];
 273 }
 274
 275 static u8 bone_not_connected_to_ac_power(void)
 276 {
 277         if (board_is_bone()) {
 278                 uchar pmic_status_reg;
 279                 if (tps65217_reg_read(TPS65217_STATUS,
 280                                       &pmic_status_reg))
 281                         return 1;
 282                 if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) {
 283                         puts("No AC power, switching to default OPP\n");
 284                         return 1;
 285                 }
 286         }
 287         return 0;
 288 }
 289
 290 const struct dpll_params *get_dpll_mpu_params(void)
 291 {
 292         int ind = get_sys_clk_index();
 293         int freq = am335x_get_efuse_mpu_max_freq(cdev);
 294
 295         if (bone_not_connected_to_ac_power())
 296                 freq = MPUPLL_M_600;
 297
 298         if (board_is_bone_lt())
 299                 freq = MPUPLL_M_1000;
 300
 301         switch (freq) {
 302         case MPUPLL_M_1000:
 303                 return &dpll_mpu_opp[ind][5];
 304         case MPUPLL_M_800:
 305                 return &dpll_mpu_opp[ind][4];
 306         case MPUPLL_M_720:
 307                 return &dpll_mpu_opp[ind][3];
 308         case MPUPLL_M_600:
 309                 return &dpll_mpu_opp[ind][2];
 310         case MPUPLL_M_500:
 311                 return &dpll_mpu_opp100;
 312         case MPUPLL_M_300:
 313                 return &dpll_mpu_opp[ind][0];
 314         }
 315
 316         return &dpll_mpu_opp[ind][0];
 317 }
 318
 319 static void scale_vcores_bone(int freq)
 320 {
 321         int usb_cur_lim, mpu_vdd;
 322
 323         /*
 324          * Only perform PMIC configurations if board rev > A1
 325          * on Beaglebone White
 326          */
 327         if (board_is_bone() && !strncmp(board_ti_get_rev(), "00A1", 4))
 328                 return;
 329
 330         if (i2c_probe(TPS65217_CHIP_PM))
 331                 return;
 332
 333         /*
 334          * On Beaglebone White we need to ensure we have AC power
 335          * before increasing the frequency.
 336          */
 337         if (bone_not_connected_to_ac_power())
 338                 freq = MPUPLL_M_600;
 339
 340         /*
 341          * Override what we have detected since we know if we have
 342          * a Beaglebone Black it supports 1GHz.
 343          */
 344         if (board_is_bone_lt())
 345                 freq = MPUPLL_M_1000;
 346
 347         if (freq == MPUPLL_M_1000) {
 348                 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
 349                 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
 350         } else {
 351                 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
 352                 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
 353         }
 354
 355         switch (freq) {
 356         case MPUPLL_M_1000:
 357                 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
 358                 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
 359                 break;
 360         case MPUPLL_M_800:
 361                 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
 362                 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
 363                 break;
 364         case MPUPLL_M_720:
 365                 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1200MV;
 366                 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
 367                 break;
 368         case MPUPLL_M_600:
 369         case MPUPLL_M_500:
 370         case MPUPLL_M_300:
 371                 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1100MV;
 372                 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
 373                 break;
 374         }
 375
 376         if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
 377                                TPS65217_POWER_PATH,
 378                                usb_cur_lim,
 379                                TPS65217_USB_INPUT_CUR_LIMIT_MASK))
 380                 puts("tps65217_reg_write failure\n");
 381
 382         /* Set DCDC3 (CORE) voltage to 1.10V */
 383         if (tps65217_voltage_update(TPS65217_DEFDCDC3,
 384                                     TPS65217_DCDC_VOLT_SEL_1100MV)) {
 385                 puts("tps65217_voltage_update failure\n");
 386                 return;
 387         }
 388
 389         /* Set DCDC2 (MPU) voltage */
 390         if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
 391                 puts("tps65217_voltage_update failure\n");
 392                 return;
 393         }
 394
 395         /*
 396          * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
 397          * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
 398          */
 399         if (board_is_bone()) {
 400                 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
 401                                        TPS65217_DEFLS1,
 402                                        TPS65217_LDO_VOLTAGE_OUT_3_3,
 403                                        TPS65217_LDO_MASK))
 404                         puts("tps65217_reg_write failure\n");
 405         } else {
 406                 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
 407                                        TPS65217_DEFLS1,
 408                                        TPS65217_LDO_VOLTAGE_OUT_1_8,
 409                                        TPS65217_LDO_MASK))
 410                         puts("tps65217_reg_write failure\n");
 411         }
 412
 413         if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
 414                                TPS65217_DEFLS2,
 415                                TPS65217_LDO_VOLTAGE_OUT_3_3,
 416                                TPS65217_LDO_MASK))
 417                 puts("tps65217_reg_write failure\n");
 418 }
 419
 420 void scale_vcores_generic(int freq)
 421 {
 422         int sil_rev, mpu_vdd;
 423
 424         /*
 425          * The GP EVM, IDK and EVM SK use a TPS65910 PMIC.  For all
 426          * MPU frequencies we support we use a CORE voltage of
 427          * 1.10V.  For MPU voltage we need to switch based on
 428          * the frequency we are running at.
 429          */
 430         if (i2c_probe(TPS65910_CTRL_I2C_ADDR))
 431                 return;
 432
 433         /*
 434          * Depending on MPU clock and PG we will need a different
 435          * VDD to drive at that speed.
 436          */
 437         sil_rev = readl(&cdev->deviceid) >> 28;
 438         mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, freq);
 439
 440         /* Tell the TPS65910 to use i2c */
 441         tps65910_set_i2c_control();
 442
 443         /* First update MPU voltage. */
 444         if (tps65910_voltage_update(MPU, mpu_vdd))
 445                 return;
 446
 447         /* Second, update the CORE voltage. */
 448         if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_0))
 449                 return;
 450
 451 }
 452
 453 void gpi2c_init(void)
 454 {
 455         /* When needed to be invoked prior to BSS initialization */
 456         static bool first_time = true;
 457
 458         if (first_time) {
 459                 enable_i2c0_pin_mux();
 460                 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
 461                          CONFIG_SYS_OMAP24_I2C_SLAVE);
 462                 first_time = false;
 463         }
 464 }
 465
 466 void scale_vcores(void)
 467 {
 468         int freq;
 469
 470         gpi2c_init();
 471         freq = am335x_get_efuse_mpu_max_freq(cdev);
 472
 473         if (board_is_bone())
 474                 scale_vcores_bone(freq);
 475         else
 476                 scale_vcores_generic(freq);
 477 }
 478
 479 void set_uart_mux_conf(void)
 480 {
 481 #if CONFIG_CONS_INDEX == 1
 482         enable_uart0_pin_mux();
 483 #elif CONFIG_CONS_INDEX == 2
 484         enable_uart1_pin_mux();
 485 #elif CONFIG_CONS_INDEX == 3
 486         enable_uart2_pin_mux();
 487 #elif CONFIG_CONS_INDEX == 4
 488         enable_uart3_pin_mux();
 489 #elif CONFIG_CONS_INDEX == 5
 490         enable_uart4_pin_mux();
 491 #elif CONFIG_CONS_INDEX == 6
 492         enable_uart5_pin_mux();
 493 #endif
 494 }
 495
 496 void set_mux_conf_regs(void)
 497 {
 498         enable_board_pin_mux();
 499 }
 500
 501 const struct ctrl_ioregs ioregs_evmsk = {
 502         .cm0ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 503         .cm1ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 504         .cm2ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 505         .dt0ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 506         .dt1ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 507 };
 508
 509 const struct ctrl_ioregs ioregs_bonelt = {
 510         .cm0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 511         .cm1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 512         .cm2ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 513         .dt0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 514         .dt1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 515 };
 516
 517 const struct ctrl_ioregs ioregs_evm15 = {
 518         .cm0ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 519         .cm1ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 520         .cm2ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 521         .dt0ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 522         .dt1ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 523 };
 524
 525 const struct ctrl_ioregs ioregs = {
 526         .cm0ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 527         .cm1ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 528         .cm2ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 529         .dt0ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 530         .dt1ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 531 };
 532
 533 void sdram_init(void)
 534 {
 535         if (board_is_evm_sk()) {
 536                 /*
 537                  * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
 538                  * This is safe enough to do on older revs.
 539                  */
 540                 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
 541                 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
 542         }
 543
 544         if (board_is_icev2()) {
 545                 gpio_request(ICE_GPIO_DDR_VTT_EN, "ddr_vtt_en");
 546                 gpio_direction_output(ICE_GPIO_DDR_VTT_EN, 1);
 547         }
 548
 549         if (board_is_evm_sk())
 550                 config_ddr(303, &ioregs_evmsk, &ddr3_data,
 551                            &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
 552         else if (board_is_bone_lt())
 553                 config_ddr(400, &ioregs_bonelt,
 554                            &ddr3_beagleblack_data,
 555                            &ddr3_beagleblack_cmd_ctrl_data,
 556                            &ddr3_beagleblack_emif_reg_data, 0);
 557         else if (board_is_evm_15_or_later())
 558                 config_ddr(303, &ioregs_evm15, &ddr3_evm_data,
 559                            &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
 560         else if (board_is_icev2())
 561                 config_ddr(400, &ioregs_evmsk, &ddr3_icev2_data,
 562                            &ddr3_icev2_cmd_ctrl_data, &ddr3_icev2_emif_reg_data,
 563                            0);
 564         else if (board_is_gp_evm())
 565                 config_ddr(266, &ioregs, &ddr2_data,
 566                            &ddr2_cmd_ctrl_data, &ddr2_evm_emif_reg_data, 0);
 567         else
 568                 config_ddr(266, &ioregs, &ddr2_data,
 569                            &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
 570 }
 571 #endif
 572
 573 #if !defined(CONFIG_SPL_BUILD) || \
 574         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 575 static void request_and_set_gpio(int gpio, char *name, int val)
 576 {
 577         int ret;
 578
 579         ret = gpio_request(gpio, name);
 580         if (ret < 0) {
 581                 printf("%s: Unable to request %s\n", __func__, name);
 582                 return;
 583         }
 584
 585         ret = gpio_direction_output(gpio, 0);
 586         if (ret < 0) {
 587                 printf("%s: Unable to set %s  as output\n", __func__, name);
 588                 goto err_free_gpio;
 589         }
 590
 591         gpio_set_value(gpio, val);
 592
 593         return;
 594
 595 err_free_gpio:
 596         gpio_free(gpio);
 597 }
 598
 599 #define REQUEST_AND_SET_GPIO(N) request_and_set_gpio(N, #N, 1);
 600 #define REQUEST_AND_CLR_GPIO(N) request_and_set_gpio(N, #N, 0);
 601
 602 /**
 603  * RMII mode on ICEv2 board needs 50MHz clock. Given the clock
 604  * synthesizer With a capacitor of 18pF, and 25MHz input clock cycle
 605  * PLL1 gives an output of 100MHz. So, configuring the div2/3 as 2 to
 606  * give 50MHz output for Eth0 and 1.
 607  */
 608 static struct clk_synth cdce913_data = {
 609         .id = 0x81,
 610         .capacitor = 0x90,
 611         .mux = 0x6d,
 612         .pdiv2 = 0x2,
 613         .pdiv3 = 0x2,
 614 };
 615 #endif
 616
 617 /*
 618  * Basic board specific setup.  Pinmux has been handled already.
 619  */
 620 int board_init(void)
 621 {
 622 #if defined(CONFIG_HW_WATCHDOG)
 623         hw_watchdog_init();
 624 #endif
 625
 626         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 627 #if defined(CONFIG_NOR) || defined(CONFIG_NAND)
 628         gpmc_init();
 629 #endif
 630
 631 #if !defined(CONFIG_SPL_BUILD) || \
 632         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 633         if (board_is_icev2()) {
 634                 int rv;
 635                 u32 reg;
 636
 637                 REQUEST_AND_SET_GPIO(GPIO_PR1_MII_CTRL);
 638                 /* Make J19 status available on GPIO1_26 */
 639                 REQUEST_AND_CLR_GPIO(GPIO_MUX_MII_CTRL);
 640
 641                 REQUEST_AND_SET_GPIO(GPIO_FET_SWITCH_CTRL);
 642                 /*
 643                  * Both ports can be set as RMII-CPSW or MII-PRU-ETH using
 644                  * jumpers near the port. Read the jumper value and set
 645                  * the pinmux, external mux and PHY clock accordingly.
 646                  * As jumper line is overridden by PHY RX_DV pin immediately
 647                  * after bootstrap (power-up/reset), we need to sample
 648                  * it during PHY reset using GPIO rising edge detection.
 649                  */
 650                 REQUEST_AND_SET_GPIO(GPIO_PHY_RESET);
 651                 /* Enable rising edge IRQ on GPIO0_11 and GPIO 1_26 */
 652                 reg = readl(GPIO0_RISINGDETECT) | BIT(11);
 653                 writel(reg, GPIO0_RISINGDETECT);
 654                 reg = readl(GPIO1_RISINGDETECT) | BIT(26);
 655                 writel(reg, GPIO1_RISINGDETECT);
 656                 /* Reset PHYs to capture the Jumper setting */
 657                 gpio_set_value(GPIO_PHY_RESET, 0);
 658                 udelay(2);      /* PHY datasheet states 1uS min. */
 659                 gpio_set_value(GPIO_PHY_RESET, 1);
 660
 661                 reg = readl(GPIO0_IRQSTATUSRAW) & BIT(11);
 662                 if (reg) {
 663                         writel(reg, GPIO0_IRQSTATUS1); /* clear irq */
 664                         /* RMII mode */
 665                         printf("ETH0, CPSW\n");
 666                 } else {
 667                         /* MII mode */
 668                         printf("ETH0, PRU\n");
 669                         cdce913_data.pdiv3 = 4; /* 25MHz PHY clk */
 670                 }
 671
 672                 reg = readl(GPIO1_IRQSTATUSRAW) & BIT(26);
 673                 if (reg) {
 674                         writel(reg, GPIO1_IRQSTATUS1); /* clear irq */
 675                         /* RMII mode */
 676                         printf("ETH1, CPSW\n");
 677                         gpio_set_value(GPIO_MUX_MII_CTRL, 1);
 678                 } else {
 679                         /* MII mode */
 680                         printf("ETH1, PRU\n");
 681                         cdce913_data.pdiv2 = 4; /* 25MHz PHY clk */
 682                 }
 683
 684                 /* disable rising edge IRQs */
 685                 reg = readl(GPIO0_RISINGDETECT) & ~BIT(11);
 686                 writel(reg, GPIO0_RISINGDETECT);
 687                 reg = readl(GPIO1_RISINGDETECT) & ~BIT(26);
 688                 writel(reg, GPIO1_RISINGDETECT);
 689
 690                 rv = setup_clock_synthesizer(&cdce913_data);
 691                 if (rv) {
 692                         printf("Clock synthesizer setup failed %d\n", rv);
 693                         return rv;
 694                 }
 695
 696                 /* reset PHYs */
 697                 gpio_set_value(GPIO_PHY_RESET, 0);
 698                 udelay(2);      /* PHY datasheet states 1uS min. */
 699                 gpio_set_value(GPIO_PHY_RESET, 1);
 700         }
 701 #endif
 702
 703         return 0;
 704 }
 705
 706 #ifdef CONFIG_BOARD_LATE_INIT
 707 int board_late_init(void)
 708 {
 709 #if !defined(CONFIG_SPL_BUILD)
 710         uint8_t mac_addr[6];
 711         uint32_t mac_hi, mac_lo;
 712 #endif
 713
 714 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 715         char *name = NULL;
 716
 717         if (board_is_bone_lt()) {
 718                 /* BeagleBoard.org BeagleBone Black Wireless: */
 719                 if (!strncmp(board_ti_get_rev(), "BWA", 3)) {
 720                         name = "BBBW";
 721                 }
 722                 /* SeeedStudio BeagleBone Green Wireless */
 723                 if (!strncmp(board_ti_get_rev(), "GW1", 3)) {
 724                         name = "BBGW";
 725                 }
 726                 /* BeagleBoard.org BeagleBone Blue */
 727                 if (!strncmp(board_ti_get_rev(), "BLA", 3)) {
 728                         name = "BBBL";
 729                 }
 730         }
 731
 732         if (board_is_bbg1())
 733                 name = "BBG1";
 734         set_board_info_env(name);
 735
 736         /*
 737          * Default FIT boot on HS devices. Non FIT images are not allowed
 738          * on HS devices.
 739          */
 740         if (get_device_type() == HS_DEVICE)
 741                 setenv("boot_fit", "1");
 742 #endif
 743
 744 #if !defined(CONFIG_SPL_BUILD)
 745         /* try reading mac address from efuse */
 746         mac_lo = readl(&cdev->macid0l);
 747         mac_hi = readl(&cdev->macid0h);
 748         mac_addr[0] = mac_hi & 0xFF;
 749         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 750         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 751         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 752         mac_addr[4] = mac_lo & 0xFF;
 753         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 754
 755         if (!getenv("ethaddr")) {
 756                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
 757
 758                 if (is_valid_ethaddr(mac_addr))
 759                         eth_setenv_enetaddr("ethaddr", mac_addr);
 760         }
 761
 762         mac_lo = readl(&cdev->macid1l);
 763         mac_hi = readl(&cdev->macid1h);
 764         mac_addr[0] = mac_hi & 0xFF;
 765         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 766         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 767         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 768         mac_addr[4] = mac_lo & 0xFF;
 769         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 770
 771         if (!getenv("eth1addr")) {
 772                 if (is_valid_ethaddr(mac_addr))
 773                         eth_setenv_enetaddr("eth1addr", mac_addr);
 774         }
 775 #endif
 776
 777         return 0;
 778 }
 779 #endif
 780
 781 #ifndef CONFIG_DM_ETH
 782
 783 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
 784         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 785 static void cpsw_control(int enabled)
 786 {
 787         /* VTP can be added here */
 788
 789         return;
 790 }
 791
 792 static struct cpsw_slave_data cpsw_slaves[] = {
 793         {
 794                 .slave_reg_ofs  = 0x208,
 795                 .sliver_reg_ofs = 0xd80,
 796                 .phy_addr       = 0,
 797         },
 798         {
 799                 .slave_reg_ofs  = 0x308,
 800                 .sliver_reg_ofs = 0xdc0,
 801                 .phy_addr       = 1,
 802         },
 803 };
 804
 805 static struct cpsw_platform_data cpsw_data = {
 806         .mdio_base              = CPSW_MDIO_BASE,
 807         .cpsw_base              = CPSW_BASE,
 808         .mdio_div               = 0xff,
 809         .channels               = 8,
 810         .cpdma_reg_ofs          = 0x800,
 811         .slaves                 = 1,
 812         .slave_data             = cpsw_slaves,
 813         .ale_reg_ofs            = 0xd00,
 814         .ale_entries            = 1024,
 815         .host_port_reg_ofs      = 0x108,
 816         .hw_stats_reg_ofs       = 0x900,
 817         .bd_ram_ofs             = 0x2000,
 818         .mac_control            = (1 << 5),
 819         .control                = cpsw_control,
 820         .host_port_num          = 0,
 821         .version                = CPSW_CTRL_VERSION_2,
 822 };
 823 #endif
 824
 825 #if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) &&\
 826         defined(CONFIG_SPL_BUILD)) || \
 827         ((defined(CONFIG_DRIVER_TI_CPSW) || \
 828           defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \
 829          !defined(CONFIG_SPL_BUILD))
 830
 831 /*
 832  * This function will:
 833  * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
 834  * in the environment
 835  * Perform fixups to the PHY present on certain boards.  We only need this
 836  * function in:
 837  * - SPL with either CPSW or USB ethernet support
 838  * - Full U-Boot, with either CPSW or USB ethernet
 839  * Build in only these cases to avoid warnings about unused variables
 840  * when we build an SPL that has neither option but full U-Boot will.
 841  */
 842 int board_eth_init(bd_t *bis)
 843 {
 844         int rv, n = 0;
 845 #if defined(CONFIG_USB_ETHER) && \
 846         (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
 847         uint8_t mac_addr[6];
 848         uint32_t mac_hi, mac_lo;
 849
 850         /*
 851          * use efuse mac address for USB ethernet as we know that
 852          * both CPSW and USB ethernet will never be active at the same time
 853          */
 854         mac_lo = readl(&cdev->macid0l);
 855         mac_hi = readl(&cdev->macid0h);
 856         mac_addr[0] = mac_hi & 0xFF;
 857         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 858         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 859         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 860         mac_addr[4] = mac_lo & 0xFF;
 861         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 862 #endif
 863
 864
 865 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
 866         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 867
 868 #ifdef CONFIG_DRIVER_TI_CPSW
 869         if (board_is_bone() || board_is_bone_lt() ||
 870             board_is_idk()) {
 871                 writel(MII_MODE_ENABLE, &cdev->miisel);
 872                 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
 873                                 PHY_INTERFACE_MODE_MII;
 874         } else if (board_is_icev2()) {
 875                 writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
 876                 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
 877                 cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RMII;
 878                 cpsw_slaves[0].phy_addr = 1;
 879                 cpsw_slaves[1].phy_addr = 3;
 880         } else {
 881                 writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
 882                 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
 883                                 PHY_INTERFACE_MODE_RGMII;
 884         }
 885
 886         rv = cpsw_register(&cpsw_data);
 887         if (rv < 0)
 888                 printf("Error %d registering CPSW switch\n", rv);
 889         else
 890                 n += rv;
 891 #endif
 892
 893         /*
 894          *
 895          * CPSW RGMII Internal Delay Mode is not supported in all PVT
 896          * operating points.  So we must set the TX clock delay feature
 897          * in the AR8051 PHY.  Since we only support a single ethernet
 898          * device in U-Boot, we only do this for the first instance.
 899          */
 900 #define AR8051_PHY_DEBUG_ADDR_REG       0x1d
 901 #define AR8051_PHY_DEBUG_DATA_REG       0x1e
 902 #define AR8051_DEBUG_RGMII_CLK_DLY_REG  0x5
 903 #define AR8051_RGMII_TX_CLK_DLY         0x100
 904
 905         if (board_is_evm_sk() || board_is_gp_evm()) {
 906                 const char *devname;
 907                 devname = miiphy_get_current_dev();
 908
 909                 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
 910                                 AR8051_DEBUG_RGMII_CLK_DLY_REG);
 911                 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
 912                                 AR8051_RGMII_TX_CLK_DLY);
 913         }
 914 #endif
 915 #if defined(CONFIG_USB_ETHER) && \
 916         (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
 917         if (is_valid_ethaddr(mac_addr))
 918                 eth_setenv_enetaddr("usbnet_devaddr", mac_addr);
 919
 920         rv = usb_eth_initialize(bis);
 921         if (rv < 0)
 922                 printf("Error %d registering USB_ETHER\n", rv);
 923         else
 924                 n += rv;
 925 #endif
 926         return n;
 927 }
 928 #endif
 929
 930 #endif /* CONFIG_DM_ETH */
 931
 932 #ifdef CONFIG_SPL_LOAD_FIT
 933 int board_fit_config_name_match(const char *name)
 934 {
 935         if (board_is_gp_evm() && !strcmp(name, "am335x-evm"))
 936                 return 0;
 937         else if (board_is_bone() && !strcmp(name, "am335x-bone"))
 938                 return 0;
 939         else if (board_is_bone_lt() && !strcmp(name, "am335x-boneblack"))
 940                 return 0;
 941         else if (board_is_evm_sk() && !strcmp(name, "am335x-evmsk"))
 942                 return 0;
 943         else if (board_is_bbg1() && !strcmp(name, "am335x-bonegreen"))
 944                 return 0;
 945         else if (board_is_icev2() && !strcmp(name, "am335x-icev2"))
 946                 return 0;
 947         else
 948                 return -1;
 949 }
 950 #endif
 951
 952 #ifdef CONFIG_TI_SECURE_DEVICE
 953 void board_fit_image_post_process(void **p_image, size_t *p_size)
 954 {
 955         secure_boot_verify_image(p_image, p_size);
 956 }
 957 #endif
 958
 959 #if !CONFIG_IS_ENABLED(OF_CONTROL)
 960 static const struct omap_hsmmc_plat am335x_mmc0_platdata = {
 961         .base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE,
 962         .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_4BIT,
 963         .cfg.f_min = 400000,
 964         .cfg.f_max = 52000000,
 965         .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195,
 966         .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
 967 };
 968
 969 U_BOOT_DEVICE(am335x_mmc0) = {
 970         .name = "omap_hsmmc",
 971         .platdata = &am335x_mmc0_platdata,
 972 };
 973
 974 static const struct omap_hsmmc_plat am335x_mmc1_platdata = {
 975         .base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE,
 976         .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_8BIT,
 977         .cfg.f_min = 400000,
 978         .cfg.f_max = 52000000,
 979         .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195,
 980         .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
 981 };
 982
 983 U_BOOT_DEVICE(am335x_mmc1) = {
 984         .name = "omap_hsmmc",
 985         .platdata = &am335x_mmc1_platdata,
 986 };
 987 #endif