board/ti/am335x/board.c

   1 /*
   2  * board.c
   3  *
   4  * Board functions for TI AM335X based boards
   5  *
   6  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <common.h>
  20 #include <errno.h>
  21 #include <spl.h>
  22 #include <asm/arch/cpu.h>
  23 #include <asm/arch/hardware.h>
  24 #include <asm/arch/omap.h>
  25 #include <asm/arch/ddr_defs.h>
  26 #include <asm/arch/clock.h>
  27 #include <asm/arch/gpio.h>
  28 #include <asm/arch/mmc_host_def.h>
  29 #include <asm/arch/sys_proto.h>
  30 #include <asm/io.h>
  31 #include <asm/emif.h>
  32 #include <asm/gpio.h>
  33 #include <i2c.h>
  34 #include <miiphy.h>
  35 #include <cpsw.h>
  36 #include "board.h"
  37
  38 DECLARE_GLOBAL_DATA_PTR;
  39
  40 static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
  41 #ifdef CONFIG_SPL_BUILD
  42 static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
  43 #endif
  44
  45 /* MII mode defines */
  46 #define MII_MODE_ENABLE         0x0
  47 #define RGMII_MODE_ENABLE       0x3A
  48
  49 /* GPIO that controls power to DDR on EVM-SK */
  50 #define GPIO_DDR_VTT_EN         7
  51
  52 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  53
  54 static struct am335x_baseboard_id __attribute__((section (".data"))) header;
  55
  56 static inline int board_is_bone(void)
  57 {
  58         return !strncmp(header.name, "A335BONE", HDR_NAME_LEN);
  59 }
  60
  61 static inline int board_is_bone_lt(void)
  62 {
  63         return !strncmp(header.name, "A335BNLT", HDR_NAME_LEN);
  64 }
  65
  66 static inline int board_is_evm_sk(void)
  67 {
  68         return !strncmp("A335X_SK", header.name, HDR_NAME_LEN);
  69 }
  70
  71 static inline int board_is_idk(void)
  72 {
  73         return !strncmp(header.config, "SKU#02", 6);
  74 }
  75
  76 static int __maybe_unused board_is_gp_evm(void)
  77 {
  78         return !strncmp("A33515BB", header.name, 8);
  79 }
  80
  81 int board_is_evm_15_or_later(void)
  82 {
  83         return (!strncmp("A33515BB", header.name, 8) &&
  84                 strncmp("1.5", header.version, 3) <= 0);
  85 }
  86
  87 /*
  88  * Read header information from EEPROM into global structure.
  89  */
  90 static int read_eeprom(void)
  91 {
  92         /* Check if baseboard eeprom is available */
  93         if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
  94                 puts("Could not probe the EEPROM; something fundamentally "
  95                         "wrong on the I2C bus.\n");
  96                 return -ENODEV;
  97         }
  98
  99         /* read the eeprom using i2c */
 100         if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header,
 101                                                         sizeof(header))) {
 102                 puts("Could not read the EEPROM; something fundamentally"
 103                         " wrong on the I2C bus.\n");
 104                 return -EIO;
 105         }
 106
 107         if (header.magic != 0xEE3355AA) {
 108                 /*
 109                  * read the eeprom using i2c again,
 110                  * but use only a 1 byte address
 111                  */
 112                 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1,
 113                                         (uchar *)&header, sizeof(header))) {
 114                         puts("Could not read the EEPROM; something "
 115                                 "fundamentally wrong on the I2C bus.\n");
 116                         return -EIO;
 117                 }
 118
 119                 if (header.magic != 0xEE3355AA) {
 120                         printf("Incorrect magic number (0x%x) in EEPROM\n",
 121                                         header.magic);
 122                         return -EINVAL;
 123                 }
 124         }
 125
 126         return 0;
 127 }
 128
 129 /* UART Defines */
 130 #ifdef CONFIG_SPL_BUILD
 131 #define UART_RESET              (0x1 << 1)
 132 #define UART_CLK_RUNNING_MASK   0x1
 133 #define UART_SMART_IDLE_EN      (0x1 << 0x3)
 134
 135 static const struct ddr_data ddr2_data = {
 136         .datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) |
 137                           (MT47H128M16RT25E_RD_DQS<<20) |
 138                           (MT47H128M16RT25E_RD_DQS<<10) |
 139                           (MT47H128M16RT25E_RD_DQS<<0)),
 140         .datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) |
 141                           (MT47H128M16RT25E_WR_DQS<<20) |
 142                           (MT47H128M16RT25E_WR_DQS<<10) |
 143                           (MT47H128M16RT25E_WR_DQS<<0)),
 144         .datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) |
 145                          (MT47H128M16RT25E_PHY_WRLVL<<20) |
 146                          (MT47H128M16RT25E_PHY_WRLVL<<10) |
 147                          (MT47H128M16RT25E_PHY_WRLVL<<0)),
 148         .datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) |
 149                          (MT47H128M16RT25E_PHY_GATELVL<<20) |
 150                          (MT47H128M16RT25E_PHY_GATELVL<<10) |
 151                          (MT47H128M16RT25E_PHY_GATELVL<<0)),
 152         .datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) |
 153                           (MT47H128M16RT25E_PHY_FIFO_WE<<20) |
 154                           (MT47H128M16RT25E_PHY_FIFO_WE<<10) |
 155                           (MT47H128M16RT25E_PHY_FIFO_WE<<0)),
 156         .datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) |
 157                           (MT47H128M16RT25E_PHY_WR_DATA<<20) |
 158                           (MT47H128M16RT25E_PHY_WR_DATA<<10) |
 159                           (MT47H128M16RT25E_PHY_WR_DATA<<0)),
 160         .datauserank0delay = MT47H128M16RT25E_PHY_RANK0_DELAY,
 161         .datadldiff0 = PHY_DLL_LOCK_DIFF,
 162 };
 163
 164 static const struct cmd_control ddr2_cmd_ctrl_data = {
 165         .cmd0csratio = MT47H128M16RT25E_RATIO,
 166         .cmd0dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
 167         .cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
 168
 169         .cmd1csratio = MT47H128M16RT25E_RATIO,
 170         .cmd1dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
 171         .cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
 172
 173         .cmd2csratio = MT47H128M16RT25E_RATIO,
 174         .cmd2dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
 175         .cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
 176 };
 177
 178 static const struct emif_regs ddr2_emif_reg_data = {
 179         .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
 180         .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
 181         .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
 182         .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
 183         .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
 184         .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
 185 };
 186
 187 static const struct ddr_data ddr3_data = {
 188         .datardsratio0 = MT41J128MJT125_RD_DQS,
 189         .datawdsratio0 = MT41J128MJT125_WR_DQS,
 190         .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
 191         .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
 192         .datadldiff0 = PHY_DLL_LOCK_DIFF,
 193 };
 194
 195 static const struct ddr_data ddr3_beagleblack_data = {
 196         .datardsratio0 = MT41K256M16HA125E_RD_DQS,
 197         .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
 198         .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
 199         .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
 200         .datadldiff0 = PHY_DLL_LOCK_DIFF,
 201 };
 202
 203 static const struct ddr_data ddr3_evm_data = {
 204         .datardsratio0 = MT41J512M8RH125_RD_DQS,
 205         .datawdsratio0 = MT41J512M8RH125_WR_DQS,
 206         .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
 207         .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
 208         .datadldiff0 = PHY_DLL_LOCK_DIFF,
 209 };
 210
 211 static const struct cmd_control ddr3_cmd_ctrl_data = {
 212         .cmd0csratio = MT41J128MJT125_RATIO,
 213         .cmd0dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
 214         .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
 215
 216         .cmd1csratio = MT41J128MJT125_RATIO,
 217         .cmd1dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
 218         .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
 219
 220         .cmd2csratio = MT41J128MJT125_RATIO,
 221         .cmd2dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
 222         .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
 223 };
 224
 225 static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
 226         .cmd0csratio = MT41K256M16HA125E_RATIO,
 227         .cmd0dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
 228         .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 229
 230         .cmd1csratio = MT41K256M16HA125E_RATIO,
 231         .cmd1dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
 232         .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 233
 234         .cmd2csratio = MT41K256M16HA125E_RATIO,
 235         .cmd2dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
 236         .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 237 };
 238
 239 static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
 240         .cmd0csratio = MT41J512M8RH125_RATIO,
 241         .cmd0dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
 242         .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,
 243
 244         .cmd1csratio = MT41J512M8RH125_RATIO,
 245         .cmd1dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
 246         .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,
 247
 248         .cmd2csratio = MT41J512M8RH125_RATIO,
 249         .cmd2dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
 250         .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
 251 };
 252
 253 static struct emif_regs ddr3_emif_reg_data = {
 254         .sdram_config = MT41J128MJT125_EMIF_SDCFG,
 255         .ref_ctrl = MT41J128MJT125_EMIF_SDREF,
 256         .sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
 257         .sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
 258         .sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
 259         .zq_config = MT41J128MJT125_ZQ_CFG,
 260         .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
 261                                 PHY_EN_DYN_PWRDN,
 262 };
 263
 264 static struct emif_regs ddr3_beagleblack_emif_reg_data = {
 265         .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
 266         .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
 267         .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
 268         .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
 269         .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
 270         .zq_config = MT41K256M16HA125E_ZQ_CFG,
 271         .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
 272 };
 273
 274 static struct emif_regs ddr3_evm_emif_reg_data = {
 275         .sdram_config = MT41J512M8RH125_EMIF_SDCFG,
 276         .ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
 277         .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
 278         .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
 279         .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
 280         .zq_config = MT41J512M8RH125_ZQ_CFG,
 281         .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
 282                                 PHY_EN_DYN_PWRDN,
 283 };
 284 #endif
 285
 286 /*
 287  * early system init of muxing and clocks.
 288  */
 289 void s_init(void)
 290 {
 291         /*
 292          * Save the boot parameters passed from romcode.
 293          * We cannot delay the saving further than this,
 294          * to prevent overwrites.
 295          */
 296 #ifdef CONFIG_SPL_BUILD
 297         save_omap_boot_params();
 298 #endif
 299
 300         /* WDT1 is already running when the bootloader gets control
 301          * Disable it to avoid "random" resets
 302          */
 303         writel(0xAAAA, &wdtimer->wdtwspr);
 304         while (readl(&wdtimer->wdtwwps) != 0x0)
 305                 ;
 306         writel(0x5555, &wdtimer->wdtwspr);
 307         while (readl(&wdtimer->wdtwwps) != 0x0)
 308                 ;
 309
 310 #ifdef CONFIG_SPL_BUILD
 311         /* Setup the PLLs and the clocks for the peripherals */
 312         pll_init();
 313
 314         /* Enable RTC32K clock */
 315         rtc32k_enable();
 316
 317         /* UART softreset */
 318         u32 regVal;
 319
 320 #ifdef CONFIG_SERIAL1
 321         enable_uart0_pin_mux();
 322 #endif /* CONFIG_SERIAL1 */
 323 #ifdef CONFIG_SERIAL2
 324         enable_uart1_pin_mux();
 325 #endif /* CONFIG_SERIAL2 */
 326 #ifdef CONFIG_SERIAL3
 327         enable_uart2_pin_mux();
 328 #endif /* CONFIG_SERIAL3 */
 329 #ifdef CONFIG_SERIAL4
 330         enable_uart3_pin_mux();
 331 #endif /* CONFIG_SERIAL4 */
 332 #ifdef CONFIG_SERIAL5
 333         enable_uart4_pin_mux();
 334 #endif /* CONFIG_SERIAL5 */
 335 #ifdef CONFIG_SERIAL6
 336         enable_uart5_pin_mux();
 337 #endif /* CONFIG_SERIAL6 */
 338
 339         regVal = readl(&uart_base->uartsyscfg);
 340         regVal |= UART_RESET;
 341         writel(regVal, &uart_base->uartsyscfg);
 342         while ((readl(&uart_base->uartsyssts) &
 343                 UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
 344                 ;
 345
 346         /* Disable smart idle */
 347         regVal = readl(&uart_base->uartsyscfg);
 348         regVal |= UART_SMART_IDLE_EN;
 349         writel(regVal, &uart_base->uartsyscfg);
 350
 351         gd = &gdata;
 352
 353         preloader_console_init();
 354
 355         /* Initalize the board header */
 356         enable_i2c0_pin_mux();
 357         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 358         if (read_eeprom() < 0)
 359                 puts("Could not get board ID.\n");
 360
 361         enable_board_pin_mux(&header);
 362         if (board_is_evm_sk()) {
 363                 /*
 364                  * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
 365                  * This is safe enough to do on older revs.
 366                  */
 367                 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
 368                 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
 369         }
 370
 371         if (board_is_evm_sk())
 372                 config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data,
 373                            &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
 374         else if (board_is_bone_lt())
 375                 config_ddr(400, MT41K256M16HA125E_IOCTRL_VALUE,
 376                            &ddr3_beagleblack_data,
 377                            &ddr3_beagleblack_cmd_ctrl_data,
 378                            &ddr3_beagleblack_emif_reg_data, 0);
 379         else if (board_is_evm_15_or_later())
 380                 config_ddr(303, MT41J512M8RH125_IOCTRL_VALUE, &ddr3_evm_data,
 381                            &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
 382         else
 383                 config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data,
 384                            &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
 385 #endif
 386 }
 387
 388 /*
 389  * Basic board specific setup.  Pinmux has been handled already.
 390  */
 391 int board_init(void)
 392 {
 393         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 394         if (read_eeprom() < 0)
 395                 puts("Could not get board ID.\n");
 396
 397         gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
 398
 399         gpmc_init();
 400
 401         return 0;
 402 }
 403
 404 #ifdef CONFIG_BOARD_LATE_INIT
 405 int board_late_init(void)
 406 {
 407 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 408         char safe_string[HDR_NAME_LEN + 1];
 409
 410         /* Now set variables based on the header. */
 411         strncpy(safe_string, (char *)header.name, sizeof(header.name));
 412         safe_string[sizeof(header.name)] = 0;
 413         setenv("board_name", safe_string);
 414
 415         strncpy(safe_string, (char *)header.version, sizeof(header.version));
 416         safe_string[sizeof(header.version)] = 0;
 417         setenv("board_rev", safe_string);
 418 #endif
 419
 420         return 0;
 421 }
 422 #endif
 423
 424 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
 425         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 426 static void cpsw_control(int enabled)
 427 {
 428         /* VTP can be added here */
 429
 430         return;
 431 }
 432
 433 static struct cpsw_slave_data cpsw_slaves[] = {
 434         {
 435                 .slave_reg_ofs  = 0x208,
 436                 .sliver_reg_ofs = 0xd80,
 437                 .phy_id         = 0,
 438         },
 439         {
 440                 .slave_reg_ofs  = 0x308,
 441                 .sliver_reg_ofs = 0xdc0,
 442                 .phy_id         = 1,
 443         },
 444 };
 445
 446 static struct cpsw_platform_data cpsw_data = {
 447         .mdio_base              = CPSW_MDIO_BASE,
 448         .cpsw_base              = CPSW_BASE,
 449         .mdio_div               = 0xff,
 450         .channels               = 8,
 451         .cpdma_reg_ofs          = 0x800,
 452         .slaves                 = 1,
 453         .slave_data             = cpsw_slaves,
 454         .ale_reg_ofs            = 0xd00,
 455         .ale_entries            = 1024,
 456         .host_port_reg_ofs      = 0x108,
 457         .hw_stats_reg_ofs       = 0x900,
 458         .mac_control            = (1 << 5),
 459         .control                = cpsw_control,
 460         .host_port_num          = 0,
 461         .version                = CPSW_CTRL_VERSION_2,
 462 };
 463 #endif
 464
 465 #if defined(CONFIG_DRIVER_TI_CPSW) || \
 466         (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
 467 int board_eth_init(bd_t *bis)
 468 {
 469         int rv, n = 0;
 470         uint8_t mac_addr[6];
 471         uint32_t mac_hi, mac_lo;
 472
 473         /* try reading mac address from efuse */
 474         mac_lo = readl(&cdev->macid0l);
 475         mac_hi = readl(&cdev->macid0h);
 476         mac_addr[0] = mac_hi & 0xFF;
 477         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 478         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 479         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 480         mac_addr[4] = mac_lo & 0xFF;
 481         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 482
 483 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
 484         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 485         if (!getenv("ethaddr")) {
 486                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
 487
 488                 if (is_valid_ether_addr(mac_addr))
 489                         eth_setenv_enetaddr("ethaddr", mac_addr);
 490         }
 491
 492 #ifdef CONFIG_DRIVER_TI_CPSW
 493         if (board_is_bone() || board_is_bone_lt() || board_is_idk()) {
 494                 writel(MII_MODE_ENABLE, &cdev->miisel);
 495                 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
 496                                 PHY_INTERFACE_MODE_MII;
 497         } else {
 498                 writel(RGMII_MODE_ENABLE, &cdev->miisel);
 499                 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
 500                                 PHY_INTERFACE_MODE_RGMII;
 501         }
 502
 503         rv = cpsw_register(&cpsw_data);
 504         if (rv < 0)
 505                 printf("Error %d registering CPSW switch\n", rv);
 506         else
 507                 n += rv;
 508 #endif
 509
 510         /*
 511          *
 512          * CPSW RGMII Internal Delay Mode is not supported in all PVT
 513          * operating points.  So we must set the TX clock delay feature
 514          * in the AR8051 PHY.  Since we only support a single ethernet
 515          * device in U-Boot, we only do this for the first instance.
 516          */
 517 #define AR8051_PHY_DEBUG_ADDR_REG       0x1d
 518 #define AR8051_PHY_DEBUG_DATA_REG       0x1e
 519 #define AR8051_DEBUG_RGMII_CLK_DLY_REG  0x5
 520 #define AR8051_RGMII_TX_CLK_DLY         0x100
 521
 522         if (board_is_evm_sk() || board_is_gp_evm()) {
 523                 const char *devname;
 524                 devname = miiphy_get_current_dev();
 525
 526                 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
 527                                 AR8051_DEBUG_RGMII_CLK_DLY_REG);
 528                 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
 529                                 AR8051_RGMII_TX_CLK_DLY);
 530         }
 531 #endif
 532 #if defined(CONFIG_USB_ETHER) && \
 533         (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
 534         if (is_valid_ether_addr(mac_addr))
 535                 eth_setenv_enetaddr("usbnet_devaddr", mac_addr);
 536
 537         rv = usb_eth_initialize(bis);
 538         if (rv < 0)
 539                 printf("Error %d registering USB_ETHER\n", rv);
 540         else
 541                 n += rv;
 542 #endif
 543         return n;
 544 }
 545 #endif