1 // SPDX-License-Identifier: GPL-2.0+
5 * Board functions for TI AM335X based boards
7 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
20 #include <asm/arch/cpu.h>
21 #include <asm/arch/hardware.h>
22 #include <asm/arch/omap.h>
23 #include <asm/arch/ddr_defs.h>
24 #include <asm/arch/clock.h>
25 #include <asm/arch/clk_synthesizer.h>
26 #include <asm/arch/gpio.h>
27 #include <asm/arch/mmc_host_def.h>
28 #include <asm/arch/sys_proto.h>
29 #include <asm/arch/mem.h>
33 #include <asm/omap_common.h>
34 #include <asm/omap_sec_common.h>
35 #include <asm/omap_mmc.h>
39 #include <linux/bitops.h>
40 #include <linux/delay.h>
41 #include <power/tps65217.h>
42 #include <power/tps65910.h>
43 #include <env_internal.h>
45 #include "../common/board_detect.h"
48 DECLARE_GLOBAL_DATA_PTR;
50 /* GPIO that controls power to DDR on EVM-SK */
51 #define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
52 #define GPIO_DDR_VTT_EN GPIO_TO_PIN(0, 7)
53 #define ICE_GPIO_DDR_VTT_EN GPIO_TO_PIN(0, 18)
54 #define GPIO_PR1_MII_CTRL GPIO_TO_PIN(3, 4)
55 #define GPIO_MUX_MII_CTRL GPIO_TO_PIN(3, 10)
56 #define GPIO_FET_SWITCH_CTRL GPIO_TO_PIN(0, 7)
57 #define GPIO_PHY_RESET GPIO_TO_PIN(2, 5)
58 #define GPIO_ETH0_MODE GPIO_TO_PIN(0, 11)
59 #define GPIO_ETH1_MODE GPIO_TO_PIN(1, 26)
61 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
63 #define GPIO0_RISINGDETECT (AM33XX_GPIO0_BASE + OMAP_GPIO_RISINGDETECT)
64 #define GPIO1_RISINGDETECT (AM33XX_GPIO1_BASE + OMAP_GPIO_RISINGDETECT)
66 #define GPIO0_IRQSTATUS1 (AM33XX_GPIO0_BASE + OMAP_GPIO_IRQSTATUS1)
67 #define GPIO1_IRQSTATUS1 (AM33XX_GPIO1_BASE + OMAP_GPIO_IRQSTATUS1)
69 #define GPIO0_IRQSTATUSRAW (AM33XX_GPIO0_BASE + 0x024)
70 #define GPIO1_IRQSTATUSRAW (AM33XX_GPIO1_BASE + 0x024)
73 * Read header information from EEPROM into global structure.
75 #ifdef CONFIG_TI_I2C_BOARD_DETECT
76 void do_board_detect(void)
78 enable_i2c0_pin_mux();
80 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
82 if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
83 CONFIG_EEPROM_CHIP_ADDRESS))
84 printf("ti_i2c_eeprom_init failed\n");
88 #ifndef CONFIG_DM_SERIAL
89 struct serial_device *default_serial_console(void)
92 return &eserial4_device;
94 return &eserial1_device;
98 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
99 static const struct ddr_data ddr2_data = {
100 .datardsratio0 = MT47H128M16RT25E_RD_DQS,
101 .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
102 .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
105 static const struct cmd_control ddr2_cmd_ctrl_data = {
106 .cmd0csratio = MT47H128M16RT25E_RATIO,
108 .cmd1csratio = MT47H128M16RT25E_RATIO,
110 .cmd2csratio = MT47H128M16RT25E_RATIO,
113 static const struct emif_regs ddr2_emif_reg_data = {
114 .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
115 .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
116 .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
117 .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
118 .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
119 .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
122 static const struct emif_regs ddr2_evm_emif_reg_data = {
123 .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
124 .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
125 .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
126 .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
127 .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
128 .ocp_config = EMIF_OCP_CONFIG_AM335X_EVM,
129 .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
132 static const struct ddr_data ddr3_data = {
133 .datardsratio0 = MT41J128MJT125_RD_DQS,
134 .datawdsratio0 = MT41J128MJT125_WR_DQS,
135 .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
136 .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
139 static const struct ddr_data ddr3_beagleblack_data = {
140 .datardsratio0 = MT41K256M16HA125E_RD_DQS,
141 .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
142 .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
143 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
146 static const struct ddr_data ddr3_evm_data = {
147 .datardsratio0 = MT41J512M8RH125_RD_DQS,
148 .datawdsratio0 = MT41J512M8RH125_WR_DQS,
149 .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
150 .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
153 static const struct ddr_data ddr3_icev2_data = {
154 .datardsratio0 = MT41J128MJT125_RD_DQS_400MHz,
155 .datawdsratio0 = MT41J128MJT125_WR_DQS_400MHz,
156 .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE_400MHz,
157 .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA_400MHz,
160 static const struct cmd_control ddr3_cmd_ctrl_data = {
161 .cmd0csratio = MT41J128MJT125_RATIO,
162 .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
164 .cmd1csratio = MT41J128MJT125_RATIO,
165 .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
167 .cmd2csratio = MT41J128MJT125_RATIO,
168 .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
171 static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
172 .cmd0csratio = MT41K256M16HA125E_RATIO,
173 .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
175 .cmd1csratio = MT41K256M16HA125E_RATIO,
176 .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
178 .cmd2csratio = MT41K256M16HA125E_RATIO,
179 .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
182 static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
183 .cmd0csratio = MT41J512M8RH125_RATIO,
184 .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,
186 .cmd1csratio = MT41J512M8RH125_RATIO,
187 .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,
189 .cmd2csratio = MT41J512M8RH125_RATIO,
190 .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
193 static const struct cmd_control ddr3_icev2_cmd_ctrl_data = {
194 .cmd0csratio = MT41J128MJT125_RATIO_400MHz,
195 .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
197 .cmd1csratio = MT41J128MJT125_RATIO_400MHz,
198 .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
200 .cmd2csratio = MT41J128MJT125_RATIO_400MHz,
201 .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
204 static struct emif_regs ddr3_emif_reg_data = {
205 .sdram_config = MT41J128MJT125_EMIF_SDCFG,
206 .ref_ctrl = MT41J128MJT125_EMIF_SDREF,
207 .sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
208 .sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
209 .sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
210 .zq_config = MT41J128MJT125_ZQ_CFG,
211 .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
215 static struct emif_regs ddr3_beagleblack_emif_reg_data = {
216 .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
217 .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
218 .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
219 .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
220 .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
221 .ocp_config = EMIF_OCP_CONFIG_BEAGLEBONE_BLACK,
222 .zq_config = MT41K256M16HA125E_ZQ_CFG,
223 .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
226 static struct emif_regs ddr3_evm_emif_reg_data = {
227 .sdram_config = MT41J512M8RH125_EMIF_SDCFG,
228 .ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
229 .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
230 .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
231 .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
232 .ocp_config = EMIF_OCP_CONFIG_AM335X_EVM,
233 .zq_config = MT41J512M8RH125_ZQ_CFG,
234 .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
238 static struct emif_regs ddr3_icev2_emif_reg_data = {
239 .sdram_config = MT41J128MJT125_EMIF_SDCFG_400MHz,
240 .ref_ctrl = MT41J128MJT125_EMIF_SDREF_400MHz,
241 .sdram_tim1 = MT41J128MJT125_EMIF_TIM1_400MHz,
242 .sdram_tim2 = MT41J128MJT125_EMIF_TIM2_400MHz,
243 .sdram_tim3 = MT41J128MJT125_EMIF_TIM3_400MHz,
244 .zq_config = MT41J128MJT125_ZQ_CFG_400MHz,
245 .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY_400MHz |
249 #ifdef CONFIG_SPL_OS_BOOT
250 int spl_start_uboot(void)
252 #ifdef CONFIG_SPL_SERIAL_SUPPORT
253 /* break into full u-boot on 'c' */
254 if (serial_tstc() && serial_getc() == 'c')
258 #ifdef CONFIG_SPL_ENV_SUPPORT
261 if (env_get_yesno("boot_os") != 1)
269 const struct dpll_params *get_dpll_ddr_params(void)
271 int ind = get_sys_clk_index();
273 if (board_is_evm_sk())
274 return &dpll_ddr3_303MHz[ind];
275 else if (board_is_pb() || board_is_bone_lt() || board_is_icev2())
276 return &dpll_ddr3_400MHz[ind];
277 else if (board_is_evm_15_or_later())
278 return &dpll_ddr3_303MHz[ind];
280 return &dpll_ddr2_266MHz[ind];
283 static u8 bone_not_connected_to_ac_power(void)
285 if (board_is_bone()) {
286 uchar pmic_status_reg;
287 if (tps65217_reg_read(TPS65217_STATUS,
290 if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) {
291 puts("No AC power, switching to default OPP\n");
298 const struct dpll_params *get_dpll_mpu_params(void)
300 int ind = get_sys_clk_index();
301 int freq = am335x_get_efuse_mpu_max_freq(cdev);
303 if (bone_not_connected_to_ac_power())
306 if (board_is_pb() || board_is_bone_lt())
307 freq = MPUPLL_M_1000;
311 return &dpll_mpu_opp[ind][5];
313 return &dpll_mpu_opp[ind][4];
315 return &dpll_mpu_opp[ind][3];
317 return &dpll_mpu_opp[ind][2];
319 return &dpll_mpu_opp100;
321 return &dpll_mpu_opp[ind][0];
324 return &dpll_mpu_opp[ind][0];
327 static void scale_vcores_bone(int freq)
329 int usb_cur_lim, mpu_vdd;
332 * Only perform PMIC configurations if board rev > A1
333 * on Beaglebone White
335 if (board_is_bone() && !strncmp(board_ti_get_rev(), "00A1", 4))
338 #ifndef CONFIG_DM_I2C
339 if (i2c_probe(TPS65217_CHIP_PM))
342 if (power_tps65217_init(0))
348 * On Beaglebone White we need to ensure we have AC power
349 * before increasing the frequency.
351 if (bone_not_connected_to_ac_power())
355 * Override what we have detected since we know if we have
356 * a Beaglebone Black it supports 1GHz.
358 if (board_is_pb() || board_is_bone_lt())
359 freq = MPUPLL_M_1000;
363 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
364 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
367 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
368 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
371 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1200MV;
372 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
378 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1100MV;
379 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
383 if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
386 TPS65217_USB_INPUT_CUR_LIMIT_MASK))
387 puts("tps65217_reg_write failure\n");
389 /* Set DCDC3 (CORE) voltage to 1.10V */
390 if (tps65217_voltage_update(TPS65217_DEFDCDC3,
391 TPS65217_DCDC_VOLT_SEL_1100MV)) {
392 puts("tps65217_voltage_update failure\n");
396 /* Set DCDC2 (MPU) voltage */
397 if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
398 puts("tps65217_voltage_update failure\n");
403 * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
404 * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
406 if (board_is_bone()) {
407 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
409 TPS65217_LDO_VOLTAGE_OUT_3_3,
411 puts("tps65217_reg_write failure\n");
413 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
415 TPS65217_LDO_VOLTAGE_OUT_1_8,
417 puts("tps65217_reg_write failure\n");
420 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
422 TPS65217_LDO_VOLTAGE_OUT_3_3,
424 puts("tps65217_reg_write failure\n");
427 void scale_vcores_generic(int freq)
429 int sil_rev, mpu_vdd;
432 * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all
433 * MPU frequencies we support we use a CORE voltage of
434 * 1.10V. For MPU voltage we need to switch based on
435 * the frequency we are running at.
437 #ifndef CONFIG_DM_I2C
438 if (i2c_probe(TPS65910_CTRL_I2C_ADDR))
441 if (power_tps65910_init(0))
445 * Depending on MPU clock and PG we will need a different
446 * VDD to drive at that speed.
448 sil_rev = readl(&cdev->deviceid) >> 28;
449 mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, freq);
451 /* Tell the TPS65910 to use i2c */
452 tps65910_set_i2c_control();
454 /* First update MPU voltage. */
455 if (tps65910_voltage_update(MPU, mpu_vdd))
458 /* Second, update the CORE voltage. */
459 if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_0))
464 void gpi2c_init(void)
466 /* When needed to be invoked prior to BSS initialization */
467 static bool first_time = true;
470 enable_i2c0_pin_mux();
471 #ifndef CONFIG_DM_I2C
472 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
473 CONFIG_SYS_OMAP24_I2C_SLAVE);
479 void scale_vcores(void)
484 freq = am335x_get_efuse_mpu_max_freq(cdev);
486 if (board_is_beaglebonex())
487 scale_vcores_bone(freq);
489 scale_vcores_generic(freq);
492 void set_uart_mux_conf(void)
494 #if CONFIG_CONS_INDEX == 1
495 enable_uart0_pin_mux();
496 #elif CONFIG_CONS_INDEX == 2
497 enable_uart1_pin_mux();
498 #elif CONFIG_CONS_INDEX == 3
499 enable_uart2_pin_mux();
500 #elif CONFIG_CONS_INDEX == 4
501 enable_uart3_pin_mux();
502 #elif CONFIG_CONS_INDEX == 5
503 enable_uart4_pin_mux();
504 #elif CONFIG_CONS_INDEX == 6
505 enable_uart5_pin_mux();
509 void set_mux_conf_regs(void)
511 enable_board_pin_mux();
514 const struct ctrl_ioregs ioregs_evmsk = {
515 .cm0ioctl = MT41J128MJT125_IOCTRL_VALUE,
516 .cm1ioctl = MT41J128MJT125_IOCTRL_VALUE,
517 .cm2ioctl = MT41J128MJT125_IOCTRL_VALUE,
518 .dt0ioctl = MT41J128MJT125_IOCTRL_VALUE,
519 .dt1ioctl = MT41J128MJT125_IOCTRL_VALUE,
522 const struct ctrl_ioregs ioregs_bonelt = {
523 .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
524 .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
525 .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
526 .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
527 .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
530 const struct ctrl_ioregs ioregs_evm15 = {
531 .cm0ioctl = MT41J512M8RH125_IOCTRL_VALUE,
532 .cm1ioctl = MT41J512M8RH125_IOCTRL_VALUE,
533 .cm2ioctl = MT41J512M8RH125_IOCTRL_VALUE,
534 .dt0ioctl = MT41J512M8RH125_IOCTRL_VALUE,
535 .dt1ioctl = MT41J512M8RH125_IOCTRL_VALUE,
538 const struct ctrl_ioregs ioregs = {
539 .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
540 .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
541 .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
542 .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
543 .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
546 void sdram_init(void)
548 if (board_is_evm_sk()) {
550 * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
551 * This is safe enough to do on older revs.
553 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
554 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
557 if (board_is_icev2()) {
558 gpio_request(ICE_GPIO_DDR_VTT_EN, "ddr_vtt_en");
559 gpio_direction_output(ICE_GPIO_DDR_VTT_EN, 1);
562 if (board_is_evm_sk())
563 config_ddr(303, &ioregs_evmsk, &ddr3_data,
564 &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
565 else if (board_is_pb() || board_is_bone_lt())
566 config_ddr(400, &ioregs_bonelt,
567 &ddr3_beagleblack_data,
568 &ddr3_beagleblack_cmd_ctrl_data,
569 &ddr3_beagleblack_emif_reg_data, 0);
570 else if (board_is_evm_15_or_later())
571 config_ddr(303, &ioregs_evm15, &ddr3_evm_data,
572 &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
573 else if (board_is_icev2())
574 config_ddr(400, &ioregs_evmsk, &ddr3_icev2_data,
575 &ddr3_icev2_cmd_ctrl_data, &ddr3_icev2_emif_reg_data,
577 else if (board_is_gp_evm())
578 config_ddr(266, &ioregs, &ddr2_data,
579 &ddr2_cmd_ctrl_data, &ddr2_evm_emif_reg_data, 0);
581 config_ddr(266, &ioregs, &ddr2_data,
582 &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
586 #if defined(CONFIG_CLOCK_SYNTHESIZER) && (!defined(CONFIG_SPL_BUILD) || \
587 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)))
588 static void request_and_set_gpio(int gpio, char *name, int val)
592 ret = gpio_request(gpio, name);
594 printf("%s: Unable to request %s\n", __func__, name);
598 ret = gpio_direction_output(gpio, 0);
600 printf("%s: Unable to set %s as output\n", __func__, name);
604 gpio_set_value(gpio, val);
612 #define REQUEST_AND_SET_GPIO(N) request_and_set_gpio(N, #N, 1);
613 #define REQUEST_AND_CLR_GPIO(N) request_and_set_gpio(N, #N, 0);
616 * RMII mode on ICEv2 board needs 50MHz clock. Given the clock
617 * synthesizer With a capacitor of 18pF, and 25MHz input clock cycle
618 * PLL1 gives an output of 100MHz. So, configuring the div2/3 as 2 to
619 * give 50MHz output for Eth0 and 1.
621 static struct clk_synth cdce913_data = {
630 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_CONTROL) && \
631 defined(CONFIG_DM_ETH) && defined(CONFIG_DRIVER_TI_CPSW)
633 #define MAX_CPSW_SLAVES 2
635 /* At the moment, we do not want to stop booting for any failures here */
636 int ft_board_setup(void *fdt, bd_t *bd)
638 const char *slave_path, *enet_name;
639 int enetnode, slavenode, phynode;
640 struct udevice *ethdev;
646 /* phy address fixup needed only on beagle bone family */
647 if (!board_is_beaglebonex())
650 for (i = 0; i < MAX_CPSW_SLAVES; i++) {
651 sprintf(alias, "ethernet%d", i);
653 slave_path = fdt_get_alias(fdt, alias);
657 slavenode = fdt_path_offset(fdt, slave_path);
661 enetnode = fdt_parent_offset(fdt, slavenode);
662 enet_name = fdt_get_name(fdt, enetnode, NULL);
664 ethdev = eth_get_dev_by_name(enet_name);
668 phy_addr = cpsw_get_slave_phy_addr(ethdev, i);
670 /* check for phy_id as well as phy-handle properties */
671 ret = fdtdec_get_int_array_count(fdt, slavenode, "phy_id",
674 if (phy_id[1] != phy_addr) {
675 printf("fixing up phy_id for %s, old: %d, new: %d\n",
676 alias, phy_id[1], phy_addr);
678 phy_id[0] = cpu_to_fdt32(phy_id[0]);
679 phy_id[1] = cpu_to_fdt32(phy_addr);
680 do_fixup_by_path(fdt, slave_path, "phy_id",
681 phy_id, sizeof(phy_id), 0);
684 phynode = fdtdec_lookup_phandle(fdt, slavenode,
689 ret = fdtdec_get_int(fdt, phynode, "reg", -ENOENT);
693 if (ret != phy_addr) {
694 printf("fixing up phy-handle for %s, old: %d, new: %d\n",
695 alias, ret, phy_addr);
697 fdt_setprop_u32(fdt, phynode, "reg",
698 cpu_to_fdt32(phy_addr));
709 * Basic board specific setup. Pinmux has been handled already.
713 #if defined(CONFIG_HW_WATCHDOG)
717 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
718 #if defined(CONFIG_NOR) || defined(CONFIG_MTD_RAW_NAND)
722 #if defined(CONFIG_CLOCK_SYNTHESIZER) && (!defined(CONFIG_SPL_BUILD) || \
723 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)))
724 if (board_is_icev2()) {
728 REQUEST_AND_SET_GPIO(GPIO_PR1_MII_CTRL);
729 /* Make J19 status available on GPIO1_26 */
730 REQUEST_AND_CLR_GPIO(GPIO_MUX_MII_CTRL);
732 REQUEST_AND_SET_GPIO(GPIO_FET_SWITCH_CTRL);
734 * Both ports can be set as RMII-CPSW or MII-PRU-ETH using
735 * jumpers near the port. Read the jumper value and set
736 * the pinmux, external mux and PHY clock accordingly.
737 * As jumper line is overridden by PHY RX_DV pin immediately
738 * after bootstrap (power-up/reset), we need to sample
739 * it during PHY reset using GPIO rising edge detection.
741 REQUEST_AND_SET_GPIO(GPIO_PHY_RESET);
742 /* Enable rising edge IRQ on GPIO0_11 and GPIO 1_26 */
743 reg = readl(GPIO0_RISINGDETECT) | BIT(11);
744 writel(reg, GPIO0_RISINGDETECT);
745 reg = readl(GPIO1_RISINGDETECT) | BIT(26);
746 writel(reg, GPIO1_RISINGDETECT);
747 /* Reset PHYs to capture the Jumper setting */
748 gpio_set_value(GPIO_PHY_RESET, 0);
749 udelay(2); /* PHY datasheet states 1uS min. */
750 gpio_set_value(GPIO_PHY_RESET, 1);
752 reg = readl(GPIO0_IRQSTATUSRAW) & BIT(11);
754 writel(reg, GPIO0_IRQSTATUS1); /* clear irq */
756 printf("ETH0, CPSW\n");
759 printf("ETH0, PRU\n");
760 cdce913_data.pdiv3 = 4; /* 25MHz PHY clk */
763 reg = readl(GPIO1_IRQSTATUSRAW) & BIT(26);
765 writel(reg, GPIO1_IRQSTATUS1); /* clear irq */
767 printf("ETH1, CPSW\n");
768 gpio_set_value(GPIO_MUX_MII_CTRL, 1);
771 printf("ETH1, PRU\n");
772 cdce913_data.pdiv2 = 4; /* 25MHz PHY clk */
775 /* disable rising edge IRQs */
776 reg = readl(GPIO0_RISINGDETECT) & ~BIT(11);
777 writel(reg, GPIO0_RISINGDETECT);
778 reg = readl(GPIO1_RISINGDETECT) & ~BIT(26);
779 writel(reg, GPIO1_RISINGDETECT);
781 rv = setup_clock_synthesizer(&cdce913_data);
783 printf("Clock synthesizer setup failed %d\n", rv);
788 gpio_set_value(GPIO_PHY_RESET, 0);
789 udelay(2); /* PHY datasheet states 1uS min. */
790 gpio_set_value(GPIO_PHY_RESET, 1);
797 #ifdef CONFIG_BOARD_LATE_INIT
798 int board_late_init(void)
801 #if !defined(CONFIG_SPL_BUILD)
803 uint32_t mac_hi, mac_lo;
806 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
809 if (board_is_bone_lt()) {
810 /* BeagleBoard.org BeagleBone Black Wireless: */
811 if (!strncmp(board_ti_get_rev(), "BWA", 3)) {
814 /* SeeedStudio BeagleBone Green Wireless */
815 if (!strncmp(board_ti_get_rev(), "GW1", 3)) {
818 /* BeagleBoard.org BeagleBone Blue */
819 if (!strncmp(board_ti_get_rev(), "BLA", 3)) {
828 set_board_info_env(name);
831 * Default FIT boot on HS devices. Non FIT images are not allowed
834 if (get_device_type() == HS_DEVICE)
835 env_set("boot_fit", "1");
838 #if !defined(CONFIG_SPL_BUILD)
839 /* try reading mac address from efuse */
840 mac_lo = readl(&cdev->macid0l);
841 mac_hi = readl(&cdev->macid0h);
842 mac_addr[0] = mac_hi & 0xFF;
843 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
844 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
845 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
846 mac_addr[4] = mac_lo & 0xFF;
847 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
849 if (!env_get("ethaddr")) {
850 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
852 if (is_valid_ethaddr(mac_addr))
853 eth_env_set_enetaddr("ethaddr", mac_addr);
856 mac_lo = readl(&cdev->macid1l);
857 mac_hi = readl(&cdev->macid1h);
858 mac_addr[0] = mac_hi & 0xFF;
859 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
860 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
861 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
862 mac_addr[4] = mac_lo & 0xFF;
863 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
865 if (!env_get("eth1addr")) {
866 if (is_valid_ethaddr(mac_addr))
867 eth_env_set_enetaddr("eth1addr", mac_addr);
871 if (!env_get("serial#")) {
872 char *board_serial = env_get("board_serial");
873 char *ethaddr = env_get("ethaddr");
875 if (!board_serial || !strncmp(board_serial, "unknown", 7))
876 env_set("serial#", ethaddr);
878 env_set("serial#", board_serial);
881 /* Just probe the potentially supported cdce913 device */
882 uclass_get_device(UCLASS_CLK, 0, &dev);
889 #if !CONFIG_IS_ENABLED(OF_CONTROL)
890 struct cpsw_slave_data slave_data[] = {
892 .slave_reg_ofs = CPSW_SLAVE0_OFFSET,
893 .sliver_reg_ofs = CPSW_SLIVER0_OFFSET,
897 .slave_reg_ofs = CPSW_SLAVE1_OFFSET,
898 .sliver_reg_ofs = CPSW_SLIVER1_OFFSET,
903 struct cpsw_platform_data am335_eth_data = {
904 .cpsw_base = CPSW_BASE,
905 .version = CPSW_CTRL_VERSION_2,
906 .bd_ram_ofs = CPSW_BD_OFFSET,
907 .ale_reg_ofs = CPSW_ALE_OFFSET,
908 .cpdma_reg_ofs = CPSW_CPDMA_OFFSET,
909 .mdio_div = CPSW_MDIO_DIV,
910 .host_port_reg_ofs = CPSW_HOST_PORT_OFFSET,
913 .slave_data = slave_data,
915 .bd_ram_ofs = 0x2000,
918 .mdio_base = 0x4a101000,
919 .gmii_sel = 0x44e10650,
920 .phy_sel_compat = "ti,am3352-cpsw-phy-sel",
921 .syscon_addr = 0x44e10630,
922 .macid_sel_compat = "cpsw,am33xx",
925 struct eth_pdata cpsw_pdata = {
926 .iobase = 0x4a100000,
928 .priv_pdata = &am335_eth_data,
931 U_BOOT_DEVICE(am335x_eth) = {
933 .platdata = &cpsw_pdata,
937 #ifdef CONFIG_SPL_LOAD_FIT
938 int board_fit_config_name_match(const char *name)
940 if (board_is_gp_evm() && !strcmp(name, "am335x-evm"))
942 else if (board_is_bone() && !strcmp(name, "am335x-bone"))
944 else if (board_is_bone_lt() && !strcmp(name, "am335x-boneblack"))
946 else if (board_is_pb() && !strcmp(name, "am335x-pocketbeagle"))
948 else if (board_is_evm_sk() && !strcmp(name, "am335x-evmsk"))
950 else if (board_is_bbg1() && !strcmp(name, "am335x-bonegreen"))
952 else if (board_is_icev2() && !strcmp(name, "am335x-icev2"))
959 #ifdef CONFIG_TI_SECURE_DEVICE
960 void board_fit_image_post_process(void **p_image, size_t *p_size)
962 secure_boot_verify_image(p_image, p_size);
966 #if !CONFIG_IS_ENABLED(OF_CONTROL)
967 static const struct omap_hsmmc_plat am335x_mmc0_platdata = {
968 .base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE,
969 .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_4BIT,
971 .cfg.f_max = 52000000,
972 .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195,
973 .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
976 U_BOOT_DEVICE(am335x_mmc0) = {
977 .name = "omap_hsmmc",
978 .platdata = &am335x_mmc0_platdata,
981 static const struct omap_hsmmc_plat am335x_mmc1_platdata = {
982 .base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE,
983 .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_8BIT,
985 .cfg.f_max = 52000000,
986 .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195,
987 .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
990 U_BOOT_DEVICE(am335x_mmc1) = {
991 .name = "omap_hsmmc",
992 .platdata = &am335x_mmc1_platdata,