3 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
5 * Copyright (C) 2009 TechNexion Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
28 #include <asm/arch/mem.h>
29 #include <asm/arch/mux.h>
30 #include <asm/arch/sys_proto.h>
31 #include <asm/omap_gpio.h>
32 #include <asm/arch/mmc_host_def.h>
33 #include <asm/arch/dss.h>
34 #include <asm/arch/clocks.h>
38 #ifdef CONFIG_USB_EHCI
40 #include <asm/ehci-omap.h>
42 #include "mt_ventoux.h"
44 DECLARE_GLOBAL_DATA_PTR;
50 #error "The Teejet mt_ventoux must have CONFIG_FPGA enabled"
61 #define LCD_PON_PIN 139
63 #if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
67 } panel_resolution[] = {
72 static struct panel_config lcd_cfg[] = {
74 .timing_h = PANEL_TIMING_H(4, 8, 41),
75 .timing_v = PANEL_TIMING_V(2, 4, 10),
76 .pol_freq = 0x00000000, /* Pol Freq */
77 .divisor = 0x0001000d, /* 33Mhz Pixel Clock */
78 .panel_type = 0x01, /* TFT */
79 .data_lines = 0x03, /* 24 Bit RGB */
80 .load_mode = 0x02, /* Frame Mode */
84 .timing_h = PANEL_TIMING_H(20, 192, 4),
85 .timing_v = PANEL_TIMING_V(2, 20, 10),
86 .pol_freq = 0x00004000, /* Pol Freq */
87 .divisor = 0x0001000E, /* 36Mhz Pixel Clock */
88 .panel_type = 0x01, /* TFT */
89 .data_lines = 0x03, /* 24 Bit RGB */
90 .load_mode = 0x02, /* Frame Mode */
96 /* Timing definitions for FPGA */
97 static const u32 gpmc_fpga[] = {
106 #ifdef CONFIG_USB_EHCI
107 static struct omap_usbhs_board_data usbhs_bdata = {
108 .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
109 .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
110 .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
113 int ehci_hcd_init(void)
115 return omap_ehci_hcd_init(&usbhs_bdata);
118 int ehci_hcd_stop(void)
120 return omap_ehci_hcd_stop();
125 static inline void fpga_reset(int nassert)
127 gpio_set_value(FPGA_RESET, !nassert);
130 int fpga_pgm_fn(int nassert, int nflush, int cookie)
132 debug("%s:%d: FPGA PROGRAM ", __func__, __LINE__);
134 gpio_set_value(FPGA_PROG, !nassert);
139 int fpga_init_fn(int cookie)
141 return !gpio_get_value(FPGA_INIT);
144 int fpga_done_fn(int cookie)
146 return gpio_get_value(FPGA_DONE);
149 int fpga_pre_config_fn(int cookie)
151 debug("%s:%d: FPGA pre-configuration\n", __func__, __LINE__);
153 /* Setting GPIOs for programming Mode */
154 gpio_request(FPGA_RESET, "FPGA_RESET");
155 gpio_direction_output(FPGA_RESET, 1);
156 gpio_request(FPGA_PROG, "FPGA_PROG");
157 gpio_direction_output(FPGA_PROG, 1);
158 gpio_request(FPGA_CCLK, "FPGA_CCLK");
159 gpio_direction_output(FPGA_CCLK, 1);
160 gpio_request(FPGA_DIN, "FPGA_DIN");
161 gpio_direction_output(FPGA_DIN, 0);
162 gpio_request(FPGA_INIT, "FPGA_INIT");
163 gpio_direction_input(FPGA_INIT);
164 gpio_request(FPGA_DONE, "FPGA_DONE");
165 gpio_direction_input(FPGA_DONE);
167 /* Be sure that signal are deasserted */
168 gpio_set_value(FPGA_RESET, 1);
169 gpio_set_value(FPGA_PROG, 1);
174 int fpga_post_config_fn(int cookie)
176 debug("%s:%d: FPGA post-configuration\n", __func__, __LINE__);
185 /* Write program to the FPGA */
186 int fpga_wr_fn(int nassert_write, int flush, int cookie)
188 gpio_set_value(FPGA_DIN, nassert_write);
190 return nassert_write;
193 int fpga_clk_fn(int assert_clk, int flush, int cookie)
195 gpio_set_value(FPGA_CCLK, assert_clk);
200 Xilinx_Spartan3_Slave_Serial_fns mt_ventoux_fpga_fns = {
210 Xilinx_desc fpga = XILINX_XC6SLX4_DESC(slave_serial,
211 (void *)&mt_ventoux_fpga_fns, 0);
213 /* Initialize the FPGA */
214 static void mt_ventoux_init_fpga(void)
216 fpga_pre_config_fn(0);
218 /* Setting CS1 for FPGA access */
219 enable_gpmc_cs_config(gpmc_fpga, &gpmc_cfg->cs[1],
220 FPGA_BASE_ADDR, GPMC_SIZE_128M);
223 fpga_add(fpga_xilinx, &fpga);
227 * Routine: board_init
228 * Description: Early hardware init.
232 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
234 /* boot param addr */
235 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
237 mt_ventoux_init_fpga();
239 /* GPIO_140: speaker #mute */
240 MUX_VAL(CP(MCBSP3_DX), (IEN | PTU | EN | M4))
241 /* GPIO_141: Buzz Hi */
242 MUX_VAL(CP(MCBSP3_DR), (IEN | PTU | EN | M4))
244 /* Turning off the buzzer */
245 gpio_request(BUZZER, "BUZZER_MUTE");
246 gpio_request(SPEAKER, "SPEAKER");
247 gpio_direction_output(BUZZER, 0);
248 gpio_direction_output(SPEAKER, 0);
253 int misc_init_r(void)
259 eth_addr = getenv("ethaddr");
263 #ifndef CONFIG_SPL_BUILD
264 TAM3517_READ_MAC_FROM_EEPROM;
270 * Routine: set_muxconf_regs
271 * Description: Setting up the configuration Mux registers specific to the
272 * hardware. Many pins need to be moved from protect to primary
275 void set_muxconf_regs(void)
281 * Initializes on-chip ethernet controllers.
282 * to override, implement board_eth_init()
284 int board_eth_init(bd_t *bis)
286 davinci_emac_initialize();
290 #if defined(CONFIG_OMAP_HSMMC) && \
291 !defined(CONFIG_SPL_BUILD)
292 int board_mmc_init(bd_t *bis)
294 return omap_mmc_init(0, 0, 0);
298 #if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
299 int board_video_init(void)
301 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
302 struct panel_config *panel = &lcd_cfg[0];
308 fb = (void *)0x88000000;
312 index = simple_strtoul(s, NULL, 10);
313 if (index < ARRAY_SIZE(lcd_cfg))
314 panel = &lcd_cfg[index];
319 panel->frame_buffer = fb;
320 printf("Panel: %dx%d\n", panel_resolution[index].xres,
321 panel_resolution[index].yres);
322 panel->lcd_size = (panel_resolution[index].yres - 1) << 16 |
323 (panel_resolution[index].xres - 1);
325 gpio_request(LCD_PWR, "LCD Power");
326 gpio_request(LCD_PON_PIN, "LCD Pon");
327 gpio_direction_output(LCD_PWR, 0);
328 gpio_direction_output(LCD_PON_PIN, 1);
331 setbits_le32(&prcm_base->fclken_dss, FCK_DSS_ON);
332 setbits_le32(&prcm_base->iclken_dss, ICK_DSS_ON);
334 omap3_dss_panel_config(panel);