3 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
5 * Copyright (C) 2009 TechNexion Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
28 #include <asm/arch/mem.h>
29 #include <asm/arch/mux.h>
30 #include <asm/arch/sys_proto.h>
31 #include <asm/omap_gpio.h>
32 #include <asm/arch/mmc_host_def.h>
33 #include <asm/arch/dss.h>
34 #include <asm/arch/clocks.h>
38 #ifdef CONFIG_USB_EHCI
40 #include <asm/ehci-omap.h>
42 #include "mt_ventoux.h"
44 DECLARE_GLOBAL_DATA_PTR;
52 #error "The Teejet mt_ventoux must have CONFIG_FPGA enabled"
63 #define LCD_PON_PIN 139
65 #if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
69 } panel_resolution[] = {
74 static struct panel_config lcd_cfg[] = {
76 .timing_h = PANEL_TIMING_H(40, 5, 2),
77 .timing_v = PANEL_TIMING_V(8, 8, 2),
78 .pol_freq = 0x00003000, /* Pol Freq */
79 .divisor = 0x00010033, /* 9 Mhz Pixel Clock */
80 .panel_type = 0x01, /* TFT */
81 .data_lines = 0x03, /* 24 Bit RGB */
82 .load_mode = 0x02, /* Frame Mode */
84 .gfx_format = GFXFORMAT_RGB24_UNPACKED,
87 .timing_h = PANEL_TIMING_H(20, 192, 4),
88 .timing_v = PANEL_TIMING_V(2, 20, 10),
89 .pol_freq = 0x00004000, /* Pol Freq */
90 .divisor = 0x0001000E, /* 36Mhz Pixel Clock */
91 .panel_type = 0x01, /* TFT */
92 .data_lines = 0x03, /* 24 Bit RGB */
93 .load_mode = 0x02, /* Frame Mode */
95 .gfx_format = GFXFORMAT_RGB24_UNPACKED,
100 /* Timing definitions for FPGA */
101 static const u32 gpmc_fpga[] = {
110 #ifdef CONFIG_USB_EHCI
111 static struct omap_usbhs_board_data usbhs_bdata = {
112 .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
113 .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
114 .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
117 int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
119 return omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor);
122 int ehci_hcd_stop(int index)
124 return omap_ehci_hcd_stop();
129 static inline void fpga_reset(int nassert)
131 gpio_set_value(FPGA_RESET, !nassert);
134 int fpga_pgm_fn(int nassert, int nflush, int cookie)
136 debug("%s:%d: FPGA PROGRAM ", __func__, __LINE__);
138 gpio_set_value(FPGA_PROG, !nassert);
143 int fpga_init_fn(int cookie)
145 return !gpio_get_value(FPGA_INIT);
148 int fpga_done_fn(int cookie)
150 return gpio_get_value(FPGA_DONE);
153 int fpga_pre_config_fn(int cookie)
155 debug("%s:%d: FPGA pre-configuration\n", __func__, __LINE__);
157 /* Setting GPIOs for programming Mode */
158 gpio_request(FPGA_RESET, "FPGA_RESET");
159 gpio_direction_output(FPGA_RESET, 1);
160 gpio_request(FPGA_PROG, "FPGA_PROG");
161 gpio_direction_output(FPGA_PROG, 1);
162 gpio_request(FPGA_CCLK, "FPGA_CCLK");
163 gpio_direction_output(FPGA_CCLK, 1);
164 gpio_request(FPGA_DIN, "FPGA_DIN");
165 gpio_direction_output(FPGA_DIN, 0);
166 gpio_request(FPGA_INIT, "FPGA_INIT");
167 gpio_direction_input(FPGA_INIT);
168 gpio_request(FPGA_DONE, "FPGA_DONE");
169 gpio_direction_input(FPGA_DONE);
171 /* Be sure that signal are deasserted */
172 gpio_set_value(FPGA_RESET, 1);
173 gpio_set_value(FPGA_PROG, 1);
178 int fpga_post_config_fn(int cookie)
180 debug("%s:%d: FPGA post-configuration\n", __func__, __LINE__);
189 /* Write program to the FPGA */
190 int fpga_wr_fn(int nassert_write, int flush, int cookie)
192 gpio_set_value(FPGA_DIN, nassert_write);
194 return nassert_write;
197 int fpga_clk_fn(int assert_clk, int flush, int cookie)
199 gpio_set_value(FPGA_CCLK, assert_clk);
204 Xilinx_Spartan3_Slave_Serial_fns mt_ventoux_fpga_fns = {
214 Xilinx_desc fpga = XILINX_XC6SLX4_DESC(slave_serial,
215 (void *)&mt_ventoux_fpga_fns, 0);
217 /* Initialize the FPGA */
218 static void mt_ventoux_init_fpga(void)
220 fpga_pre_config_fn(0);
222 /* Setting CS1 for FPGA access */
223 enable_gpmc_cs_config(gpmc_fpga, &gpmc_cfg->cs[1],
224 FPGA_BASE_ADDR, GPMC_SIZE_128M);
227 fpga_add(fpga_xilinx, &fpga);
231 * Routine: board_init
232 * Description: Early hardware init.
236 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
238 /* boot param addr */
239 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
241 mt_ventoux_init_fpga();
243 /* GPIO_140: speaker #mute */
244 MUX_VAL(CP(MCBSP3_DX), (IEN | PTU | EN | M4))
245 /* GPIO_141: Buzz Hi */
246 MUX_VAL(CP(MCBSP3_DR), (IEN | PTU | EN | M4))
248 /* Turning off the buzzer */
249 gpio_request(BUZZER, "BUZZER_MUTE");
250 gpio_request(SPEAKER, "SPEAKER");
251 gpio_direction_output(BUZZER, 0);
252 gpio_direction_output(SPEAKER, 0);
254 /* Activate USB power */
255 gpio_request(USB1_PWR, "USB1_PWR");
256 gpio_request(USB2_PWR, "USB2_PWR");
257 gpio_direction_output(USB1_PWR, 1);
258 gpio_direction_output(USB2_PWR, 1);
263 #ifndef CONFIG_SPL_BUILD
264 int misc_init_r(void)
267 struct tam3517_module_info info;
270 TAM3517_READ_EEPROM(&info, ret);
275 eth_addr = getenv("ethaddr");
277 TAM3517_READ_MAC_FROM_EEPROM(&info);
279 TAM3517_PRINT_SOM_INFO(&info);
285 * Routine: set_muxconf_regs
286 * Description: Setting up the configuration Mux registers specific to the
287 * hardware. Many pins need to be moved from protect to primary
290 void set_muxconf_regs(void)
296 * Initializes on-chip ethernet controllers.
297 * to override, implement board_eth_init()
299 int board_eth_init(bd_t *bis)
301 davinci_emac_initialize();
305 #if defined(CONFIG_OMAP_HSMMC) && \
306 !defined(CONFIG_SPL_BUILD)
307 int board_mmc_init(bd_t *bis)
309 return omap_mmc_init(0, 0, 0, -1, -1);
313 #if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
314 int board_video_init(void)
316 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
317 struct panel_config *panel = &lcd_cfg[0];
323 fb = (void *)0x88000000;
327 index = simple_strtoul(s, NULL, 10);
328 if (index < ARRAY_SIZE(lcd_cfg))
329 panel = &lcd_cfg[index];
334 panel->frame_buffer = fb;
335 printf("Panel: %dx%d\n", panel_resolution[index].xres,
336 panel_resolution[index].yres);
337 panel->lcd_size = (panel_resolution[index].yres - 1) << 16 |
338 (panel_resolution[index].xres - 1);
340 gpio_request(LCD_PWR, "LCD Power");
341 gpio_request(LCD_PON_PIN, "LCD Pon");
342 gpio_direction_output(LCD_PWR, 0);
343 gpio_direction_output(LCD_PON_PIN, 1);
346 setbits_le32(&prcm_base->fclken_dss, FCK_DSS_ON);
347 setbits_le32(&prcm_base->iclken_dss, ICK_DSS_ON);
349 omap3_dss_panel_config(panel);