board/technexion/pico-imx7d/spl.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2018 Technexion Ltd.
   4  *
   5  * Author: Richard Hu <richard.hu@technexion.com>
   6  */
   7
   8 #include <common.h>
   9 #include <cpu_func.h>
  10 #include <init.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/imx-regs.h>
  13 #include <asm/arch/crm_regs.h>
  14 #include <asm/arch/mx7-pins.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/arch-mx7/mx7-ddr.h>
  17 #include <asm/mach-imx/iomux-v3.h>
  18 #include <asm/gpio.h>
  19 #include <fsl_esdhc_imx.h>
  20 #include <spl.h>
  21
  22 #if defined(CONFIG_SPL_BUILD)
  23
  24 #ifdef CONFIG_SPL_OS_BOOT
  25 int spl_start_uboot(void)
  26 {
  27         /* Break into full U-Boot on 'c' */
  28         if (serial_tstc() && serial_getc() == 'c')
  29                 return 1;
  30
  31         return 0;
  32 }
  33 #endif
  34
  35 static struct ddrc ddrc_regs_val = {
  36         .mstr           = 0x01040001,
  37         .rfshtmg        = 0x00400046,
  38         .init1          = 0x00690000,
  39         .init0          = 0x00020083,
  40         .init3          = 0x09300004,
  41         .init4          = 0x04080000,
  42         .init5          = 0x00100004,
  43         .rankctl        = 0x0000033F,
  44         .dramtmg0       = 0x09081109,
  45         .dramtmg1       = 0x0007020d,
  46         .dramtmg2       = 0x03040407,
  47         .dramtmg3       = 0x00002006,
  48         .dramtmg4       = 0x04020205,
  49         .dramtmg5       = 0x03030202,
  50         .dramtmg8       = 0x00000803,
  51         .zqctl0         = 0x00800020,
  52         .dfitmg0        = 0x02098204,
  53         .dfitmg1        = 0x00030303,
  54         .dfiupd0        = 0x80400003,
  55         .dfiupd1        = 0x00100020,
  56         .dfiupd2        = 0x80100004,
  57         .addrmap4       = 0x00000F0F,
  58         .odtcfg         = 0x06000604,
  59         .odtmap         = 0x00000001,
  60         .rfshtmg        = 0x00400046,
  61         .dramtmg0       = 0x09081109,
  62         .addrmap0       = 0x0000001f,
  63         .addrmap1       = 0x00080808,
  64         .addrmap4       = 0x00000f0f,
  65         .addrmap5       = 0x07070707,
  66         .addrmap6       = 0x0f0f0707,
  67 };
  68
  69 static struct ddrc_mp ddrc_mp_val = {
  70         .pctrl_0        = 0x00000001,
  71 };
  72
  73 static struct ddr_phy ddr_phy_regs_val = {
  74         .phy_con0       = 0x17420f40,
  75         .phy_con1       = 0x10210100,
  76         .phy_con4       = 0x00060807,
  77         .mdll_con0      = 0x1010007e,
  78         .drvds_con0     = 0x00000d6e,
  79         .cmd_sdll_con0  = 0x00000010,
  80         .offset_lp_con0 = 0x0000000f,
  81         .offset_rd_con0 = 0x08080808,
  82         .offset_wr_con0 = 0x08080808,
  83 };
  84
  85 static struct mx7_calibration calib_param = {
  86         .num_val        = 5,
  87         .values         = {
  88                 0x0E407304,
  89                 0x0E447304,
  90                 0x0E447306,
  91                 0x0E447304,
  92                 0x0E447304,
  93         },
  94 };
  95
  96 static void gpr_init(void)
  97 {
  98         struct iomuxc_gpr_base_regs *gpr_regs =
  99                 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
 100         writel(0x4F400005, &gpr_regs->gpr[1]);
 101 }
 102
 103 static bool is_1g(void)
 104 {
 105         gpio_direction_input(IMX_GPIO_NR(1, 12));
 106         return !gpio_get_value(IMX_GPIO_NR(1, 12));
 107 }
 108
 109 static void ddr_init(void)
 110 {
 111         if (is_1g())
 112                 ddrc_regs_val.addrmap6  = 0x0f070707;
 113
 114         mx7_dram_cfg(&ddrc_regs_val, &ddrc_mp_val, &ddr_phy_regs_val,
 115                      &calib_param);
 116 }
 117
 118 void board_init_f(ulong dummy)
 119 {
 120         arch_cpu_init();
 121         gpr_init();
 122         board_early_init_f();
 123         timer_init();
 124         preloader_console_init();
 125         ddr_init();
 126         memset(__bss_start, 0, __bss_end - __bss_start);
 127         board_init_r(NULL, 0);
 128 }
 129
 130 void reset_cpu(ulong addr)
 131 {
 132 }
 133
 134 #define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
 135         PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
 136
 137 static iomux_v3_cfg_t const usdhc3_pads[] = {
 138         MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 139         MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 140         MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 141         MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 142         MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 143         MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 144         MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 145         MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 146         MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 147         MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 148         MX7D_PAD_GPIO1_IO14__GPIO1_IO14 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 149 };
 150
 151 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
 152         {USDHC3_BASE_ADDR},
 153 };
 154
 155 int board_mmc_getcd(struct mmc *mmc)
 156 {
 157         /* Assume uSDHC3 emmc is always present */
 158         return 1;
 159 }
 160
 161 int board_mmc_init(bd_t *bis)
 162 {
 163         imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 164         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 165         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 166 }
 167 #endif