board/technexion/pico-imx7d/pico-imx7d.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2017 NXP Semiconductors
   4  */
   5
   6 #include <asm/arch/clock.h>
   7 #include <asm/arch/crm_regs.h>
   8 #include <asm/arch/imx-regs.h>
   9 #include <asm/arch/mx7-pins.h>
  10 #include <asm/arch/sys_proto.h>
  11 #include <asm/gpio.h>
  12 #include <asm/mach-imx/iomux-v3.h>
  13 #include <asm/mach-imx/mxc_i2c.h>
  14 #include <asm/io.h>
  15 #include <common.h>
  16 #include <i2c.h>
  17 #include <miiphy.h>
  18 #include <netdev.h>
  19 #include <power/pmic.h>
  20 #include <power/pfuze3000_pmic.h>
  21 #include "../../freescale/common/pfuze.h"
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 #define UART_PAD_CTRL  (PAD_CTL_DSE_3P3V_49OHM | \
  26         PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
  27
  28 #define ENET_PAD_CTRL  (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
  29 #define ENET_PAD_CTRL_MII  (PAD_CTL_DSE_3P3V_32OHM)
  30
  31 #define ENET_RX_PAD_CTRL  (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
  32
  33 #define I2C_PAD_CTRL    (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
  34         PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
  35
  36
  37 #define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
  38                          PAD_CTL_DSE_3P3V_49OHM)
  39
  40 #define LCD_SYNC_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
  41                               PAD_CTL_DSE_3P3V_196OHM)
  42
  43 #ifdef CONFIG_SYS_I2C_MXC
  44 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  45
  46 /* I2C4 for PMIC */
  47 static struct i2c_pads_info i2c_pad_info4 = {
  48         .scl = {
  49                 .i2c_mode = MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL | PC,
  50                 .gpio_mode = MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 | PC,
  51                 .gp = IMX_GPIO_NR(6, 16),
  52         },
  53         .sda = {
  54                 .i2c_mode = MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA | PC,
  55                 .gpio_mode = MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 | PC,
  56                 .gp = IMX_GPIO_NR(6, 17),
  57         },
  58 };
  59 #endif
  60
  61 int dram_init(void)
  62 {
  63         gd->ram_size = imx_ddr_size();
  64
  65         /* Subtract the defined OPTEE runtime firmware length */
  66 #ifdef CONFIG_OPTEE_TZDRAM_SIZE
  67                 gd->ram_size -= CONFIG_OPTEE_TZDRAM_SIZE;
  68 #endif
  69
  70         return 0;
  71 }
  72
  73 #ifdef CONFIG_POWER
  74 #define I2C_PMIC        3
  75 int power_init_board(void)
  76 {
  77         struct pmic *p;
  78         int ret;
  79         unsigned int reg, rev_id;
  80
  81         ret = power_pfuze3000_init(I2C_PMIC);
  82         if (ret)
  83                 return ret;
  84
  85         p = pmic_get("PFUZE3000");
  86         ret = pmic_probe(p);
  87         if (ret) {
  88                 printf("Warning:  Cannot find PMIC PFUZE3000\n");
  89                 printf("\tPower consumption is not optimized.\n");
  90                 return 0;
  91         }
  92
  93         pmic_reg_read(p, PFUZE3000_DEVICEID, &reg);
  94         pmic_reg_read(p, PFUZE3000_REVID, &rev_id);
  95         printf("PMIC:  PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
  96
  97         /* disable Low Power Mode during standby mode */
  98         pmic_reg_read(p, PFUZE3000_LDOGCTL, &reg);
  99         reg |= 0x1;
 100         pmic_reg_write(p, PFUZE3000_LDOGCTL, reg);
 101
 102         /* SW1A/1B mode set to APS/APS */
 103         reg = 0x8;
 104         pmic_reg_write(p, PFUZE3000_SW1AMODE, reg);
 105         pmic_reg_write(p, PFUZE3000_SW1BMODE, reg);
 106
 107         /* SW1A/1B standby voltage set to 1.025V */
 108         reg = 0xd;
 109         pmic_reg_write(p, PFUZE3000_SW1ASTBY, reg);
 110         pmic_reg_write(p, PFUZE3000_SW1BSTBY, reg);
 111
 112         /* decrease SW1B normal voltage to 0.975V */
 113         pmic_reg_read(p, PFUZE3000_SW1BVOLT, &reg);
 114         reg &= ~0x1f;
 115         reg |= PFUZE3000_SW1AB_SETP(975);
 116         pmic_reg_write(p, PFUZE3000_SW1BVOLT, reg);
 117
 118         return 0;
 119 }
 120 #endif
 121
 122 static iomux_v3_cfg_t const wdog_pads[] = {
 123         MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
 124 };
 125
 126 static iomux_v3_cfg_t const uart5_pads[] = {
 127         MX7D_PAD_I2C4_SCL__UART5_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
 128         MX7D_PAD_I2C4_SDA__UART5_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
 129 };
 130
 131 #ifdef CONFIG_FEC_MXC
 132 static iomux_v3_cfg_t const fec1_pads[] = {
 133         MX7D_PAD_SD2_CD_B__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
 134         MX7D_PAD_SD2_WP__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
 135         MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
 136         MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 137         MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 138         MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 139         MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 140         MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
 141         MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 142         MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 143         MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 144         MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 145         MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 146         MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 147         MX7D_PAD_SD3_STROBE__GPIO6_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
 148         MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
 149 };
 150
 151 #define FEC1_RST_GPIO   IMX_GPIO_NR(6, 11)
 152
 153 static void setup_iomux_fec(void)
 154 {
 155         imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
 156         gpio_request(FEC1_RST_GPIO, "phy_rst");
 157         gpio_direction_output(FEC1_RST_GPIO, 0);
 158         udelay(500);
 159         gpio_set_value(FEC1_RST_GPIO, 1);
 160 }
 161
 162 int board_eth_init(bd_t *bis)
 163 {
 164         setup_iomux_fec();
 165
 166         return fecmxc_initialize_multi(bis, 0,
 167                 CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
 168 }
 169
 170 static int setup_fec(void)
 171 {
 172         struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
 173                 = (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
 174
 175         /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17] */
 176         clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
 177                         (IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK |
 178                         IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0);
 179
 180         return set_clk_enet(ENET_125MHZ);
 181 }
 182
 183 int board_phy_config(struct phy_device *phydev)
 184 {
 185         unsigned short val;
 186
 187         /* To enable AR8035 ouput a 125MHz clk from CLK_25M */
 188         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 189         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
 190         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 191
 192         val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
 193         val &= 0xffe7;
 194         val |= 0x18;
 195         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
 196
 197         /* introduce tx clock delay */
 198         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
 199         val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
 200         val |= 0x0100;
 201         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
 202
 203         if (phydev->drv->config)
 204                 phydev->drv->config(phydev);
 205
 206         return 0;
 207 }
 208 #endif
 209
 210 static void setup_iomux_uart(void)
 211 {
 212         imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads));
 213 }
 214
 215 int board_early_init_f(void)
 216 {
 217         setup_iomux_uart();
 218
 219 #ifdef CONFIG_SYS_I2C_MXC
 220         setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info4);
 221 #endif
 222
 223         return 0;
 224 }
 225
 226 #ifdef CONFIG_VIDEO_MXS
 227 static iomux_v3_cfg_t const lcd_pads[] = {
 228         MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
 229         MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_SYNC_PAD_CTRL),
 230         MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_SYNC_PAD_CTRL),
 231         MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_SYNC_PAD_CTRL),
 232         MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 233         MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 234         MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 235         MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 236         MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 237         MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 238         MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 239         MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 240         MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 241         MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 242         MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 243         MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 244         MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 245         MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 246         MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 247         MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 248         MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 249         MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 250         MX7D_PAD_LCD_DATA18__LCD_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 251         MX7D_PAD_LCD_DATA19__LCD_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 252         MX7D_PAD_LCD_DATA20__LCD_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 253         MX7D_PAD_LCD_DATA21__LCD_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 254         MX7D_PAD_LCD_DATA22__LCD_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 255         MX7D_PAD_LCD_DATA23__LCD_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 256         MX7D_PAD_GPIO1_IO06__GPIO1_IO6  | MUX_PAD_CTRL(LCD_PAD_CTRL),
 257         MX7D_PAD_GPIO1_IO11__GPIO1_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
 258 };
 259
 260 void setup_lcd(void)
 261 {
 262         imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
 263         gpio_request(IMX_GPIO_NR(1, 11), "lcd_brightness");
 264         gpio_request(IMX_GPIO_NR(1, 6), "lcd_enable");
 265         /* Set Brightness to high */
 266         gpio_direction_output(IMX_GPIO_NR(1, 11) , 1);
 267         /* Set LCD enable to high */
 268         gpio_direction_output(IMX_GPIO_NR(1, 6) , 1);
 269 }
 270 #endif
 271
 272 int board_init(void)
 273 {
 274         /* address of boot parameters */
 275         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 276
 277 #ifdef CONFIG_VIDEO_MXS
 278         setup_lcd();
 279 #endif
 280 #ifdef CONFIG_FEC_MXC
 281         setup_fec();
 282 #endif
 283
 284         return 0;
 285 }
 286
 287 int board_late_init(void)
 288 {
 289         struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
 290
 291         imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
 292
 293         set_wdog_reset(wdog);
 294
 295         /*
 296          * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4),
 297          * since we use PMIC_PWRON to reset the board.
 298          */
 299         clrsetbits_le16(&wdog->wcr, 0, 0x10);
 300
 301         return 0;
 302 }
 303
 304 int checkboard(void)
 305 {
 306         puts("Board: i.MX7D PICOSOM\n");
 307
 308         return 0;
 309 }
 310
 311 static iomux_v3_cfg_t const usb_otg2_pads[] = {
 312         MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
 313 };
 314
 315 int board_ehci_hcd_init(int port)
 316 {
 317         switch (port) {
 318         case 0:
 319                 break;
 320         case 1:
 321                 imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
 322                                                  ARRAY_SIZE(usb_otg2_pads));
 323                 break;
 324         default:
 325                 return -EINVAL;
 326         }
 327         return 0;
 328 }
 329