board/technexion/pico-imx6/spl.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2015 Technexion Ltd.
   4  *
   5  * Author: Richard Hu <richard.hu@technexion.com>
   6  *         Fabio Estevam <festevam@gmail.com>
   7  */
   8
   9 #include <asm/arch/clock.h>
  10 #include <asm/arch/imx-regs.h>
  11 #include <asm/arch/iomux.h>
  12 #include <asm/arch/mx6-pins.h>
  13 #include <linux/errno.h>
  14 #include <asm/gpio.h>
  15 #include <asm/mach-imx/iomux-v3.h>
  16 #include <asm/mach-imx/video.h>
  17 #include <mmc.h>
  18 #include <fsl_esdhc_imx.h>
  19 #include <asm/arch/crm_regs.h>
  20 #include <asm/io.h>
  21 #include <asm/arch/sys_proto.h>
  22 #include <spl.h>
  23
  24 #if defined(CONFIG_SPL_BUILD)
  25 #include <asm/arch/mx6-ddr.h>
  26
  27 #define IMX6DQ_DRIVE_STRENGTH           0x30
  28 #define IMX6SDL_DRIVE_STRENGTH          0x28
  29
  30 /* configure MX6Q/DUAL mmdc DDR io registers */
  31 static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
  32         .dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
  33         .dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
  34         .dram_cas = IMX6DQ_DRIVE_STRENGTH,
  35         .dram_ras = IMX6DQ_DRIVE_STRENGTH,
  36         .dram_reset = IMX6DQ_DRIVE_STRENGTH,
  37         .dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH,
  38         .dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH,
  39         .dram_sdba2 = 0x00000000,
  40         .dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
  41         .dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
  42         .dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
  43         .dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
  44         .dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
  45         .dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
  46         .dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
  47         .dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
  48         .dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
  49         .dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
  50         .dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
  51         .dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
  52         .dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
  53         .dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
  54         .dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
  55         .dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
  56         .dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
  57         .dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
  58 };
  59
  60 /* configure MX6Q/DUAL mmdc GRP io registers */
  61 static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
  62         .grp_ddr_type = 0x000c0000,
  63         .grp_ddrmode_ctl = 0x00020000,
  64         .grp_ddrpke = 0x00000000,
  65         .grp_addds = IMX6DQ_DRIVE_STRENGTH,
  66         .grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
  67         .grp_ddrmode = 0x00020000,
  68         .grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
  69         .grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
  70         .grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
  71         .grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
  72         .grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
  73         .grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
  74         .grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
  75         .grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
  76 };
  77
  78 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
  79 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
  80         .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
  81         .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
  82         .dram_cas = IMX6SDL_DRIVE_STRENGTH,
  83         .dram_ras = IMX6SDL_DRIVE_STRENGTH,
  84         .dram_reset = IMX6SDL_DRIVE_STRENGTH,
  85         .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
  86         .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
  87         .dram_sdba2 = 0x00000000,
  88         .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
  89         .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
  90         .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
  91         .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
  92         .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
  93         .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
  94         .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
  95         .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
  96         .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
  97         .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
  98         .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
  99         .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
 100         .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
 101         .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
 102         .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
 103         .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
 104         .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
 105         .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
 106 };
 107
 108 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
 109 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
 110         .grp_ddr_type = 0x000c0000,
 111         .grp_ddrmode_ctl = 0x00020000,
 112         .grp_ddrpke = 0x00000000,
 113         .grp_addds = IMX6SDL_DRIVE_STRENGTH,
 114         .grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
 115         .grp_ddrmode = 0x00020000,
 116         .grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
 117         .grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
 118         .grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
 119         .grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
 120         .grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
 121         .grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
 122         .grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
 123         .grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
 124 };
 125
 126 /* H5T04G63AFR-PB for i.mx6Solo/DL operating DDR at 400MHz */
 127 static struct mx6_ddr3_cfg h5t04g63afr = {
 128         .mem_speed = 800,
 129         .density = 4,
 130         .width = 16,
 131         .banks = 8,
 132         .rowaddr = 15,
 133         .coladdr = 10,
 134         .pagesz = 2,
 135         .trcd = 1500,
 136         .trcmin = 5250,
 137         .trasmin = 3750,
 138 };
 139
 140 /* H5TQ2G63FFR-H9 for i.mx6Solo/DL operating DDR at 400MHz */
 141 static struct mx6_ddr3_cfg h5tq2g63ffr = {
 142         .mem_speed = 800,
 143         .density = 2,
 144         .width = 16,
 145         .banks = 8,
 146         .rowaddr = 14,
 147         .coladdr = 10,
 148         .pagesz = 2,
 149         .trcd = 1500,
 150         .trcmin = 5250,
 151         .trasmin = 3750,
 152 };
 153
 154 static struct mx6_mmdc_calibration mx6q_1g_mmdc_calib = {
 155         .p0_mpwldectrl0 = 0x00000000,
 156         .p0_mpwldectrl1 = 0x00000000,
 157         .p1_mpwldectrl0 = 0x00000000,
 158         .p1_mpwldectrl1 = 0x00000000,
 159         .p0_mpdgctrl0 = 0x032C0340,
 160         .p0_mpdgctrl1 = 0x03300324,
 161         .p1_mpdgctrl0 = 0x032C0338,
 162         .p1_mpdgctrl1 = 0x03300274,
 163         .p0_mprddlctl = 0x423A383E,
 164         .p1_mprddlctl = 0x3638323E,
 165         .p0_mpwrdlctl = 0x363C4640,
 166         .p1_mpwrdlctl = 0x4034423C,
 167 };
 168
 169 /* DDR 32bit */
 170 static struct mx6_ddr_sysinfo mem_s = {
 171         .dsize          = 1,
 172         .cs1_mirror     = 0,
 173         /* config for full 4GB range so that get_mem_size() works */
 174         .cs_density     = 32,
 175         .ncs            = 1,
 176         .bi_on          = 1,
 177         .rtt_nom        = 1,
 178         .rtt_wr         = 0,
 179         .ralat          = 5,
 180         .walat          = 0,
 181         .mif3_mode      = 3,
 182         .rst_to_cke     = 0x23,
 183         .sde_to_rst     = 0x10,
 184 };
 185
 186 static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = {
 187         .p0_mpwldectrl0 = 0x001f001f,
 188         .p0_mpwldectrl1 = 0x001f001f,
 189         .p1_mpwldectrl0 = 0x001f001f,
 190         .p1_mpwldectrl1 = 0x001f001f,
 191         .p0_mpdgctrl0 = 0x420e020e,
 192         .p0_mpdgctrl1 = 0x02000200,
 193         .p1_mpdgctrl0 = 0x42020202,
 194         .p1_mpdgctrl1 = 0x01720172,
 195         .p0_mprddlctl = 0x494c4f4c,
 196         .p1_mprddlctl = 0x4a4c4c49,
 197         .p0_mpwrdlctl = 0x3f3f3133,
 198         .p1_mpwrdlctl = 0x39373f2e,
 199 };
 200
 201 static struct mx6_mmdc_calibration mx6s_512m_mmdc_calib = {
 202         .p0_mpwldectrl0 = 0x0040003c,
 203         .p0_mpwldectrl1 = 0x0032003e,
 204         .p0_mpdgctrl0 = 0x42350231,
 205         .p0_mpdgctrl1 = 0x021a0218,
 206         .p0_mprddlctl = 0x4b4b4e49,
 207         .p0_mpwrdlctl = 0x3f3f3035,
 208 };
 209
 210 static void ccgr_init(void)
 211 {
 212         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 213
 214         writel(0x00C03F3F, &ccm->CCGR0);
 215         writel(0x0030FC03, &ccm->CCGR1);
 216         writel(0x0FFFC000, &ccm->CCGR2);
 217         writel(0x3FF03000, &ccm->CCGR3);
 218         writel(0x00FFF300, &ccm->CCGR4);
 219         writel(0x0F0000C3, &ccm->CCGR5);
 220         writel(0x000003FF, &ccm->CCGR6);
 221 }
 222
 223 static void spl_dram_init(void)
 224 {
 225         if (is_mx6solo()) {
 226                 mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
 227                 mx6_dram_cfg(&mem_s, &mx6s_512m_mmdc_calib, &h5tq2g63ffr);
 228         } else if (is_mx6dl()) {
 229                 mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
 230                 mx6_dram_cfg(&mem_s, &mx6dl_1g_mmdc_calib, &h5t04g63afr);
 231         } else if (is_mx6dq()) {
 232                 mx6dq_dram_iocfg(32, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
 233                 mx6_dram_cfg(&mem_s, &mx6q_1g_mmdc_calib, &h5t04g63afr);
 234         }
 235
 236         udelay(100);
 237 }
 238
 239 void board_init_f(ulong dummy)
 240 {
 241         ccgr_init();
 242
 243         /* setup AIPS and disable watchdog */
 244         arch_cpu_init();
 245
 246         gpr_init();
 247
 248         /* iomux */
 249         board_early_init_f();
 250
 251         /* setup GP timer */
 252         timer_init();
 253
 254         /* UART clocks enabled and gd valid - init serial console */
 255         preloader_console_init();
 256
 257         /* DDR initialization */
 258         spl_dram_init();
 259 }
 260
 261 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
 262         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
 263         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 264
 265 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
 266         {USDHC3_BASE_ADDR},
 267 };
 268
 269 static iomux_v3_cfg_t const usdhc3_pads[] = {
 270         IOMUX_PADS(PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 271         IOMUX_PADS(PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 272         IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 273         IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 274         IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 275         IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 276         /* SOM MicroSD Card Detect */
 277         IOMUX_PADS(PAD_EIM_DA9__GPIO3_IO09  | MUX_PAD_CTRL(NO_PAD_CTRL)),
 278 };
 279
 280 int board_mmc_getcd(struct mmc *mmc)
 281 {
 282         return 1;
 283 }
 284
 285 int board_mmc_init(bd_t *bis)
 286 {
 287         SETUP_IOMUX_PADS(usdhc3_pads);
 288         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 289         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 290 }
 291 #endif
 292
 293 #ifdef CONFIG_SPL_LOAD_FIT
 294 int board_fit_config_name_match(const char *name)
 295 {
 296         if (is_mx6dq() && !strcmp(name, "imx6q-pico"))
 297                 return 0;
 298         else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-pico"))
 299                 return 0;
 300
 301         return -EINVAL;
 302 }
 303 #endif