1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2013 Freescale Semiconductor, Inc.
4 * Copyright (C) 2014 O.S. Systems Software LTDA.
6 * Author: Fabio Estevam <festevam@gmail.com>
9 #include <asm/arch/clock.h>
10 #include <asm/arch/crm_regs.h>
11 #include <asm/arch/iomux.h>
12 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/mx6-pins.h>
14 #include <asm/arch/sys_proto.h>
16 #include <asm/mach-imx/iomux-v3.h>
18 #include <linux/sizes.h>
24 DECLARE_GLOBAL_DATA_PTR;
26 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
27 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
28 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
30 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
31 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
33 #define ETH_PHY_RESET IMX_GPIO_NR(1, 26)
37 gd->ram_size = imx_ddr_size();
42 static iomux_v3_cfg_t const uart1_pads[] = {
43 IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
44 IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
47 static void setup_iomux_uart(void)
49 SETUP_IOMUX_PADS(uart1_pads);
52 static iomux_v3_cfg_t const enet_pads[] = {
53 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
54 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
55 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
56 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
57 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
58 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
59 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
60 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
61 MUX_PAD_CTRL(ENET_PAD_CTRL)),
62 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
63 MUX_PAD_CTRL(ENET_PAD_CTRL)),
64 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
65 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
66 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
67 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
68 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
69 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
70 /* AR8035 PHY Reset */
71 IOMUX_PADS(PAD_ENET_RXD1__GPIO1_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL)),
74 static void setup_iomux_enet(void)
76 SETUP_IOMUX_PADS(enet_pads);
78 /* Reset AR8031 PHY */
79 gpio_request(ETH_PHY_RESET, "enet_phy_reset");
80 gpio_direction_output(ETH_PHY_RESET, 0);
82 gpio_set_value(ETH_PHY_RESET, 1);
85 int board_early_init_f(void)
92 int board_eth_init(bd_t *bis)
96 return cpu_eth_init(bis);
99 int board_phy_config(struct phy_device *phydev)
103 /* To enable AR8035 ouput a 125MHz clk from CLK_25M */
104 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
105 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
106 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
108 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
111 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
113 /* introduce tx clock delay */
114 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
115 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
117 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
119 if (phydev->drv->config)
120 phydev->drv->config(phydev);
125 int overwrite_console(void)
130 int board_late_init(void)
133 env_set("board_rev", "MX6Q");
135 env_set("board_rev", "MX6DL");
142 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
149 puts("Board: PICO-IMX6\n");