3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <asm-offsets.h>
25 #include <ppc_asm.tmpl>
32 * This table is used by the cpu boot code to setup the initial tlb
33 * entries. Rather than make broad assumptions in the cpu source tree,
34 * this table lets each board set things up however they like.
36 * Pointer to the table is returned in r1
46 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to
47 * use the speed up boot process. It is patched after relocation to
50 tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M,
51 CONFIG_SYS_BOOT_BASE_ADDR, 4, AC_RWX | SA_G)
54 * TLB entries for SDRAM are not needed on this platform.
55 * They are dynamically generated in the DDR(2) detection
59 #ifdef CONFIG_SYS_INIT_RAM_DCACHE
60 /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
61 tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0,
65 tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xc,
67 tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x20000000, 0xc,
69 tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xd,
72 tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xd,
74 tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xd,
76 tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xd,
78 tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xd,
81 /* PCIe UTL register */
82 tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x08010000, 0xc, AC_RW | SA_IG)
84 /* TLB-entry for FPGA(s) */
85 tlbentry(CONFIG_SYS_FPGA1_BASE, SZ_16M, CONFIG_SYS_FPGA1_BASE, 4,
87 tlbentry(CONFIG_SYS_FPGA1_BASE + (16 << 20), SZ_16M,
88 CONFIG_SYS_FPGA1_BASE + (16 << 20), 4, AC_RW | SA_IG)
89 tlbentry(CONFIG_SYS_FPGA2_BASE, SZ_16M, CONFIG_SYS_FPGA2_BASE, 4,
91 tlbentry(CONFIG_SYS_FPGA3_BASE, SZ_16M, CONFIG_SYS_FPGA3_BASE, 4,
94 /* TLB-entry for OCM */
95 tlbentry(CONFIG_SYS_OCM_BASE, SZ_1M, 0x00000000, 4,
98 /* TLB-entry for Local Configuration registers => peripherals */
99 tlbentry(CONFIG_SYS_LOCAL_CONF_REGS, SZ_16M,
100 CONFIG_SYS_LOCAL_CONF_REGS, 4, AC_RWX | SA_IG)