1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Matthias Weisser <weisserm@arcor.de>
6 * (C) Copyright 2009 DENX Software Engineering
7 * Author: John Rigby <jrigby@gmail.com>
9 * Based on U-Boot and RedBoot sources for several different i.mx
13 #include <asm/macro.h>
14 #include <asm/arch/macro.h>
15 #include <asm/arch/imx-regs.h>
16 #include <generated/asm-offsets.h>
23 /* disable clock output */
24 write32 IMX_CCM_BASE + CCM_MCR, 0x00000000
25 write32 IMX_CCM_BASE + CCM_CCTL, 0x50030000
28 * enable all implemented clocks in all three
29 * clock control registers
31 write32 IMX_CCM_BASE + CCM_CGCR0, 0x1fffffff
32 write32 IMX_CCM_BASE + CCM_CGCR1, 0xffffffff
33 write32 IMX_CCM_BASE + CCM_CGCR2, 0xfffff
35 /* Devide NAND clock by 32 */
36 write32 IMX_CCM_BASE + CCM_PCDR2, 0x0101011F
40 * sdram controller init
43 ldr r0, =IMX_ESDRAMC_BASE
44 ldr r2, =IMX_SDRAM_BANK0_BASE
47 * reset SDRAM controller
48 * then wait for initialization to complete
50 ldr r1, =(1 << 1) | (1 << 2)
51 str r1, [r0, #ESDRAMC_ESDMISC]
52 1: ldr r3, [r0, #ESDRAMC_ESDMISC]
56 str r1, [r0, #ESDRAMC_ESDMISC]
59 str r1, [r0, #ESDRAMC_ESDCFG0]
61 /* control | precharge */
63 str r1, [r0, #ESDRAMC_ESDCTL0]
64 /* dram command encoded in address */
69 str r1, [r0, #ESDRAMC_ESDCTL0]
70 /* read dram twice to auto refresh */
74 /* control | load mode */
76 str r1, [r0, #ESDRAMC_ESDCTL0]
78 /* mode register of lpddram */
81 /* extended mode register of lpddrram */
85 /* control | normal */
87 str r1, [r0, #ESDRAMC_ESDCTL0]