3 * Matthias Weisser <weisserm@arcor.de>
5 * (C) Copyright 2009 DENX Software Engineering
6 * Author: John Rigby <jrigby@gmail.com>
8 * Based on U-Boot and RedBoot sources for several different i.mx
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/macro.h>
28 #include <asm/arch/macro.h>
29 #include <asm/arch/imx-regs.h>
30 #include <generated/asm-offsets.h>
37 /* disable clock output */
38 write32 IMX_CCM_BASE + CCM_MCR, 0x00000000
39 write32 IMX_CCM_BASE + CCM_CCTL, 0x50030000
42 * enable all implemented clocks in all three
43 * clock control registers
45 write32 IMX_CCM_BASE + CCM_CGCR0, 0x1fffffff
46 write32 IMX_CCM_BASE + CCM_CGCR1, 0xffffffff
47 write32 IMX_CCM_BASE + CCM_CGCR2, 0xfffff
49 /* Devide NAND clock by 32 */
50 write32 IMX_CCM_BASE + CCM_PCDR2, 0x0101011F
54 * sdram controller init
57 ldr r0, =IMX_ESDRAMC_BASE
58 ldr r2, =IMX_SDRAM_BANK0_BASE
61 * reset SDRAM controller
62 * then wait for initialization to complete
64 ldr r1, =(1 << 1) | (1 << 2)
65 str r1, [r0, #ESDRAMC_ESDMISC]
66 1: ldr r3, [r0, #ESDRAMC_ESDMISC]
70 str r1, [r0, #ESDRAMC_ESDMISC]
73 str r1, [r0, #ESDRAMC_ESDCFG0]
75 /* control | precharge */
77 str r1, [r0, #ESDRAMC_ESDCTL0]
78 /* dram command encoded in address */
83 str r1, [r0, #ESDRAMC_ESDCTL0]
84 /* read dram twice to auto refresh */
88 /* control | load mode */
90 str r1, [r0, #ESDRAMC_ESDCTL0]
92 /* mode register of lpddram */
95 /* extended mode register of lpddrram */
99 /* control | normal */
101 str r1, [r0, #ESDRAMC_ESDCTL0]