2 * Board functions for Sysam AMCORE (MCF5307 based) board
4 * (C) Copyright 2015 Angelo Dureghello <angelo@sysam.it>
6 * SPDX-License-Identifier: GPL-2.0+
8 * This file copies memory testdram() from sandburst/common/sb_common.c
12 #include <asm/immap.h>
17 /* setup for possible K0108 lcd connected on the parallel port */
18 sim_t *sim = (sim_t *)(MMAP_SIM);
20 out_be16(&sim->par, 0x300);
22 gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
24 out_be16(&gpio->paddr, 0xfcff);
25 out_be16(&gpio->padat, 0x0c00);
31 puts("AMCORE v.001(alpha)\n");
39 * in initdram we are here executing from flash
41 * is with no ACR/flash cache enabled
42 * nop = 40ns (scope measured)
44 void fudelay(int usec)
50 phys_size_t initdram(int board_type)
54 sdramctrl_t *dc = (sdramctrl_t *)(MMAP_DRAMC);
57 * SDRAM MT48LC4M32B2 details
58 * Memory block 0: 16 MB of SDRAM at address $00000000
59 * Port size: 32-bit port
61 * Memory block 0 wired as follows:
62 * CPU : A15 A14 A13 A12 A11 A10 A9 A17 A18 A19 A20 A21 A22 A23
63 * SDRAM : A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 BA0 BA1
65 * Ensure that there is a delay of at least 100 microseconds from
66 * processor reset to the following code so that the SDRAM is ready
73 * set proper RC as per specification
75 RC = (CONFIG_SYS_CPU_CLK / 1000000) >> 1;
78 /* 0x8000 is the faster option */
79 out_be16(&dc->dcr, 0x8200 | RC);
82 * DACR0, page mode continuous, CMD on A20 0x0300
84 out_be32(&dc->dacr0, 0x00003304);
86 dramsize = ((CONFIG_SYS_SDRAM_SIZE)-1) & 0xfffc0000;
87 out_be32(&dc->dmr0, dramsize|1);
89 /* issue a PRECHARGE ALL */
90 out_be32(&dc->dacr0, 0x0000330c);
91 out_be32((u32 *)0x00000004, 0xbeaddeed);
92 /* issue AUTOREFRESH */
93 out_be32(&dc->dacr0, 0x0000b304);
94 /* let refresh occour */
97 out_be32(&dc->dacr0, 0x0000b344);
98 out_be32((u32 *)0x00000c00, 0xbeaddeed);
100 return get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_SIZE);