1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2018 Synopsys, Inc. All rights reserved.
9 #include <linux/libfdt.h>
12 #include <asm/arcregs.h>
14 DECLARE_GLOBAL_DATA_PTR;
16 #define SYSCON_BASE 0xf000a000
17 #define AHBCKDIV (void *)(SYSCON_BASE + 0x04)
18 #define APBCKDIV (void *)(SYSCON_BASE + 0x08)
19 #define APBCKEN (void *)(SYSCON_BASE + 0x0C)
20 #define RESET_REG (void *)(SYSCON_BASE + 0x18)
21 #define CLKSEL (void *)(SYSCON_BASE + 0x24)
22 #define CLKSTAT (void *)(SYSCON_BASE + 0x28)
23 #define PLLCON (void *)(SYSCON_BASE + 0x2C)
24 #define APBCKSEL (void *)(SYSCON_BASE + 0x30)
25 #define AHBCKEN (void *)(SYSCON_BASE + 0x34)
26 #define USBPHY_PLL (void *)(SYSCON_BASE + 0x78)
27 #define USBCFG (void *)(SYSCON_BASE + 0x7c)
29 #define PLL_MASK_0 0xffcfffff
30 #define PLL_MASK_1 0xffcfff00
31 #define PLL_MASK_2 0xfbcfff00
33 #define CLKSEL_DEFAULT 0x5a690000
35 static int set_cpu_freq(unsigned int clk)
39 /* Set clk to ext Xtal (LSN value 0) */
40 writel(CLKSEL_DEFAULT, CLKSEL);
48 writel(readl(PLLCON) & PLL_MASK_0, PLLCON);
49 /* pll_off=1, M=25, N=1, OD=3, PLL_OUT_CLK=50M */
50 writel((readl(PLLCON) & PLL_MASK_1) | 0x300191, PLLCON);
51 /* pll_off=0, M=25, N=1, OD=3, PLL_OUT_CLK=50M */
52 writel((readl(PLLCON) & PLL_MASK_2) | 0x300191, PLLCON);
56 writel(readl(PLLCON) & PLL_MASK_0, PLLCON);
57 /* pll_off=1, M=18, N=1, OD=2, PLL_OUT_CLK=72M */
58 writel((readl(PLLCON) & PLL_MASK_1) | 0x200121, PLLCON);
59 /* pll_off=0, M=18, N=1, OD=2, PLL_OUT_CLK=72M */
60 writel((readl(PLLCON) & PLL_MASK_2) | 0x200121, PLLCON);
64 writel(readl(PLLCON) & PLL_MASK_0, PLLCON);
65 /* pll_off=1,M=25, N=1, OD=2, PLL_OUT_CLK=100M */
66 writel((readl(PLLCON) & PLL_MASK_1) | 0x200191, PLLCON);
67 /* pll_off=0,M=25, N=1, OD=2, PLL_OUT_CLK=100M */
68 writel((readl(PLLCON) & PLL_MASK_2) | 0x200191, PLLCON);
72 writel(readl(PLLCON) & PLL_MASK_0, PLLCON);
73 /* pll_off=1, M=18, N=1, OD=1, PLL_OUT_CLK=144M */
74 writel((readl(PLLCON) & PLL_MASK_1) | 0x100121, PLLCON);
75 /* pll_off=0, M=18, N=1, OD=1, PLL_OUT_CLK=144M */
76 writel((readl(PLLCON) & PLL_MASK_2) | 0x100121, PLLCON);
83 while (!(readl(CLKSTAT) & 0x4))
86 /* Set clk from PLL on bus (LSN = 1) */
87 writel(CLKSEL_DEFAULT | BIT(0), CLKSEL);
92 extern u8 __rom_end[];
93 extern u8 __ram_start[];
94 extern u8 __ram_end[];
97 * Use mach_cpu_init() for .data section copy as board_early_init_f() will be
98 * too late: initf_dm() will use a value of "av_" variable from not yet
99 * initialized (by copy) area.
101 int mach_cpu_init(void)
105 /* Don't relocate U-Boot */
106 gd->flags |= GD_FLG_SKIP_RELOC;
108 /* Copy data from ROM to RAM */
110 u8 *dst = __ram_start;
112 while (dst < __ram_end)
115 /* Enable debug uart */
116 #define DEBUG_UART_BASE 0x80014000
117 #define DEBUG_UART_DLF_OFFSET 0xc0
118 write_aux_reg(DEBUG_UART_BASE + DEBUG_UART_DLF_OFFSET, 1);
120 offset = fdt_path_offset(gd->fdt_blob, "/cpu_card/core_clk");
124 freq = fdtdec_get_int(gd->fdt_blob, offset, "clock-frequency", 0);
128 /* If CPU freq > 100 MHz, divide eFLASH clock by 2 */
129 if (freq > 100000000) {
130 u32 reg = readl(AHBCKDIV);
134 writel(reg, AHBCKDIV);
137 return set_cpu_freq(freq);
140 #define ARC_PERIPHERAL_BASE 0xF0000000
141 #define SDIO_BASE (ARC_PERIPHERAL_BASE + 0xB000)
143 int board_mmc_init(bd_t *bis)
145 struct dwmci_host *host = NULL;
147 host = malloc(sizeof(struct dwmci_host));
149 printf("dwmci_host malloc fail!\n");
153 memset(host, 0, sizeof(struct dwmci_host));
154 host->name = "Synopsys Mobile storage";
155 host->ioaddr = (void *)SDIO_BASE;
158 host->bus_hz = 50000000;
160 add_dwmci(host, host->bus_hz / 2, 400000);
165 #define IOTDK_RESET_SEQ 0x55AA6699
167 void reset_cpu(ulong addr)
169 writel(IOTDK_RESET_SEQ, RESET_REG);
174 puts("Board: Synopsys IoT Development Kit\n");
178 #ifdef CONFIG_DISPLAY_CPUINFO
179 int print_cpuinfo(void)
181 printf("CPU: ARC EM9D\n");
184 #endif /* CONFIG_DISPLAY_CPUINFO */