1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2018 Synopsys, Inc. All rights reserved.
4 * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
13 #include <linux/printk.h>
14 #include <linux/kernel.h>
16 #include <asm/arcregs.h>
17 #include <fdt_support.h>
25 DECLARE_GLOBAL_DATA_PTR;
27 #define ALL_CPU_MASK GENMASK(NR_CPUS - 1, 0)
28 #define MASTER_CPU_ID 0
29 #define APERTURE_SHIFT 28
31 #define SLAVE_CPU_READY 0x12345678
32 #define BOOTSTAGE_1 1 /* after SP, FP setup, before HW init */
33 #define BOOTSTAGE_2 2 /* after HW init, before self halt */
34 #define BOOTSTAGE_3 3 /* after self halt */
35 #define BOOTSTAGE_4 4 /* before app launch */
36 #define BOOTSTAGE_5 5 /* after app launch, unreachable */
38 #define RESET_VECTOR_ADDR 0x0
40 #define CREG_BASE (ARC_PERIPHERAL_BASE + 0x1000)
41 #define CREG_CPU_START (CREG_BASE + 0x400)
42 #define CREG_CPU_START_MASK 0xF
44 #define SDIO_BASE (ARC_PERIPHERAL_BASE + 0xA000)
45 #define SDIO_UHS_REG_EXT (SDIO_BASE + 0x108)
46 #define SDIO_UHS_REG_EXT_DIV_2 (2 << 30)
48 /* Uncached access macros */
49 #define arc_read_uncached_32(ptr) \
52 __asm__ __volatile__( \
53 " ld.di %0, [%1] \n" \
59 #define arc_write_uncached_32(ptr, data)\
61 __asm__ __volatile__( \
62 " st.di %0, [%1] \n" \
64 : "r"(data), "r"(ptr)); \
67 struct hsdk_env_core_ctl {
68 u32_env entry[NR_CPUS];
69 u32_env iccm[NR_CPUS];
70 u32_env dccm[NR_CPUS];
73 struct hsdk_env_common_ctl {
85 * Uncached cross-cpu structure. All CPUs must access to this structure fields
86 * only with arc_read_uncached_32() / arc_write_uncached_32() accessors (which
87 * implement ld.di / st.di instructions). Simultaneous cached and uncached
88 * access to this area will lead to data loss.
89 * We flush all data caches in board_early_init_r() as we don't want to have
90 * any dirty line in L1d$ or SL$ in this area.
92 struct hsdk_cross_cpu {
93 /* slave CPU ready flag */
95 /* address of the area, which can be used for stack by slave CPU */
97 /* slave CPU status - bootstage number */
101 * Slave CPU data - it is copy of corresponding fields in
102 * hsdk_env_core_ctl and hsdk_env_common_ctl structures which are
103 * required for slave CPUs initialization.
104 * This fields can be populated by copying from hsdk_env_core_ctl
105 * and hsdk_env_common_ctl structures with sync_cross_cpu_data()
116 u8 cache_padding[ARCH_DMA_MINALIGN];
117 } __aligned(ARCH_DMA_MINALIGN);
119 /* Place for slave CPUs temporary stack */
120 static u32 slave_stack[256 * NR_CPUS] __aligned(ARCH_DMA_MINALIGN);
122 static struct hsdk_env_common_ctl env_common = {};
123 static struct hsdk_env_core_ctl env_core = {};
124 static struct hsdk_cross_cpu cross_cpu_data;
126 static const struct env_map_common env_map_common[] = {
127 { "core_mask", ENV_HEX, true, 0x1, 0xF, &env_common.core_mask },
128 { "non_volatile_limit", ENV_HEX, true, 0, 0xF, &env_common.nvlim },
129 { "icache_ena", ENV_HEX, true, 0, 1, &env_common.icache },
130 { "dcache_ena", ENV_HEX, true, 0, 1, &env_common.dcache },
134 static const struct env_map_common env_map_clock[] = {
135 { "cpu_freq", ENV_DEC, false, 100, 1000, &env_common.cpu_freq },
136 { "axi_freq", ENV_DEC, false, 200, 800, &env_common.axi_freq },
137 { "tun_freq", ENV_DEC, false, 0, 150, &env_common.tun_freq },
141 static const struct env_map_percpu env_map_core[] = {
142 { "core_iccm", ENV_HEX, true, {NO_CCM, 0, NO_CCM, 0}, {NO_CCM, 0xF, NO_CCM, 0xF}, &env_core.iccm },
143 { "core_dccm", ENV_HEX, true, {NO_CCM, 0, NO_CCM, 0}, {NO_CCM, 0xF, NO_CCM, 0xF}, &env_core.dccm },
147 static const struct env_map_common env_map_mask[] = {
148 { "core_mask", ENV_HEX, false, 0x1, 0xF, &env_common.core_mask },
152 static const struct env_map_percpu env_map_go[] = {
153 { "core_entry", ENV_HEX, true, {0, 0, 0, 0}, {U32_MAX, U32_MAX, U32_MAX, U32_MAX}, &env_core.entry },
163 static inline enum board_type get_board_type_runtime(void)
165 u32 arc_id = read_aux_reg(ARC_AUX_IDENTITY) & 0xFF;
169 else if (arc_id == 0x54)
170 return T_BOARD_HSDK_4XD;
175 static inline enum board_type get_board_type_config(void)
177 if (IS_ENABLED(CONFIG_BOARD_HSDK))
179 else if (IS_ENABLED(CONFIG_BOARD_HSDK_4XD))
180 return T_BOARD_HSDK_4XD;
185 static bool is_board_match_runtime(enum board_type type_req)
187 return get_board_type_runtime() == type_req;
190 static const char * board_name(enum board_type type)
194 return "ARC HS Development Kit";
195 case T_BOARD_HSDK_4XD:
196 return "ARC HS4x/HS4xD Development Kit";
202 static bool board_mismatch(void)
204 return get_board_type_config() != get_board_type_runtime();
207 static void sync_cross_cpu_data(void)
211 for (u32 i = 0; i < NR_CPUS; i++) {
212 value = env_core.entry[i].val;
213 arc_write_uncached_32(&cross_cpu_data.entry[i], value);
216 for (u32 i = 0; i < NR_CPUS; i++) {
217 value = env_core.iccm[i].val;
218 arc_write_uncached_32(&cross_cpu_data.iccm[i], value);
221 for (u32 i = 0; i < NR_CPUS; i++) {
222 value = env_core.dccm[i].val;
223 arc_write_uncached_32(&cross_cpu_data.dccm[i], value);
226 value = env_common.core_mask.val;
227 arc_write_uncached_32(&cross_cpu_data.core_mask, value);
229 value = env_common.icache.val;
230 arc_write_uncached_32(&cross_cpu_data.icache, value);
232 value = env_common.dcache.val;
233 arc_write_uncached_32(&cross_cpu_data.dcache, value);
236 /* Can be used only on master CPU */
237 static bool is_cpu_used(u32 cpu_id)
239 return !!(env_common.core_mask.val & BIT(cpu_id));
242 /* TODO: add ICCM BCR and DCCM BCR runtime check */
243 static void init_slave_cpu_func(u32 core)
247 /* Remap ICCM to another memory region if it exists */
248 val = arc_read_uncached_32(&cross_cpu_data.iccm[core]);
250 write_aux_reg(ARC_AUX_ICCM_BASE, val << APERTURE_SHIFT);
252 /* Remap DCCM to another memory region if it exists */
253 val = arc_read_uncached_32(&cross_cpu_data.dccm[core]);
255 write_aux_reg(ARC_AUX_DCCM_BASE, val << APERTURE_SHIFT);
257 if (arc_read_uncached_32(&cross_cpu_data.icache))
262 if (arc_read_uncached_32(&cross_cpu_data.dcache))
268 static void init_cluster_nvlim(void)
270 u32 val = env_common.nvlim.val << APERTURE_SHIFT;
273 write_aux_reg(ARC_AUX_NON_VOLATILE_LIMIT, val);
274 /* AUX_AUX_CACHE_LIMIT reg is missing starting from HS48 */
275 if (is_board_match_runtime(T_BOARD_HSDK))
276 write_aux_reg(AUX_AUX_CACHE_LIMIT, val);
277 flush_n_invalidate_dcache_all();
280 static void init_master_icache(void)
282 if (icache_status()) {
283 /* I$ is enabled - we need to disable it */
284 if (!env_common.icache.val)
287 /* I$ is disabled - we need to enable it */
288 if (env_common.icache.val) {
291 /* invalidate I$ right after enable */
292 invalidate_icache_all();
297 static void init_master_dcache(void)
299 if (dcache_status()) {
300 /* D$ is enabled - we need to disable it */
301 if (!env_common.dcache.val)
304 /* D$ is disabled - we need to enable it */
305 if (env_common.dcache.val)
308 /* TODO: probably we need ti invalidate D$ right after enable */
312 static int cleanup_before_go(void)
314 disable_interrupts();
315 sync_n_cleanup_cache_all();
320 void slave_cpu_set_boot_addr(u32 addr)
322 /* All cores have reset vector pointing to 0 */
323 writel(addr, (void __iomem *)RESET_VECTOR_ADDR);
325 /* Make sure other cores see written value in memory */
326 sync_n_cleanup_cache_all();
329 static inline void halt_this_cpu(void)
331 __builtin_arc_flag(1);
334 static void smp_kick_cpu_x(u32 cpu_id)
336 int cmd = readl((void __iomem *)CREG_CPU_START);
338 if (cpu_id > NR_CPUS)
341 cmd &= ~CREG_CPU_START_MASK;
342 cmd |= (1 << cpu_id);
343 writel(cmd, (void __iomem *)CREG_CPU_START);
346 static u32 prepare_cpu_ctart_reg(void)
348 int cmd = readl((void __iomem *)CREG_CPU_START);
350 cmd &= ~CREG_CPU_START_MASK;
352 return cmd | env_common.core_mask.val;
355 /* slave CPU entry for configuration */
356 __attribute__((naked, noreturn, flatten)) noinline void hsdk_core_init_f(void)
358 __asm__ __volatile__(
363 : "r" (&cross_cpu_data.stack_ptr));
365 invalidate_icache_all();
367 arc_write_uncached_32(&cross_cpu_data.status[CPU_ID_GET()], BOOTSTAGE_1);
368 init_slave_cpu_func(CPU_ID_GET());
370 arc_write_uncached_32(&cross_cpu_data.ready_flag, SLAVE_CPU_READY);
371 arc_write_uncached_32(&cross_cpu_data.status[CPU_ID_GET()], BOOTSTAGE_2);
373 /* Halt the processor until the master kick us again */
377 * 3 NOPs after FLAG 1 instruction are no longer required for ARCv2
378 * cores but we leave them for gebug purposes.
384 arc_write_uncached_32(&cross_cpu_data.status[CPU_ID_GET()], BOOTSTAGE_3);
386 /* get the updated entry - invalidate i$ */
387 invalidate_icache_all();
389 arc_write_uncached_32(&cross_cpu_data.status[CPU_ID_GET()], BOOTSTAGE_4);
391 /* Run our program */
392 ((void (*)(void))(arc_read_uncached_32(&cross_cpu_data.entry[CPU_ID_GET()])))();
394 /* This bootstage is unreachable as we don't return from app we launch */
395 arc_write_uncached_32(&cross_cpu_data.status[CPU_ID_GET()], BOOTSTAGE_5);
397 /* Something went terribly wrong */
402 static void clear_cross_cpu_data(void)
404 arc_write_uncached_32(&cross_cpu_data.ready_flag, 0);
405 arc_write_uncached_32(&cross_cpu_data.stack_ptr, 0);
407 for (u32 i = 0; i < NR_CPUS; i++)
408 arc_write_uncached_32(&cross_cpu_data.status[i], 0);
411 static noinline void do_init_slave_cpu(u32 cpu_id)
413 /* attempts number for check clave CPU ready_flag */
415 u32 stack_ptr = (u32)(slave_stack + (64 * cpu_id));
417 if (cpu_id >= NR_CPUS)
420 arc_write_uncached_32(&cross_cpu_data.ready_flag, 0);
422 /* Use global unique place for each slave cpu stack */
423 arc_write_uncached_32(&cross_cpu_data.stack_ptr, stack_ptr);
425 debug("CPU %u: stack pool base: %p\n", cpu_id, slave_stack);
426 debug("CPU %u: current slave stack base: %x\n", cpu_id, stack_ptr);
427 slave_cpu_set_boot_addr((u32)hsdk_core_init_f);
429 smp_kick_cpu_x(cpu_id);
431 debug("CPU %u: cross-cpu flag: %x [before timeout]\n", cpu_id,
432 arc_read_uncached_32(&cross_cpu_data.ready_flag));
434 while (!arc_read_uncached_32(&cross_cpu_data.ready_flag) && attempts--)
437 /* Just to be sure that slave cpu is halted after it set ready_flag */
441 * Only print error here if we reach timeout as there is no option to
442 * halt slave cpu (or check that slave cpu is halted)
445 pr_err("CPU %u is not responding after init!\n", cpu_id);
447 /* Check current stage of slave cpu */
448 if (arc_read_uncached_32(&cross_cpu_data.status[cpu_id]) != BOOTSTAGE_2)
449 pr_err("CPU %u status is unexpected: %d\n", cpu_id,
450 arc_read_uncached_32(&cross_cpu_data.status[cpu_id]));
452 debug("CPU %u: cross-cpu flag: %x [after timeout]\n", cpu_id,
453 arc_read_uncached_32(&cross_cpu_data.ready_flag));
454 debug("CPU %u: status: %d [after timeout]\n", cpu_id,
455 arc_read_uncached_32(&cross_cpu_data.status[cpu_id]));
458 static void do_init_slave_cpus(void)
460 clear_cross_cpu_data();
461 sync_cross_cpu_data();
463 debug("cross_cpu_data location: %#x\n", (u32)&cross_cpu_data);
465 for (u32 i = MASTER_CPU_ID + 1; i < NR_CPUS; i++)
467 do_init_slave_cpu(i);
470 static void do_init_master_cpu(void)
473 * Setup master caches even if master isn't used as we want to use
474 * same cache configuration on all running CPUs
476 init_master_icache();
477 init_master_dcache();
480 enum hsdk_axi_masters {
498 * m master AXI_M_m_SLV0 AXI_M_m_SLV1 AXI_M_m_OFFSET0 AXI_M_m_OFFSET1
499 * 0 HS (CBU) 0x11111111 0x63111111 0xFEDCBA98 0x0E543210
500 * 1 HS (RTT) 0x77777777 0x77777777 0xFEDCBA98 0x76543210
501 * 2 AXI Tunnel 0x88888888 0x88888888 0xFEDCBA98 0x76543210
502 * 3 HDMI-VIDEO 0x77777777 0x77777777 0xFEDCBA98 0x76543210
503 * 4 HDMI-ADUIO 0x77777777 0x77777777 0xFEDCBA98 0x76543210
504 * 5 USB-HOST 0x77777777 0x77999999 0xFEDCBA98 0x76DCBA98
505 * 6 ETHERNET 0x77777777 0x77999999 0xFEDCBA98 0x76DCBA98
506 * 7 SDIO 0x77777777 0x77999999 0xFEDCBA98 0x76DCBA98
507 * 8 GPU 0x77777777 0x77777777 0xFEDCBA98 0x76543210
508 * 9 DMAC (port #1) 0x77777777 0x77777777 0xFEDCBA98 0x76543210
509 * 10 DMAC (port #2) 0x77777777 0x77777777 0xFEDCBA98 0x76543210
510 * 11 DVFS 0x00000000 0x60000000 0x00000000 0x00000000
512 * Please read ARC HS Development IC Specification, section 17.2 for more
513 * information about apertures configuration.
514 * NOTE: we intentionally modify default settings in U-boot. Default settings
515 * are specified in "Table 111 CREG Address Decoder register reset values".
518 #define CREG_AXI_M_SLV0(m) ((void __iomem *)(CREG_BASE + 0x020 * (m)))
519 #define CREG_AXI_M_SLV1(m) ((void __iomem *)(CREG_BASE + 0x020 * (m) + 0x004))
520 #define CREG_AXI_M_OFT0(m) ((void __iomem *)(CREG_BASE + 0x020 * (m) + 0x008))
521 #define CREG_AXI_M_OFT1(m) ((void __iomem *)(CREG_BASE + 0x020 * (m) + 0x00C))
522 #define CREG_AXI_M_UPDT(m) ((void __iomem *)(CREG_BASE + 0x020 * (m) + 0x014))
524 #define CREG_AXI_M_HS_CORE_BOOT ((void __iomem *)(CREG_BASE + 0x010))
526 #define CREG_PAE ((void __iomem *)(CREG_BASE + 0x180))
527 #define CREG_PAE_UPDT ((void __iomem *)(CREG_BASE + 0x194))
529 void init_memory_bridge(void)
534 * M_HS_CORE has one unic register - BOOT.
535 * We need to clean boot mirror (BOOT[1:0]) bits in them.
537 reg = readl(CREG_AXI_M_HS_CORE_BOOT) & (~0x3);
538 writel(reg, CREG_AXI_M_HS_CORE_BOOT);
539 writel(0x11111111, CREG_AXI_M_SLV0(M_HS_CORE));
540 writel(0x63111111, CREG_AXI_M_SLV1(M_HS_CORE));
541 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_CORE));
542 writel(0x0E543210, CREG_AXI_M_OFT1(M_HS_CORE));
543 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_CORE));
545 writel(0x77777777, CREG_AXI_M_SLV0(M_HS_RTT));
546 writel(0x77777777, CREG_AXI_M_SLV1(M_HS_RTT));
547 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_RTT));
548 writel(0x76543210, CREG_AXI_M_OFT1(M_HS_RTT));
549 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_RTT));
551 writel(0x88888888, CREG_AXI_M_SLV0(M_AXI_TUN));
552 writel(0x88888888, CREG_AXI_M_SLV1(M_AXI_TUN));
553 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_AXI_TUN));
554 writel(0x76543210, CREG_AXI_M_OFT1(M_AXI_TUN));
555 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_AXI_TUN));
557 writel(0x77777777, CREG_AXI_M_SLV0(M_HDMI_VIDEO));
558 writel(0x77777777, CREG_AXI_M_SLV1(M_HDMI_VIDEO));
559 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HDMI_VIDEO));
560 writel(0x76543210, CREG_AXI_M_OFT1(M_HDMI_VIDEO));
561 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HDMI_VIDEO));
563 writel(0x77777777, CREG_AXI_M_SLV0(M_HDMI_AUDIO));
564 writel(0x77777777, CREG_AXI_M_SLV1(M_HDMI_AUDIO));
565 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HDMI_AUDIO));
566 writel(0x76543210, CREG_AXI_M_OFT1(M_HDMI_AUDIO));
567 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HDMI_AUDIO));
569 writel(0x77777777, CREG_AXI_M_SLV0(M_USB_HOST));
570 writel(0x77999999, CREG_AXI_M_SLV1(M_USB_HOST));
571 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_USB_HOST));
572 writel(0x76DCBA98, CREG_AXI_M_OFT1(M_USB_HOST));
573 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_USB_HOST));
575 writel(0x77777777, CREG_AXI_M_SLV0(M_ETHERNET));
576 writel(0x77999999, CREG_AXI_M_SLV1(M_ETHERNET));
577 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_ETHERNET));
578 writel(0x76DCBA98, CREG_AXI_M_OFT1(M_ETHERNET));
579 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_ETHERNET));
581 writel(0x77777777, CREG_AXI_M_SLV0(M_SDIO));
582 writel(0x77999999, CREG_AXI_M_SLV1(M_SDIO));
583 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_SDIO));
584 writel(0x76DCBA98, CREG_AXI_M_OFT1(M_SDIO));
585 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_SDIO));
587 writel(0x77777777, CREG_AXI_M_SLV0(M_GPU));
588 writel(0x77777777, CREG_AXI_M_SLV1(M_GPU));
589 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_GPU));
590 writel(0x76543210, CREG_AXI_M_OFT1(M_GPU));
591 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_GPU));
593 writel(0x77777777, CREG_AXI_M_SLV0(M_DMAC_0));
594 writel(0x77777777, CREG_AXI_M_SLV1(M_DMAC_0));
595 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_DMAC_0));
596 writel(0x76543210, CREG_AXI_M_OFT1(M_DMAC_0));
597 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DMAC_0));
599 writel(0x77777777, CREG_AXI_M_SLV0(M_DMAC_1));
600 writel(0x77777777, CREG_AXI_M_SLV1(M_DMAC_1));
601 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_DMAC_1));
602 writel(0x76543210, CREG_AXI_M_OFT1(M_DMAC_1));
603 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DMAC_1));
605 writel(0x00000000, CREG_AXI_M_SLV0(M_DVFS));
606 writel(0x60000000, CREG_AXI_M_SLV1(M_DVFS));
607 writel(0x00000000, CREG_AXI_M_OFT0(M_DVFS));
608 writel(0x00000000, CREG_AXI_M_OFT1(M_DVFS));
609 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DVFS));
611 writel(0x00000000, CREG_PAE);
612 writel(UPDATE_VAL, CREG_PAE_UPDT);
615 static void setup_clocks(void)
619 /* Setup CPU clock */
620 if (env_common.cpu_freq.set) {
621 rate = env_common.cpu_freq.val;
622 soc_clk_ctl("cpu-clk", &rate, CLK_ON | CLK_SET | CLK_MHZ);
625 /* Setup TUN clock */
626 if (env_common.tun_freq.set) {
627 rate = env_common.tun_freq.val;
629 soc_clk_ctl("tun-clk", &rate, CLK_ON | CLK_SET | CLK_MHZ);
631 soc_clk_ctl("tun-clk", NULL, CLK_OFF);
634 if (env_common.axi_freq.set) {
635 rate = env_common.axi_freq.val;
636 soc_clk_ctl("axi-clk", &rate, CLK_SET | CLK_ON | CLK_MHZ);
640 static void do_init_cluster(void)
643 * A multi-core ARC HS configuration always includes only one
644 * ARC_AUX_NON_VOLATILE_LIMIT register, which is shared by all the
647 init_cluster_nvlim();
650 static int check_master_cpu_id(void)
652 if (CPU_ID_GET() == MASTER_CPU_ID)
655 pr_err("u-boot runs on non-master cpu with id: %lu\n", CPU_ID_GET());
660 static noinline int prepare_cpus(void)
664 ret = check_master_cpu_id();
668 ret = envs_process_and_validate(env_map_common, env_map_core, is_cpu_used);
672 printf("CPU start mask is %#x\n", env_common.core_mask.val);
674 do_init_slave_cpus();
675 do_init_master_cpu();
681 static int hsdk_go_run(u32 cpu_start_reg)
683 /* Cleanup caches, disable interrupts */
686 if (env_common.halt_on_boot)
690 * 3 NOPs after FLAG 1 instruction are no longer required for ARCv2
691 * cores but we leave them for gebug purposes.
697 /* Kick chosen slave CPUs */
698 writel(cpu_start_reg, (void __iomem *)CREG_CPU_START);
700 if (is_cpu_used(MASTER_CPU_ID))
701 ((void (*)(void))(env_core.entry[MASTER_CPU_ID].val))();
705 pr_err("u-boot still runs on cpu [%ld]\n", CPU_ID_GET());
708 * We will never return after executing our program if master cpu used
709 * otherwise halt master cpu manually.
717 int board_prep_linux(bootm_headers_t *images)
722 ret = envs_read_validate_common(env_map_mask);
726 /* Rollback to default values */
727 if (!env_common.core_mask.set) {
728 env_common.core_mask.val = ALL_CPU_MASK;
729 env_common.core_mask.set = true;
732 printf("CPU start mask is %#x\n", env_common.core_mask.val);
734 if (!is_cpu_used(MASTER_CPU_ID))
735 pr_err("ERR: try to launch linux with CPU[0] disabled! It doesn't work for ARC.\n");
738 * If we want to launch linux on all CPUs we don't need to patch
739 * linux DTB as it is default configuration
741 if (env_common.core_mask.val == ALL_CPU_MASK)
744 if (!IMAGE_ENABLE_OF_LIBFDT || !images->ft_len) {
745 pr_err("WARN: core_mask setup will work properly only with external DTB!\n");
749 /* patch '/possible-cpus' property according to cpu mask */
750 ofst = fdt_path_offset(images->ft_addr, "/");
751 sprintf(mask, "%s%s%s%s",
752 is_cpu_used(0) ? "0," : "",
753 is_cpu_used(1) ? "1," : "",
754 is_cpu_used(2) ? "2," : "",
755 is_cpu_used(3) ? "3," : "");
756 ret = fdt_setprop_string(images->ft_addr, ofst, "possible-cpus", mask);
758 * If we failed to patch '/possible-cpus' property we don't need break
759 * linux loading process: kernel will handle it but linux will print
760 * warning like "Timeout: CPU1 FAILED to comeup !!!".
761 * So warn here about error, but return 0 like no error had occurred.
764 pr_err("WARN: failed to patch '/possible-cpus' property, ret=%d\n",
770 void board_jump_and_run(ulong entry, int zero, int arch, uint params)
772 void (*kernel_entry)(int zero, int arch, uint params);
775 kernel_entry = (void (*)(int, int, uint))entry;
777 /* Prepare CREG_CPU_START for kicking chosen CPUs */
778 cpu_start_reg = prepare_cpu_ctart_reg();
780 /* In case of run without hsdk_init */
781 slave_cpu_set_boot_addr(entry);
783 /* In case of run with hsdk_init */
784 for (u32 i = 0; i < NR_CPUS; i++) {
785 env_core.entry[i].val = entry;
786 env_core.entry[i].set = true;
788 /* sync cross_cpu struct as we updated core-entry variables */
789 sync_cross_cpu_data();
791 /* Kick chosen slave CPUs */
792 writel(cpu_start_reg, (void __iomem *)CREG_CPU_START);
795 kernel_entry(zero, arch, params);
798 static int hsdk_go_prepare_and_run(void)
800 /* Prepare CREG_CPU_START for kicking chosen CPUs */
801 u32 reg = prepare_cpu_ctart_reg();
803 if (env_common.halt_on_boot)
804 printf("CPU will halt before application start, start application with debugger.\n");
806 return hsdk_go_run(reg);
809 static int do_hsdk_go(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
813 if (board_mismatch()) {
814 printf("ERR: U-boot is not configured for this board!\n");
815 return CMD_RET_FAILURE;
819 * Check for 'halt' parameter. 'halt' = enter halt-mode just before
820 * starting the application; can be used for debug.
823 env_common.halt_on_boot = !strcmp(argv[1], "halt");
824 if (!env_common.halt_on_boot) {
825 pr_err("Unrecognised parameter: \'%s\'\n", argv[1]);
826 return CMD_RET_FAILURE;
830 ret = check_master_cpu_id();
834 ret = envs_process_and_validate(env_map_mask, env_map_go, is_cpu_used);
838 /* sync cross_cpu struct as we updated core-entry variables */
839 sync_cross_cpu_data();
841 ret = hsdk_go_prepare_and_run();
843 return ret ? CMD_RET_FAILURE : CMD_RET_SUCCESS;
847 hsdk_go, 3, 0, do_hsdk_go,
848 "Synopsys HSDK specific command",
849 " - Boot stand-alone application on HSDK\n"
850 "hsdk_go halt - Boot stand-alone application on HSDK, halt CPU just before application run\n"
853 static int do_hsdk_init(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
855 static bool done = false;
858 if (board_mismatch()) {
859 printf("ERR: U-boot is not configured for this board!\n");
860 return CMD_RET_FAILURE;
863 /* hsdk_init can be run only once */
865 printf("HSDK HW is already initialized! Please reset the board if you want to change the configuration.\n");
866 return CMD_RET_FAILURE;
869 ret = prepare_cpus();
873 return ret ? CMD_RET_FAILURE : CMD_RET_SUCCESS;
877 hsdk_init, 1, 0, do_hsdk_init,
878 "Synopsys HSDK specific command",
882 static int do_hsdk_clock_set(cmd_tbl_t *cmdtp, int flag, int argc,
887 /* Strip off leading subcommand argument */
891 envs_cleanup_common(env_map_clock);
894 printf("Set clocks to values specified in environment\n");
895 ret = envs_read_common(env_map_clock);
897 printf("Set clocks to values specified in args\n");
898 ret = args_envs_enumerate(env_map_clock, 2, argc, argv);
902 return CMD_RET_FAILURE;
904 ret = envs_validate_common(env_map_clock);
906 return CMD_RET_FAILURE;
908 /* Setup clock tree HW */
911 return CMD_RET_SUCCESS;
914 static int do_hsdk_clock_get(cmd_tbl_t *cmdtp, int flag, int argc,
919 if (soc_clk_ctl("cpu-clk", &rate, CLK_GET | CLK_MHZ))
920 return CMD_RET_FAILURE;
922 if (env_set_ulong("cpu_freq", rate))
923 return CMD_RET_FAILURE;
925 if (soc_clk_ctl("tun-clk", &rate, CLK_GET | CLK_MHZ))
926 return CMD_RET_FAILURE;
928 if (env_set_ulong("tun_freq", rate))
929 return CMD_RET_FAILURE;
931 if (soc_clk_ctl("axi-clk", &rate, CLK_GET | CLK_MHZ))
932 return CMD_RET_FAILURE;
934 if (env_set_ulong("axi_freq", rate))
935 return CMD_RET_FAILURE;
937 printf("Clock values are saved to environment\n");
939 return CMD_RET_SUCCESS;
942 static int do_hsdk_clock_print(cmd_tbl_t *cmdtp, int flag, int argc,
946 soc_clk_ctl("cpu-clk", NULL, CLK_PRINT | CLK_MHZ);
947 soc_clk_ctl("tun-clk", NULL, CLK_PRINT | CLK_MHZ);
948 soc_clk_ctl("axi-clk", NULL, CLK_PRINT | CLK_MHZ);
949 soc_clk_ctl("ddr-clk", NULL, CLK_PRINT | CLK_MHZ);
951 return CMD_RET_SUCCESS;
954 static int do_hsdk_clock_print_all(cmd_tbl_t *cmdtp, int flag, int argc,
958 * NOTE: as of today we don't use some peripherals like HDMI / EBI
959 * so we don't want to print their clocks ("hdmi-sys-clk", "hdmi-pll",
960 * "hdmi-clk", "ebi-clk"). Nevertheless their clock subsystems is fully
961 * functional and we can print their clocks if it is required
964 /* CPU clock domain */
965 soc_clk_ctl("cpu-pll", NULL, CLK_PRINT | CLK_MHZ);
966 soc_clk_ctl("cpu-clk", NULL, CLK_PRINT | CLK_MHZ);
969 /* SYS clock domain */
970 soc_clk_ctl("sys-pll", NULL, CLK_PRINT | CLK_MHZ);
971 soc_clk_ctl("apb-clk", NULL, CLK_PRINT | CLK_MHZ);
972 soc_clk_ctl("axi-clk", NULL, CLK_PRINT | CLK_MHZ);
973 soc_clk_ctl("eth-clk", NULL, CLK_PRINT | CLK_MHZ);
974 soc_clk_ctl("usb-clk", NULL, CLK_PRINT | CLK_MHZ);
975 soc_clk_ctl("sdio-clk", NULL, CLK_PRINT | CLK_MHZ);
976 /* soc_clk_ctl("hdmi-sys-clk", NULL, CLK_PRINT | CLK_MHZ); */
977 soc_clk_ctl("gfx-core-clk", NULL, CLK_PRINT | CLK_MHZ);
978 soc_clk_ctl("gfx-dma-clk", NULL, CLK_PRINT | CLK_MHZ);
979 soc_clk_ctl("gfx-cfg-clk", NULL, CLK_PRINT | CLK_MHZ);
980 soc_clk_ctl("dmac-core-clk", NULL, CLK_PRINT | CLK_MHZ);
981 soc_clk_ctl("dmac-cfg-clk", NULL, CLK_PRINT | CLK_MHZ);
982 soc_clk_ctl("sdio-ref-clk", NULL, CLK_PRINT | CLK_MHZ);
983 soc_clk_ctl("spi-clk", NULL, CLK_PRINT | CLK_MHZ);
984 soc_clk_ctl("i2c-clk", NULL, CLK_PRINT | CLK_MHZ);
985 /* soc_clk_ctl("ebi-clk", NULL, CLK_PRINT | CLK_MHZ); */
986 soc_clk_ctl("uart-clk", NULL, CLK_PRINT | CLK_MHZ);
989 /* DDR clock domain */
990 soc_clk_ctl("ddr-clk", NULL, CLK_PRINT | CLK_MHZ);
993 /* HDMI clock domain */
994 /* soc_clk_ctl("hdmi-pll", NULL, CLK_PRINT | CLK_MHZ); */
995 /* soc_clk_ctl("hdmi-clk", NULL, CLK_PRINT | CLK_MHZ); */
998 /* TUN clock domain */
999 soc_clk_ctl("tun-pll", NULL, CLK_PRINT | CLK_MHZ);
1000 soc_clk_ctl("tun-clk", NULL, CLK_PRINT | CLK_MHZ);
1001 soc_clk_ctl("rom-clk", NULL, CLK_PRINT | CLK_MHZ);
1002 soc_clk_ctl("pwm-clk", NULL, CLK_PRINT | CLK_MHZ);
1005 return CMD_RET_SUCCESS;
1008 cmd_tbl_t cmd_hsdk_clock[] = {
1009 U_BOOT_CMD_MKENT(set, 3, 0, do_hsdk_clock_set, "", ""),
1010 U_BOOT_CMD_MKENT(get, 3, 0, do_hsdk_clock_get, "", ""),
1011 U_BOOT_CMD_MKENT(print, 4, 0, do_hsdk_clock_print, "", ""),
1012 U_BOOT_CMD_MKENT(print_all, 4, 0, do_hsdk_clock_print_all, "", ""),
1015 static int do_hsdk_clock(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1020 return CMD_RET_USAGE;
1022 /* Strip off leading 'hsdk_clock' command argument */
1026 c = find_cmd_tbl(argv[0], cmd_hsdk_clock, ARRAY_SIZE(cmd_hsdk_clock));
1028 return CMD_RET_USAGE;
1030 return c->cmd(cmdtp, flag, argc, argv);
1034 hsdk_clock, CONFIG_SYS_MAXARGS, 0, do_hsdk_clock,
1035 "Synopsys HSDK specific clock command",
1036 "set - Set clock to values specified in environment / command line arguments\n"
1037 "hsdk_clock get - Save clock values to environment\n"
1038 "hsdk_clock print - Print main clock values to console\n"
1039 "hsdk_clock print_all - Print all clock values to console\n"
1043 int board_early_init_f(void)
1046 * Setup AXI apertures unconditionally as we want to have DDR
1047 * in 0x00000000 region when we are kicking slave cpus.
1049 init_memory_bridge();
1052 * Switch SDIO external ciu clock divider from default div-by-8 to
1053 * minimum possible div-by-2.
1055 writel(SDIO_UHS_REG_EXT_DIV_2, (void __iomem *)SDIO_UHS_REG_EXT);
1060 int board_early_init_r(void)
1063 * TODO: Init USB here to be able read environment from USB MSD.
1064 * It can be done with usb_init() call. We can't do it right now
1065 * due to brocken USB IP SW reset and lack of USB IP HW reset in
1066 * linux kernel (if we init USB here we will break USB in linux)
1070 * Flush all d$ as we want to use uncached area with st.di / ld.di
1071 * instructions and we don't want to have any dirty line in L1d$ or SL$
1072 * in this area. It is enough to flush all d$ once here as we access to
1073 * uncached area with regular st (non .di) instruction only when we copy
1074 * data during u-boot relocation.
1078 printf("Relocation Offset is: %08lx\n", gd->reloc_off);
1083 int board_late_init(void)
1086 * Populate environment with clock frequency values -
1087 * run hsdk_clock get callback without uboot command run.
1089 do_hsdk_clock_get(NULL, 0, 0, NULL);
1094 int checkboard(void)
1096 printf("Board: Synopsys %s\n", board_name(get_board_type_runtime()));
1098 if (board_mismatch())
1099 printf("WARN: U-boot is configured NOT for this board but for %s!\n",
1100 board_name(get_board_type_config()));