2 * Copyright (C) 2017 Synopsys, Inc. All rights reserved.
4 * SPDX-License-Identifier: GPL-2.0+
11 DECLARE_GLOBAL_DATA_PTR;
13 #define CREG_BASE (ARC_PERIPHERAL_BASE + 0x1000)
14 #define CREG_PAE (CREG_BASE + 0x180)
15 #define CREG_PAE_UPDATE (CREG_BASE + 0x194)
16 #define CREG_CPU_START (CREG_BASE + 0x400)
18 int board_early_init_f(void)
20 /* In current chip PAE support for DMA is broken, disabling it. */
21 writel(0, (void __iomem *) CREG_PAE);
23 /* Really apply settings made above */
24 writel(1, (void __iomem *) CREG_PAE_UPDATE);
29 #define SDIO_BASE (ARC_PERIPHERAL_BASE + 0xA000)
30 #define SDIO_UHS_REG_EXT (SDIO_BASE + 0x108)
31 #define SDIO_UHS_REG_EXT_DIV_2 (2 << 30)
33 int board_mmc_init(bd_t *bis)
35 struct dwmci_host *host = NULL;
37 host = malloc(sizeof(struct dwmci_host));
39 printf("dwmci_host malloc fail!\n");
44 * Switch SDIO external ciu clock divider from default div-by-8 to
45 * minimum possible div-by-2.
47 writel(SDIO_UHS_REG_EXT_DIV_2, (void __iomem *) SDIO_UHS_REG_EXT);
49 memset(host, 0, sizeof(struct dwmci_host));
50 host->name = "Synopsys Mobile storage";
51 host->ioaddr = (void *)ARC_DWMMC_BASE;
54 host->bus_hz = 50000000;
56 add_dwmci(host, host->bus_hz / 2, 400000);
61 #define RESET_VECTOR_ADDR 0x0
63 void smp_set_core_boot_addr(unsigned long addr, int corenr)
65 /* All cores have reset vector pointing to 0 */
66 writel(addr, (void __iomem *)RESET_VECTOR_ADDR);
68 /* Make sure other cores see written value in memory */
72 void smp_kick_all_cpus(void)
74 #define BITS_START_CORE1 1
75 #define BITS_START_CORE2 2
76 #define BITS_START_CORE3 3
78 int cmd = readl((void __iomem *)CREG_CPU_START);
80 cmd |= (1 << BITS_START_CORE1) |
81 (1 << BITS_START_CORE2) |
82 (1 << BITS_START_CORE3);
83 writel(cmd, (void __iomem *)CREG_CPU_START);