1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2018 Synopsys, Inc. All rights reserved.
4 * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
12 #define HZ_IN_MHZ 1000000
13 #define ceil(x, y) ({ ulong __x = (x), __y = (y); (__x + __y - 1) / __y; })
15 int soc_clk_ctl(const char *name, ulong *rate, enum clk_ctl_ops ctl)
18 ulong mhz_rate, priv_rate;
21 /* Dummy fmeas device, just to be able to use standard clk_* api */
22 struct udevice fmeas = {
24 .node = ofnode_path("/clk-fmeas"),
27 ret = clk_get_by_name(&fmeas, name, &clk);
29 pr_err("clock '%s' not found, err=%d\n", name, ret);
34 ret = clk_enable(&clk);
35 if (ret && ret != -ENOSYS && ret != -ENOTSUPP)
39 if ((ctl & CLK_SET) && rate) {
40 priv_rate = ctl & CLK_MHZ ? (*rate) * HZ_IN_MHZ : *rate;
41 ret = clk_set_rate(&clk, priv_rate);
47 ret = clk_disable(&clk);
49 pr_err("clock '%s' can't be disabled, err=%d\n", name, ret);
54 priv_rate = clk_get_rate(&clk);
58 mhz_rate = ceil(priv_rate, HZ_IN_MHZ);
63 if ((ctl & CLK_GET) && rate)
66 if ((ctl & CLK_PRINT) && (ctl & CLK_MHZ))
67 printf("HSDK: clock '%s' rate %lu MHz\n", name, priv_rate);
68 else if (ctl & CLK_PRINT)
69 printf("HSDK: clock '%s' rate %lu Hz\n", name, priv_rate);
71 debug("HSDK: clock '%s' rate %lu MHz\n", name, mhz_rate);