1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2018 Synopsys, Inc. All rights reserved.
4 * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
13 #define HZ_IN_MHZ 1000000
14 #define ceil(x, y) ({ ulong __x = (x), __y = (y); (__x + __y - 1) / __y; })
16 int soc_clk_ctl(const char *name, ulong *rate, enum clk_ctl_ops ctl)
19 ulong mhz_rate, priv_rate;
22 /* Dummy fmeas device, just to be able to use standard clk_* api */
23 struct udevice fmeas = {
25 .node = ofnode_path("/clk-fmeas"),
28 ret = clk_get_by_name(&fmeas, name, &clk);
30 pr_err("clock '%s' not found, err=%d\n", name, ret);
35 ret = clk_enable(&clk);
36 if (ret && ret != -ENOSYS && ret != -ENOTSUPP)
40 if ((ctl & CLK_SET) && rate) {
41 priv_rate = ctl & CLK_MHZ ? (*rate) * HZ_IN_MHZ : *rate;
42 ret = clk_set_rate(&clk, priv_rate);
48 ret = clk_disable(&clk);
50 pr_err("clock '%s' can't be disabled, err=%d\n", name, ret);
55 priv_rate = clk_get_rate(&clk);
59 mhz_rate = ceil(priv_rate, HZ_IN_MHZ);
64 if ((ctl & CLK_GET) && rate)
67 if ((ctl & CLK_PRINT) && (ctl & CLK_MHZ))
68 printf("HSDK: clock '%s' rate %lu MHz\n", name, priv_rate);
69 else if (ctl & CLK_PRINT)
70 printf("HSDK: clock '%s' rate %lu Hz\n", name, priv_rate);
72 debug("HSDK: clock '%s' rate %lu MHz\n", name, mhz_rate);