1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
10 #include <asm/arcregs.h>
13 DECLARE_GLOBAL_DATA_PTR;
15 #define AXS_MB_CREG 0xE0011000
17 int board_early_init_f(void)
19 if (readl((void __iomem *)AXS_MB_CREG + 0x234) & (1 << 28))
20 gd->board_type = AXS_MB_V3;
22 gd->board_type = AXS_MB_V2;
27 #ifdef CONFIG_ISA_ARCV2
29 void board_jump_and_run(ulong entry, int zero, int arch, uint params)
31 void (*kernel_entry)(int zero, int arch, uint params);
33 kernel_entry = (void (*)(int, int, uint))entry;
35 smp_set_core_boot_addr(entry, -1);
37 kernel_entry(zero, arch, params);
40 #define RESET_VECTOR_ADDR 0x0
42 void smp_set_core_boot_addr(unsigned long addr, int corenr)
44 /* All cores have reset vector pointing to 0 */
45 writel(addr, (void __iomem *)RESET_VECTOR_ADDR);
47 /* Make sure other cores see written value in memory */
51 void smp_kick_all_cpus(void)
54 #define AXC003_CREG_CPU_START 0xF0001400
55 /* Bits positions in CPU start CREG */
57 #define BITS_START_MODE 4
58 #define BITS_CORE_SEL 9
61 * In axs103 v1.1 START bits semantics has changed quite a bit.
62 * We used to have a generic START bit for all cores selected by CORE_SEL mask.
63 * But now we don't touch CORE_SEL at all because we have a dedicated START bit
65 * bit 0: Core 0 (master)
66 * bit 1: Core 1 (slave)
68 #define BITS_START_CORE1 1
70 #define ARCVER_HS38_3_0 0x53
72 int core_family = read_aux_reg(ARC_AUX_IDENTITY) & 0xff;
73 int cmd = readl((void __iomem *)AXC003_CREG_CPU_START);
75 if (core_family < ARCVER_HS38_3_0) {
76 cmd |= (1 << BITS_CORE_SEL) | (1 << BITS_START);
77 cmd &= ~(1 << BITS_START_MODE);
79 cmd |= (1 << BITS_START_CORE1);
81 writel(cmd, (void __iomem *)AXC003_CREG_CPU_START);
87 printf("Board: ARC Software Development Platform AXS%s\n",
88 is_isa_arcv2() ? "103" : "101");