1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
9 #include <asm/arcregs.h>
12 DECLARE_GLOBAL_DATA_PTR;
14 int board_mmc_init(bd_t *bis)
16 struct dwmci_host *host = NULL;
18 host = malloc(sizeof(struct dwmci_host));
20 printf("dwmci_host malloc fail!\n");
24 memset(host, 0, sizeof(struct dwmci_host));
25 host->name = "Synopsys Mobile storage";
26 host->ioaddr = (void *)ARC_DWMMC_BASE;
29 host->bus_hz = 50000000;
31 add_dwmci(host, host->bus_hz / 2, 400000);
36 int board_mmc_getcd(struct mmc *mmc)
38 struct dwmci_host *host = mmc->priv;
40 return !(dwmci_readl(host, DWMCI_CDETECT) & 1);
43 #define AXS_MB_CREG 0xE0011000
45 int board_early_init_f(void)
47 if (readl((void __iomem *)AXS_MB_CREG + 0x234) & (1 << 28))
48 gd->board_type = AXS_MB_V3;
50 gd->board_type = AXS_MB_V2;
55 #ifdef CONFIG_ISA_ARCV2
57 void board_jump_and_run(ulong entry, int zero, int arch, uint params)
59 void (*kernel_entry)(int zero, int arch, uint params);
61 kernel_entry = (void (*)(int, int, uint))entry;
63 smp_set_core_boot_addr(entry, -1);
65 kernel_entry(zero, arch, params);
68 #define RESET_VECTOR_ADDR 0x0
70 void smp_set_core_boot_addr(unsigned long addr, int corenr)
72 /* All cores have reset vector pointing to 0 */
73 writel(addr, (void __iomem *)RESET_VECTOR_ADDR);
75 /* Make sure other cores see written value in memory */
79 void smp_kick_all_cpus(void)
82 #define AXC003_CREG_CPU_START 0xF0001400
83 /* Bits positions in CPU start CREG */
85 #define BITS_START_MODE 4
86 #define BITS_CORE_SEL 9
89 * In axs103 v1.1 START bits semantics has changed quite a bit.
90 * We used to have a generic START bit for all cores selected by CORE_SEL mask.
91 * But now we don't touch CORE_SEL at all because we have a dedicated START bit
93 * bit 0: Core 0 (master)
94 * bit 1: Core 1 (slave)
96 #define BITS_START_CORE1 1
98 #define ARCVER_HS38_3_0 0x53
100 int core_family = read_aux_reg(ARC_AUX_IDENTITY) & 0xff;
101 int cmd = readl((void __iomem *)AXC003_CREG_CPU_START);
103 if (core_family < ARCVER_HS38_3_0) {
104 cmd |= (1 << BITS_CORE_SEL) | (1 << BITS_START);
105 cmd &= ~(1 << BITS_START_MODE);
107 cmd |= (1 << BITS_START_CORE1);
109 writel(cmd, (void __iomem *)AXC003_CREG_CPU_START);