1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
10 #include <asm/arcregs.h>
12 #include <asm/cache.h>
14 DECLARE_GLOBAL_DATA_PTR;
16 #define AXS_MB_CREG 0xE0011000
18 int board_early_init_f(void)
20 if (readl((void __iomem *)AXS_MB_CREG + 0x234) & (1 << 28))
21 gd->board_type = AXS_MB_V3;
23 gd->board_type = AXS_MB_V2;
28 #ifdef CONFIG_ISA_ARCV2
30 void board_jump_and_run(ulong entry, int zero, int arch, uint params)
32 void (*kernel_entry)(int zero, int arch, uint params);
34 kernel_entry = (void (*)(int, int, uint))entry;
36 smp_set_core_boot_addr(entry, -1);
38 kernel_entry(zero, arch, params);
41 #define RESET_VECTOR_ADDR 0x0
43 void smp_set_core_boot_addr(unsigned long addr, int corenr)
45 /* All cores have reset vector pointing to 0 */
46 writel(addr, (void __iomem *)RESET_VECTOR_ADDR);
48 /* Make sure other cores see written value in memory */
52 void smp_kick_all_cpus(void)
55 #define AXC003_CREG_CPU_START 0xF0001400
56 /* Bits positions in CPU start CREG */
58 #define BITS_START_MODE 4
59 #define BITS_CORE_SEL 9
62 * In axs103 v1.1 START bits semantics has changed quite a bit.
63 * We used to have a generic START bit for all cores selected by CORE_SEL mask.
64 * But now we don't touch CORE_SEL at all because we have a dedicated START bit
66 * bit 0: Core 0 (master)
67 * bit 1: Core 1 (slave)
69 #define BITS_START_CORE1 1
71 #define ARCVER_HS38_3_0 0x53
73 int core_family = read_aux_reg(ARC_AUX_IDENTITY) & 0xff;
74 int cmd = readl((void __iomem *)AXC003_CREG_CPU_START);
76 if (core_family < ARCVER_HS38_3_0) {
77 cmd |= (1 << BITS_CORE_SEL) | (1 << BITS_START);
78 cmd &= ~(1 << BITS_START_MODE);
80 cmd |= (1 << BITS_START_CORE1);
82 writel(cmd, (void __iomem *)AXC003_CREG_CPU_START);
88 printf("Board: ARC Software Development Platform AXS%s\n",
89 is_isa_arcv2() ? "103" : "101");