1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
4 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
6 * (C) Copyright 2007-2011
7 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
8 * Tom Cubie <tangliang@allwinnertech.com>
10 * Some board init for the Allwinner A10-evb board.
17 #include <generic-phy.h>
18 #include <phy-sun4i-usb.h>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/cpu.h>
21 #include <asm/arch/display.h>
22 #include <asm/arch/dram.h>
23 #include <asm/arch/gpio.h>
24 #include <asm/arch/mmc.h>
25 #include <asm/arch/spl.h>
27 #include <asm/armv7.h>
31 #include <u-boot/crc.h>
32 #include <environment.h>
33 #include <linux/libfdt.h>
38 #include <asm/setup.h>
40 #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
41 /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */
42 int soft_i2c_gpio_sda;
43 int soft_i2c_gpio_scl;
45 static int soft_i2c_board_init(void)
49 soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA);
50 if (soft_i2c_gpio_sda < 0) {
51 printf("Error invalid soft i2c sda pin: '%s', err %d\n",
52 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda);
53 return soft_i2c_gpio_sda;
55 ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda");
57 printf("Error requesting soft i2c sda pin: '%s', err %d\n",
58 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret);
62 soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL);
63 if (soft_i2c_gpio_scl < 0) {
64 printf("Error invalid soft i2c scl pin: '%s', err %d\n",
65 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl);
66 return soft_i2c_gpio_scl;
68 ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl");
70 printf("Error requesting soft i2c scl pin: '%s', err %d\n",
71 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret);
78 static int soft_i2c_board_init(void) { return 0; }
81 DECLARE_GLOBAL_DATA_PTR;
83 void i2c_init_board(void)
85 #ifdef CONFIG_I2C0_ENABLE
86 #if defined(CONFIG_MACH_SUN4I) || \
87 defined(CONFIG_MACH_SUN5I) || \
88 defined(CONFIG_MACH_SUN7I) || \
89 defined(CONFIG_MACH_SUN8I_R40)
90 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0);
91 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0);
92 clock_twi_onoff(0, 1);
93 #elif defined(CONFIG_MACH_SUN6I)
94 sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
95 sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
96 clock_twi_onoff(0, 1);
97 #elif defined(CONFIG_MACH_SUN8I)
98 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0);
99 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0);
100 clock_twi_onoff(0, 1);
104 #ifdef CONFIG_I2C1_ENABLE
105 #if defined(CONFIG_MACH_SUN4I) || \
106 defined(CONFIG_MACH_SUN7I) || \
107 defined(CONFIG_MACH_SUN8I_R40)
108 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1);
109 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1);
110 clock_twi_onoff(1, 1);
111 #elif defined(CONFIG_MACH_SUN5I)
112 sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1);
113 sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1);
114 clock_twi_onoff(1, 1);
115 #elif defined(CONFIG_MACH_SUN6I)
116 sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1);
117 sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1);
118 clock_twi_onoff(1, 1);
119 #elif defined(CONFIG_MACH_SUN8I)
120 sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1);
121 sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1);
122 clock_twi_onoff(1, 1);
126 #ifdef CONFIG_I2C2_ENABLE
127 #if defined(CONFIG_MACH_SUN4I) || \
128 defined(CONFIG_MACH_SUN7I) || \
129 defined(CONFIG_MACH_SUN8I_R40)
130 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2);
131 sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2);
132 clock_twi_onoff(2, 1);
133 #elif defined(CONFIG_MACH_SUN5I)
134 sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2);
135 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2);
136 clock_twi_onoff(2, 1);
137 #elif defined(CONFIG_MACH_SUN6I)
138 sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2);
139 sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2);
140 clock_twi_onoff(2, 1);
141 #elif defined(CONFIG_MACH_SUN8I)
142 sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2);
143 sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2);
144 clock_twi_onoff(2, 1);
148 #ifdef CONFIG_I2C3_ENABLE
149 #if defined(CONFIG_MACH_SUN6I)
150 sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3);
151 sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3);
152 clock_twi_onoff(3, 1);
153 #elif defined(CONFIG_MACH_SUN7I) || \
154 defined(CONFIG_MACH_SUN8I_R40)
155 sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3);
156 sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3);
157 clock_twi_onoff(3, 1);
161 #ifdef CONFIG_I2C4_ENABLE
162 #if defined(CONFIG_MACH_SUN7I) || \
163 defined(CONFIG_MACH_SUN8I_R40)
164 sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4);
165 sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4);
166 clock_twi_onoff(4, 1);
170 #ifdef CONFIG_R_I2C_ENABLE
171 #ifdef CONFIG_MACH_SUN50I
172 clock_twi_onoff(5, 1);
173 sunxi_gpio_set_cfgpin(SUNXI_GPL(8), SUN50I_GPL_R_TWI);
174 sunxi_gpio_set_cfgpin(SUNXI_GPL(9), SUN50I_GPL_R_TWI);
176 clock_twi_onoff(5, 1);
177 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI);
178 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI);
183 #if defined(CONFIG_ENV_IS_IN_MMC) && defined(CONFIG_ENV_IS_IN_FAT)
184 enum env_location env_get_location(enum env_operation op, int prio)
199 /* add board specific code here */
202 __maybe_unused int id_pfr1, ret, satapwr_pin, macpwr_pin;
204 gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
207 asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
208 debug("id_pfr1: 0x%08x\n", id_pfr1);
209 /* Generic Timer Extension available? */
210 if ((id_pfr1 >> CPUID_ARM_GENTIMER_SHIFT) & 0xf) {
213 debug("Setting CNTFRQ\n");
216 * CNTFRQ is a secure register, so we will crash if we try to
217 * write this from the non-secure world (read is OK, though).
218 * In case some bootcode has already set the correct value,
219 * we avoid the risk of writing to it.
221 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq));
222 if (freq != COUNTER_FREQUENCY) {
223 debug("arch timer frequency is %d Hz, should be %d, fixing ...\n",
224 freq, COUNTER_FREQUENCY);
225 #ifdef CONFIG_NON_SECURE
226 printf("arch timer frequency is wrong, but cannot adjust it\n");
228 asm volatile("mcr p15, 0, %0, c14, c0, 0"
229 : : "r"(COUNTER_FREQUENCY));
233 #endif /* !CONFIG_ARM64 */
235 ret = axp_gpio_init();
239 #ifdef CONFIG_SATAPWR
240 satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR);
241 gpio_request(satapwr_pin, "satapwr");
242 gpio_direction_output(satapwr_pin, 1);
243 /* Give attached sata device time to power-up to avoid link timeouts */
247 macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR);
248 gpio_request(macpwr_pin, "macpwr");
249 gpio_direction_output(macpwr_pin, 1);
254 * Temporary workaround for enabling I2C clocks until proper sunxi DM
255 * clk, reset and pinctrl drivers land.
260 /* Uses dm gpio code so do this here and not in i2c_init_board() */
261 return soft_i2c_board_init();
265 * On older SoCs the SPL is actually at address zero, so using NULL as
266 * an error value does not work.
268 #define INVALID_SPL_HEADER ((void *)~0UL)
270 static struct boot_file_head * get_spl_header(uint8_t req_version)
272 struct boot_file_head *spl = (void *)(ulong)SPL_ADDR;
273 uint8_t spl_header_version = spl->spl_signature[3];
275 /* Is there really the SPL header (still) there? */
276 if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) != 0)
277 return INVALID_SPL_HEADER;
279 if (spl_header_version < req_version) {
280 printf("sunxi SPL version mismatch: expected %u, got %u\n",
281 req_version, spl_header_version);
282 return INVALID_SPL_HEADER;
290 struct boot_file_head *spl = get_spl_header(SPL_DRAM_HEADER_VERSION);
292 if (spl == INVALID_SPL_HEADER)
293 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0,
296 gd->ram_size = (phys_addr_t)spl->dram_size << 20;
298 if (gd->ram_size > CONFIG_SUNXI_DRAM_MAX_SIZE)
299 gd->ram_size = CONFIG_SUNXI_DRAM_MAX_SIZE;
304 #if defined(CONFIG_NAND_SUNXI)
305 static void nand_pinmux_setup(void)
309 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++)
310 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
312 #if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I
313 for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++)
314 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
316 /* sun4i / sun7i do have a PC23, but it is not used for nand,
317 * only sun7i has a PC24 */
318 #ifdef CONFIG_MACH_SUN7I
319 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND);
323 static void nand_clock_setup(void)
325 struct sunxi_ccm_reg *const ccm =
326 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
328 setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0));
329 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I || \
330 defined CONFIG_MACH_SUN9I || defined CONFIG_MACH_SUN50I
331 setbits_le32(&ccm->ahb_reset0_cfg, (1 << AHB_GATE_OFFSET_NAND0));
333 setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1);
336 void board_nand_init(void)
340 #ifndef CONFIG_SPL_BUILD
347 static void mmc_pinmux_setup(int sdc)
350 __maybe_unused int pins;
355 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
356 sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0);
357 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
358 sunxi_gpio_set_drv(pin, 2);
363 pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS);
365 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
366 defined(CONFIG_MACH_SUN8I_R40)
367 if (pins == SUNXI_GPIO_H) {
368 /* SDC1: PH22-PH-27 */
369 for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
370 sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1);
371 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
372 sunxi_gpio_set_drv(pin, 2);
376 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
377 sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1);
378 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
379 sunxi_gpio_set_drv(pin, 2);
382 #elif defined(CONFIG_MACH_SUN5I)
384 for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) {
385 sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1);
386 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
387 sunxi_gpio_set_drv(pin, 2);
389 #elif defined(CONFIG_MACH_SUN6I)
391 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
392 sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1);
393 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
394 sunxi_gpio_set_drv(pin, 2);
396 #elif defined(CONFIG_MACH_SUN8I)
397 if (pins == SUNXI_GPIO_D) {
399 for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) {
400 sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1);
401 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
402 sunxi_gpio_set_drv(pin, 2);
406 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
407 sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1);
408 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
409 sunxi_gpio_set_drv(pin, 2);
416 pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS);
418 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
420 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
421 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
422 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
423 sunxi_gpio_set_drv(pin, 2);
425 #elif defined(CONFIG_MACH_SUN5I)
426 if (pins == SUNXI_GPIO_E) {
428 for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) {
429 sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2);
430 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
431 sunxi_gpio_set_drv(pin, 2);
435 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
436 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
437 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
438 sunxi_gpio_set_drv(pin, 2);
441 #elif defined(CONFIG_MACH_SUN6I)
442 if (pins == SUNXI_GPIO_A) {
444 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
445 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2);
446 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
447 sunxi_gpio_set_drv(pin, 2);
450 /* SDC2: PC6-PC15, PC24 */
451 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
452 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
453 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
454 sunxi_gpio_set_drv(pin, 2);
457 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
458 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
459 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
461 #elif defined(CONFIG_MACH_SUN8I_R40)
462 /* SDC2: PC6-PC15, PC24 */
463 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
464 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
465 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
466 sunxi_gpio_set_drv(pin, 2);
469 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
470 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
471 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
472 #elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I)
473 /* SDC2: PC5-PC6, PC8-PC16 */
474 for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) {
475 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
476 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
477 sunxi_gpio_set_drv(pin, 2);
480 for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) {
481 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
482 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
483 sunxi_gpio_set_drv(pin, 2);
485 #elif defined(CONFIG_MACH_SUN50I_H6)
487 for (pin = SUNXI_GPC(4); pin <= SUNXI_GPC(14); pin++) {
488 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
489 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
490 sunxi_gpio_set_drv(pin, 2);
492 #elif defined(CONFIG_MACH_SUN9I)
494 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(16); pin++) {
495 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
496 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
497 sunxi_gpio_set_drv(pin, 2);
503 pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS);
505 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
506 defined(CONFIG_MACH_SUN8I_R40)
508 for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
509 sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3);
510 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
511 sunxi_gpio_set_drv(pin, 2);
513 #elif defined(CONFIG_MACH_SUN6I)
514 if (pins == SUNXI_GPIO_A) {
516 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
517 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3);
518 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
519 sunxi_gpio_set_drv(pin, 2);
522 /* SDC3: PC6-PC15, PC24 */
523 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
524 sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3);
525 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
526 sunxi_gpio_set_drv(pin, 2);
529 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3);
530 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
531 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
537 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc);
542 int board_mmc_init(bd_t *bis)
544 __maybe_unused struct mmc *mmc0, *mmc1;
546 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
547 mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
551 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
552 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
553 mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
562 #ifdef CONFIG_SPL_BUILD
564 static void sunxi_spl_store_dram_size(phys_addr_t dram_size)
566 struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
568 if (spl == INVALID_SPL_HEADER)
571 /* Promote the header version for U-Boot proper, if needed. */
572 if (spl->spl_signature[3] < SPL_DRAM_HEADER_VERSION)
573 spl->spl_signature[3] = SPL_DRAM_HEADER_VERSION;
575 spl->dram_size = dram_size >> 20;
578 void sunxi_board_init(void)
580 int power_failed = 0;
582 #ifdef CONFIG_SY8106A_POWER
583 power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT);
586 #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
587 defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
588 defined CONFIG_AXP818_POWER
589 power_failed = axp_init();
591 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
592 defined CONFIG_AXP818_POWER
593 power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT);
595 power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT);
596 power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT);
597 #if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER)
598 power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT);
600 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
601 defined CONFIG_AXP818_POWER
602 power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT);
605 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
606 defined CONFIG_AXP818_POWER
607 power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT);
609 power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT);
610 #if !defined(CONFIG_AXP152_POWER)
611 power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT);
613 #ifdef CONFIG_AXP209_POWER
614 power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT);
617 #if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \
618 defined(CONFIG_AXP818_POWER)
619 power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT);
620 power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT);
621 #if !defined CONFIG_AXP809_POWER
622 power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT);
623 power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT);
625 power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT);
626 power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT);
627 power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT);
630 #ifdef CONFIG_AXP818_POWER
631 power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT);
632 power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT);
633 power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT);
636 #if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
637 power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON));
642 * Only clock up the CPU to full speed if we are reasonably
643 * assured it's being powered with suitable core voltage
646 clock_set_pll1(CONFIG_SYS_CLK_FREQ);
648 printf("Error setting up the power controller.\n"
649 "CPU frequency not set.\n");
652 gd->ram_size = sunxi_dram_init();
653 printf(" %d MiB\n", (int)(gd->ram_size >> 20));
657 sunxi_spl_store_dram_size(gd->ram_size);
661 #ifdef CONFIG_USB_GADGET
662 int g_dnl_board_usb_cable_connected(void)
668 ret = uclass_get_device(UCLASS_USB_GADGET_GENERIC, 0, &dev);
670 pr_err("%s: Cannot find USB device\n", __func__);
674 ret = generic_phy_get_by_name(dev, "usb", &phy);
676 pr_err("failed to get %s USB PHY\n", dev->name);
680 ret = generic_phy_init(&phy);
682 pr_err("failed to init %s USB PHY\n", dev->name);
686 ret = sun4i_usb_phy_vbus_detect(&phy);
688 pr_err("A charger is plugged into the OTG\n");
696 #ifdef CONFIG_SERIAL_TAG
697 void get_board_serial(struct tag_serialnr *serialnr)
700 unsigned long long serial;
702 serial_string = env_get("serial#");
705 serial = simple_strtoull(serial_string, NULL, 16);
707 serialnr->high = (unsigned int) (serial >> 32);
708 serialnr->low = (unsigned int) (serial & 0xffffffff);
717 * Check the SPL header for the "sunxi" variant. If found: parse values
718 * that might have been passed by the loader ("fel" utility), and update
719 * the environment accordingly.
721 static void parse_spl_header(const uint32_t spl_addr)
723 struct boot_file_head *spl = get_spl_header(SPL_ENV_HEADER_VERSION);
725 if (spl == INVALID_SPL_HEADER)
728 if (!spl->fel_script_address)
731 if (spl->fel_uEnv_length != 0) {
733 * data is expected in uEnv.txt compatible format, so "env
734 * import -t" the string(s) at fel_script_address right away.
736 himport_r(&env_htab, (char *)(uintptr_t)spl->fel_script_address,
737 spl->fel_uEnv_length, '\n', H_NOCLEAR, 0, 0, NULL);
740 /* otherwise assume .scr format (mkimage-type script) */
741 env_set_hex("fel_scriptaddr", spl->fel_script_address);
745 * Note this function gets called multiple times.
746 * It must not make any changes to env variables which already exist.
748 static void setup_environment(const void *fdt)
750 char serial_string[17] = { 0 };
756 ret = sunxi_get_sid(sid);
757 if (ret == 0 && sid[0] != 0) {
759 * The single words 1 - 3 of the SID have quite a few bits
760 * which are the same on many models, so we take a crc32
761 * of all 3 words, to get a more unique value.
763 * Note we only do this on newer SoCs as we cannot change
764 * the algorithm on older SoCs since those have been using
765 * fixed mac-addresses based on only using word 3 for a
766 * long time and changing a fixed mac-address with an
767 * u-boot update is not good.
769 #if !defined(CONFIG_MACH_SUN4I) && !defined(CONFIG_MACH_SUN5I) && \
770 !defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_MACH_SUN7I) && \
771 !defined(CONFIG_MACH_SUN8I_A23) && !defined(CONFIG_MACH_SUN8I_A33)
772 sid[3] = crc32(0, (unsigned char *)&sid[1], 12);
775 /* Ensure the NIC specific bytes of the mac are not all 0 */
776 if ((sid[3] & 0xffffff) == 0)
779 for (i = 0; i < 4; i++) {
780 sprintf(ethaddr, "ethernet%d", i);
781 if (!fdt_get_alias(fdt, ethaddr))
785 strcpy(ethaddr, "ethaddr");
787 sprintf(ethaddr, "eth%daddr", i);
789 if (env_get(ethaddr))
792 /* Non OUI / registered MAC address */
793 mac_addr[0] = (i << 4) | 0x02;
794 mac_addr[1] = (sid[0] >> 0) & 0xff;
795 mac_addr[2] = (sid[3] >> 24) & 0xff;
796 mac_addr[3] = (sid[3] >> 16) & 0xff;
797 mac_addr[4] = (sid[3] >> 8) & 0xff;
798 mac_addr[5] = (sid[3] >> 0) & 0xff;
800 eth_env_set_enetaddr(ethaddr, mac_addr);
803 if (!env_get("serial#")) {
804 snprintf(serial_string, sizeof(serial_string),
805 "%08x%08x", sid[0], sid[3]);
807 env_set("serial#", serial_string);
812 int misc_init_r(void)
816 env_set("fel_booted", NULL);
817 env_set("fel_scriptaddr", NULL);
818 env_set("mmc_bootdev", NULL);
820 boot = sunxi_get_boot_device();
821 /* determine if we are running in FEL mode */
822 if (boot == BOOT_DEVICE_BOARD) {
823 env_set("fel_booted", "1");
824 parse_spl_header(SPL_ADDR);
825 /* or if we booted from MMC, and which one */
826 } else if (boot == BOOT_DEVICE_MMC1) {
827 env_set("mmc_bootdev", "0");
828 } else if (boot == BOOT_DEVICE_MMC2) {
829 env_set("mmc_bootdev", "1");
832 setup_environment(gd->fdt_blob);
834 #ifdef CONFIG_USB_ETHER
841 int ft_board_setup(void *blob, bd_t *bd)
843 int __maybe_unused r;
846 * Call setup_environment again in case the boot fdt has
847 * ethernet aliases the u-boot copy does not have.
849 setup_environment(blob);
851 #ifdef CONFIG_VIDEO_DT_SIMPLEFB
852 r = sunxi_simplefb_setup(blob);
859 #ifdef CONFIG_SPL_LOAD_FIT
860 int board_fit_config_name_match(const char *name)
862 struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
863 const char *cmp_str = (const char *)spl;
865 /* Check if there is a DT name stored in the SPL header and use that. */
866 if (spl != INVALID_SPL_HEADER && spl->dt_name_offset) {
867 cmp_str += spl->dt_name_offset;
869 #ifdef CONFIG_DEFAULT_DEVICE_TREE
870 cmp_str = CONFIG_DEFAULT_DEVICE_TREE;
876 #ifdef CONFIG_PINE64_DT_SELECTION
877 /* Differentiate the two Pine64 board DTs by their DRAM size. */
878 if (strstr(name, "-pine64") && strstr(cmp_str, "-pine64")) {
879 if ((gd->ram_size > 512 * 1024 * 1024))
880 return !strstr(name, "plus");
882 return !!strstr(name, "plus");
884 return strcmp(name, cmp_str);
887 return strcmp(name, cmp_str);