2 * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
3 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
5 * (C) Copyright 2007-2011
6 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
7 * Tom Cubie <tangliang@allwinnertech.com>
9 * Some board init for the Allwinner A10-evb board.
11 * SPDX-License-Identifier: GPL-2.0+
17 #include <asm/arch/clock.h>
18 #include <asm/arch/cpu.h>
19 #include <asm/arch/display.h>
20 #include <asm/arch/dram.h>
21 #include <asm/arch/gpio.h>
22 #include <asm/arch/mmc.h>
23 #include <asm/arch/usb_phy.h>
30 #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
31 /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */
32 int soft_i2c_gpio_sda;
33 int soft_i2c_gpio_scl;
35 static int soft_i2c_board_init(void)
39 soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA);
40 if (soft_i2c_gpio_sda < 0) {
41 printf("Error invalid soft i2c sda pin: '%s', err %d\n",
42 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda);
43 return soft_i2c_gpio_sda;
45 ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda");
47 printf("Error requesting soft i2c sda pin: '%s', err %d\n",
48 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret);
52 soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL);
53 if (soft_i2c_gpio_scl < 0) {
54 printf("Error invalid soft i2c scl pin: '%s', err %d\n",
55 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl);
56 return soft_i2c_gpio_scl;
58 ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl");
60 printf("Error requesting soft i2c scl pin: '%s', err %d\n",
61 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret);
68 static int soft_i2c_board_init(void) { return 0; }
71 DECLARE_GLOBAL_DATA_PTR;
73 /* add board specific code here */
78 gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
80 asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
81 debug("id_pfr1: 0x%08x\n", id_pfr1);
82 /* Generic Timer Extension available? */
83 if ((id_pfr1 >> 16) & 0xf) {
84 debug("Setting CNTFRQ\n");
85 /* CNTFRQ == 24 MHz */
86 asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r"(24000000));
89 ret = axp_gpio_init();
93 /* Uses dm gpio code so do this here and not in i2c_init_board() */
94 return soft_i2c_board_init();
99 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE);
104 #if defined(CONFIG_NAND_SUNXI) && defined(CONFIG_SPL_BUILD)
105 static void nand_pinmux_setup(void)
109 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++)
110 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
112 #if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I
113 for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++)
114 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
116 /* sun4i / sun7i do have a PC23, but it is not used for nand,
117 * only sun7i has a PC24 */
118 #ifdef CONFIG_MACH_SUN7I
119 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND);
123 static void nand_clock_setup(void)
125 struct sunxi_ccm_reg *const ccm =
126 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
128 setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0));
129 #ifdef CONFIG_MACH_SUN9I
130 setbits_le32(&ccm->ahb_gate1, (1 << AHB_GATE_OFFSET_DMA));
132 setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_DMA));
134 setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1);
137 void board_nand_init(void)
144 #ifdef CONFIG_GENERIC_MMC
145 static void mmc_pinmux_setup(int sdc)
148 __maybe_unused int pins;
153 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
154 sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0);
155 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
156 sunxi_gpio_set_drv(pin, 2);
161 pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS);
163 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
164 if (pins == SUNXI_GPIO_H) {
165 /* SDC1: PH22-PH-27 */
166 for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
167 sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1);
168 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
169 sunxi_gpio_set_drv(pin, 2);
173 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
174 sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1);
175 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
176 sunxi_gpio_set_drv(pin, 2);
179 #elif defined(CONFIG_MACH_SUN5I)
181 for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) {
182 sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1);
183 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
184 sunxi_gpio_set_drv(pin, 2);
186 #elif defined(CONFIG_MACH_SUN6I)
188 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
189 sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1);
190 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
191 sunxi_gpio_set_drv(pin, 2);
193 #elif defined(CONFIG_MACH_SUN8I)
194 if (pins == SUNXI_GPIO_D) {
196 for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) {
197 sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1);
198 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
199 sunxi_gpio_set_drv(pin, 2);
203 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
204 sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1);
205 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
206 sunxi_gpio_set_drv(pin, 2);
213 pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS);
215 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
217 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
218 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
219 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
220 sunxi_gpio_set_drv(pin, 2);
222 #elif defined(CONFIG_MACH_SUN5I)
223 if (pins == SUNXI_GPIO_E) {
225 for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) {
226 sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2);
227 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
228 sunxi_gpio_set_drv(pin, 2);
232 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
233 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
234 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
235 sunxi_gpio_set_drv(pin, 2);
238 #elif defined(CONFIG_MACH_SUN6I)
239 if (pins == SUNXI_GPIO_A) {
241 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
242 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2);
243 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
244 sunxi_gpio_set_drv(pin, 2);
247 /* SDC2: PC6-PC15, PC24 */
248 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
249 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
250 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
251 sunxi_gpio_set_drv(pin, 2);
254 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
255 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
256 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
258 #elif defined(CONFIG_MACH_SUN8I)
259 /* SDC2: PC5-PC6, PC8-PC16 */
260 for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) {
261 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
262 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
263 sunxi_gpio_set_drv(pin, 2);
266 for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) {
267 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
268 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
269 sunxi_gpio_set_drv(pin, 2);
275 pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS);
277 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
279 for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
280 sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3);
281 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
282 sunxi_gpio_set_drv(pin, 2);
284 #elif defined(CONFIG_MACH_SUN6I)
285 if (pins == SUNXI_GPIO_A) {
287 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
288 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3);
289 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
290 sunxi_gpio_set_drv(pin, 2);
293 /* SDC3: PC6-PC15, PC24 */
294 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
295 sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3);
296 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
297 sunxi_gpio_set_drv(pin, 2);
300 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3);
301 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
302 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
308 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc);
313 int board_mmc_init(bd_t *bis)
315 __maybe_unused struct mmc *mmc0, *mmc1;
316 __maybe_unused char buf[512];
318 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
319 mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
323 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
324 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
325 mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
330 #if !defined(CONFIG_SPL_BUILD) && CONFIG_MMC_SUNXI_SLOT_EXTRA == 2
332 * On systems with an emmc (mmc2), figure out if we are booting from
333 * the emmc and if we are make it "mmc dev 0" so that boot.scr, etc.
334 * are searched there first. Note we only do this for u-boot proper,
335 * not for the SPL, see spl_boot_device().
337 if (!sunxi_mmc_has_egon_boot_signature(mmc0) &&
338 sunxi_mmc_has_egon_boot_signature(mmc1)) {
339 /* Booting from emmc / mmc2, swap */
340 mmc0->block_dev.dev = 1;
341 mmc1->block_dev.dev = 0;
349 void i2c_init_board(void)
351 #ifdef CONFIG_I2C0_ENABLE
352 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
353 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0);
354 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0);
355 clock_twi_onoff(0, 1);
356 #elif defined(CONFIG_MACH_SUN6I)
357 sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
358 sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
359 clock_twi_onoff(0, 1);
360 #elif defined(CONFIG_MACH_SUN8I)
361 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0);
362 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0);
363 clock_twi_onoff(0, 1);
367 #ifdef CONFIG_I2C1_ENABLE
368 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
369 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1);
370 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1);
371 clock_twi_onoff(1, 1);
372 #elif defined(CONFIG_MACH_SUN5I)
373 sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1);
374 sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1);
375 clock_twi_onoff(1, 1);
376 #elif defined(CONFIG_MACH_SUN6I)
377 sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1);
378 sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1);
379 clock_twi_onoff(1, 1);
380 #elif defined(CONFIG_MACH_SUN8I)
381 sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1);
382 sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1);
383 clock_twi_onoff(1, 1);
387 #ifdef CONFIG_I2C2_ENABLE
388 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
389 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2);
390 sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2);
391 clock_twi_onoff(2, 1);
392 #elif defined(CONFIG_MACH_SUN5I)
393 sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2);
394 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2);
395 clock_twi_onoff(2, 1);
396 #elif defined(CONFIG_MACH_SUN6I)
397 sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2);
398 sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2);
399 clock_twi_onoff(2, 1);
400 #elif defined(CONFIG_MACH_SUN8I)
401 sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2);
402 sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2);
403 clock_twi_onoff(2, 1);
407 #ifdef CONFIG_I2C3_ENABLE
408 #if defined(CONFIG_MACH_SUN6I)
409 sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3);
410 sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3);
411 clock_twi_onoff(3, 1);
412 #elif defined(CONFIG_MACH_SUN7I)
413 sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3);
414 sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3);
415 clock_twi_onoff(3, 1);
419 #ifdef CONFIG_I2C4_ENABLE
420 #if defined(CONFIG_MACH_SUN7I)
421 sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4);
422 sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4);
423 clock_twi_onoff(4, 1);
427 #ifdef CONFIG_R_I2C_ENABLE
428 clock_twi_onoff(5, 1);
429 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI);
430 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI);
434 #ifdef CONFIG_SPL_BUILD
435 void sunxi_board_init(void)
437 int power_failed = 0;
438 unsigned long ramsize;
440 #ifdef CONFIG_SY8106A_POWER
441 power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT);
444 #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
445 defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER
446 power_failed = axp_init();
448 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER
449 power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT);
451 power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT);
452 power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT);
453 #if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER)
454 power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT);
456 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER
457 power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT);
460 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER
461 power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT);
463 power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT);
464 #if !defined(CONFIG_AXP152_POWER)
465 power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT);
467 #ifdef CONFIG_AXP209_POWER
468 power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT);
471 #if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP818_POWER)
472 power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT);
473 power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT);
474 power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT);
475 power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT);
476 power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT);
477 power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT);
478 power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT);
482 ramsize = sunxi_dram_init();
483 printf(" %lu MiB\n", ramsize >> 20);
488 * Only clock up the CPU to full speed if we are reasonably
489 * assured it's being powered with suitable core voltage
492 clock_set_pll1(CONFIG_SYS_CLK_FREQ);
494 printf("Failed to set core voltage! Can't set CPU frequency\n");
498 #ifdef CONFIG_USB_GADGET
499 int g_dnl_board_usb_cable_connected(void)
501 return sunxi_usb_phy_vbus_detect(0);
505 #ifdef CONFIG_SERIAL_TAG
506 void get_board_serial(struct tag_serialnr *serialnr)
509 unsigned long long serial;
511 serial_string = getenv("serial#");
514 serial = simple_strtoull(serial_string, NULL, 16);
516 serialnr->high = (unsigned int) (serial >> 32);
517 serialnr->low = (unsigned int) (serial & 0xffffffff);
525 #if !defined(CONFIG_SPL_BUILD)
526 #include <asm/arch/spl.h>
529 * Check the SPL header for the "sunxi" variant. If found: parse values
530 * that might have been passed by the loader ("fel" utility), and update
531 * the environment accordingly.
533 static void parse_spl_header(const uint32_t spl_addr)
535 struct boot_file_head *spl = (void *)spl_addr;
536 if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) == 0) {
537 uint8_t spl_header_version = spl->spl_signature[3];
538 if (spl_header_version == SPL_HEADER_VERSION) {
539 if (spl->fel_script_address)
540 setenv_hex("fel_scriptaddr",
541 spl->fel_script_address);
544 printf("sunxi SPL version mismatch: expected %u, got %u\n",
545 SPL_HEADER_VERSION, spl_header_version);
550 #ifdef CONFIG_MISC_INIT_R
551 int misc_init_r(void)
553 char serial_string[17] = { 0 };
558 #if !defined(CONFIG_SPL_BUILD)
559 setenv("fel_booted", NULL);
560 setenv("fel_scriptaddr", NULL);
561 /* determine if we are running in FEL mode */
562 if (!is_boot0_magic(SPL_ADDR + 4)) { /* eGON.BT0 */
563 setenv("fel_booted", "1");
564 parse_spl_header(SPL_ADDR);
568 ret = sunxi_get_sid(sid);
569 if (ret == 0 && sid[0] != 0 && sid[3] != 0) {
570 if (!getenv("ethaddr")) {
571 /* Non OUI / registered MAC address */
573 mac_addr[1] = (sid[0] >> 0) & 0xff;
574 mac_addr[2] = (sid[3] >> 24) & 0xff;
575 mac_addr[3] = (sid[3] >> 16) & 0xff;
576 mac_addr[4] = (sid[3] >> 8) & 0xff;
577 mac_addr[5] = (sid[3] >> 0) & 0xff;
579 eth_setenv_enetaddr("ethaddr", mac_addr);
582 if (!getenv("serial#")) {
583 snprintf(serial_string, sizeof(serial_string),
584 "%08x%08x", sid[0], sid[3]);
586 setenv("serial#", serial_string);
590 #ifndef CONFIG_MACH_SUN9I
591 ret = sunxi_usb_phy_probe();
595 sunxi_musb_board_init();
601 #ifdef CONFIG_OF_BOARD_SETUP
602 int ft_board_setup(void *blob, bd_t *bd)
604 #ifdef CONFIG_VIDEO_DT_SIMPLEFB
605 return sunxi_simplefb_setup(blob);
608 #endif /* CONFIG_OF_BOARD_SETUP */