2 * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
3 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
5 * (C) Copyright 2007-2011
6 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
7 * Tom Cubie <tangliang@allwinnertech.com>
9 * Some board init for the Allwinner A10-evb board.
11 * SPDX-License-Identifier: GPL-2.0+
17 #include <asm/arch/clock.h>
18 #include <asm/arch/cpu.h>
19 #include <asm/arch/display.h>
20 #include <asm/arch/dram.h>
21 #include <asm/arch/gpio.h>
22 #include <asm/arch/mmc.h>
23 #include <asm/arch/usb_phy.h>
30 #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
31 /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */
32 int soft_i2c_gpio_sda;
33 int soft_i2c_gpio_scl;
35 static int soft_i2c_board_init(void)
39 soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA);
40 if (soft_i2c_gpio_sda < 0) {
41 printf("Error invalid soft i2c sda pin: '%s', err %d\n",
42 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda);
43 return soft_i2c_gpio_sda;
45 ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda");
47 printf("Error requesting soft i2c sda pin: '%s', err %d\n",
48 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret);
52 soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL);
53 if (soft_i2c_gpio_scl < 0) {
54 printf("Error invalid soft i2c scl pin: '%s', err %d\n",
55 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl);
56 return soft_i2c_gpio_scl;
58 ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl");
60 printf("Error requesting soft i2c scl pin: '%s', err %d\n",
61 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret);
68 static int soft_i2c_board_init(void) { return 0; }
71 DECLARE_GLOBAL_DATA_PTR;
73 /* add board specific code here */
78 gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
80 asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
81 debug("id_pfr1: 0x%08x\n", id_pfr1);
82 /* Generic Timer Extension available? */
83 if ((id_pfr1 >> 16) & 0xf) {
84 debug("Setting CNTFRQ\n");
85 /* CNTFRQ == 24 MHz */
86 asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r"(24000000));
89 ret = axp_gpio_init();
94 gpio_request(CONFIG_SATAPWR, "satapwr");
95 gpio_direction_output(CONFIG_SATAPWR, 1);
98 gpio_request(CONFIG_MACPWR, "macpwr");
99 gpio_direction_output(CONFIG_MACPWR, 1);
102 /* Uses dm gpio code so do this here and not in i2c_init_board() */
103 return soft_i2c_board_init();
108 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE);
113 #if defined(CONFIG_NAND_SUNXI) && defined(CONFIG_SPL_BUILD)
114 static void nand_pinmux_setup(void)
118 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++)
119 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
121 #if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I
122 for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++)
123 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
125 /* sun4i / sun7i do have a PC23, but it is not used for nand,
126 * only sun7i has a PC24 */
127 #ifdef CONFIG_MACH_SUN7I
128 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND);
132 static void nand_clock_setup(void)
134 struct sunxi_ccm_reg *const ccm =
135 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
137 setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0));
138 #ifdef CONFIG_MACH_SUN9I
139 setbits_le32(&ccm->ahb_gate1, (1 << AHB_GATE_OFFSET_DMA));
141 setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_DMA));
143 setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1);
146 void board_nand_init(void)
153 #ifdef CONFIG_GENERIC_MMC
154 static void mmc_pinmux_setup(int sdc)
157 __maybe_unused int pins;
162 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
163 sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0);
164 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
165 sunxi_gpio_set_drv(pin, 2);
170 pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS);
172 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
173 if (pins == SUNXI_GPIO_H) {
174 /* SDC1: PH22-PH-27 */
175 for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
176 sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1);
177 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
178 sunxi_gpio_set_drv(pin, 2);
182 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
183 sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1);
184 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
185 sunxi_gpio_set_drv(pin, 2);
188 #elif defined(CONFIG_MACH_SUN5I)
190 for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) {
191 sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1);
192 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
193 sunxi_gpio_set_drv(pin, 2);
195 #elif defined(CONFIG_MACH_SUN6I)
197 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
198 sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1);
199 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
200 sunxi_gpio_set_drv(pin, 2);
202 #elif defined(CONFIG_MACH_SUN8I)
203 if (pins == SUNXI_GPIO_D) {
205 for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) {
206 sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1);
207 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
208 sunxi_gpio_set_drv(pin, 2);
212 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
213 sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1);
214 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
215 sunxi_gpio_set_drv(pin, 2);
222 pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS);
224 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
226 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
227 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
228 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
229 sunxi_gpio_set_drv(pin, 2);
231 #elif defined(CONFIG_MACH_SUN5I)
232 if (pins == SUNXI_GPIO_E) {
234 for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) {
235 sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2);
236 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
237 sunxi_gpio_set_drv(pin, 2);
241 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
242 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
243 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
244 sunxi_gpio_set_drv(pin, 2);
247 #elif defined(CONFIG_MACH_SUN6I)
248 if (pins == SUNXI_GPIO_A) {
250 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
251 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2);
252 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
253 sunxi_gpio_set_drv(pin, 2);
256 /* SDC2: PC6-PC15, PC24 */
257 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
258 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
259 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
260 sunxi_gpio_set_drv(pin, 2);
263 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
264 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
265 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
267 #elif defined(CONFIG_MACH_SUN8I)
268 /* SDC2: PC5-PC6, PC8-PC16 */
269 for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) {
270 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
271 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
272 sunxi_gpio_set_drv(pin, 2);
275 for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) {
276 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
277 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
278 sunxi_gpio_set_drv(pin, 2);
284 pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS);
286 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
288 for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
289 sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3);
290 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
291 sunxi_gpio_set_drv(pin, 2);
293 #elif defined(CONFIG_MACH_SUN6I)
294 if (pins == SUNXI_GPIO_A) {
296 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
297 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3);
298 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
299 sunxi_gpio_set_drv(pin, 2);
302 /* SDC3: PC6-PC15, PC24 */
303 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
304 sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3);
305 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
306 sunxi_gpio_set_drv(pin, 2);
309 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3);
310 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
311 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
317 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc);
322 int board_mmc_init(bd_t *bis)
324 __maybe_unused struct mmc *mmc0, *mmc1;
325 __maybe_unused char buf[512];
327 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
328 mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
332 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
333 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
334 mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
339 #if !defined(CONFIG_SPL_BUILD) && CONFIG_MMC_SUNXI_SLOT_EXTRA == 2
341 * On systems with an emmc (mmc2), figure out if we are booting from
342 * the emmc and if we are make it "mmc dev 0" so that boot.scr, etc.
343 * are searched there first. Note we only do this for u-boot proper,
344 * not for the SPL, see spl_boot_device().
346 if (!sunxi_mmc_has_egon_boot_signature(mmc0) &&
347 sunxi_mmc_has_egon_boot_signature(mmc1)) {
348 /* Booting from emmc / mmc2, swap */
349 mmc0->block_dev.devnum = 1;
350 mmc1->block_dev.devnum = 0;
358 void i2c_init_board(void)
360 #ifdef CONFIG_I2C0_ENABLE
361 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
362 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0);
363 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0);
364 clock_twi_onoff(0, 1);
365 #elif defined(CONFIG_MACH_SUN6I)
366 sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
367 sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
368 clock_twi_onoff(0, 1);
369 #elif defined(CONFIG_MACH_SUN8I)
370 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0);
371 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0);
372 clock_twi_onoff(0, 1);
376 #ifdef CONFIG_I2C1_ENABLE
377 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
378 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1);
379 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1);
380 clock_twi_onoff(1, 1);
381 #elif defined(CONFIG_MACH_SUN5I)
382 sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1);
383 sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1);
384 clock_twi_onoff(1, 1);
385 #elif defined(CONFIG_MACH_SUN6I)
386 sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1);
387 sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1);
388 clock_twi_onoff(1, 1);
389 #elif defined(CONFIG_MACH_SUN8I)
390 sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1);
391 sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1);
392 clock_twi_onoff(1, 1);
396 #ifdef CONFIG_I2C2_ENABLE
397 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
398 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2);
399 sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2);
400 clock_twi_onoff(2, 1);
401 #elif defined(CONFIG_MACH_SUN5I)
402 sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2);
403 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2);
404 clock_twi_onoff(2, 1);
405 #elif defined(CONFIG_MACH_SUN6I)
406 sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2);
407 sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2);
408 clock_twi_onoff(2, 1);
409 #elif defined(CONFIG_MACH_SUN8I)
410 sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2);
411 sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2);
412 clock_twi_onoff(2, 1);
416 #ifdef CONFIG_I2C3_ENABLE
417 #if defined(CONFIG_MACH_SUN6I)
418 sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3);
419 sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3);
420 clock_twi_onoff(3, 1);
421 #elif defined(CONFIG_MACH_SUN7I)
422 sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3);
423 sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3);
424 clock_twi_onoff(3, 1);
428 #ifdef CONFIG_I2C4_ENABLE
429 #if defined(CONFIG_MACH_SUN7I)
430 sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4);
431 sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4);
432 clock_twi_onoff(4, 1);
436 #ifdef CONFIG_R_I2C_ENABLE
437 clock_twi_onoff(5, 1);
438 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI);
439 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI);
443 #ifdef CONFIG_SPL_BUILD
444 void sunxi_board_init(void)
446 int power_failed = 0;
447 unsigned long ramsize;
449 #ifdef CONFIG_SY8106A_POWER
450 power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT);
453 #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
454 defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER
455 power_failed = axp_init();
457 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER
458 power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT);
460 power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT);
461 power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT);
462 #if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER)
463 power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT);
465 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER
466 power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT);
469 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER
470 power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT);
472 power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT);
473 #if !defined(CONFIG_AXP152_POWER)
474 power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT);
476 #ifdef CONFIG_AXP209_POWER
477 power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT);
480 #if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP818_POWER)
481 power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT);
482 power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT);
483 power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT);
484 power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT);
485 power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT);
486 power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT);
487 power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT);
491 ramsize = sunxi_dram_init();
492 printf(" %lu MiB\n", ramsize >> 20);
497 * Only clock up the CPU to full speed if we are reasonably
498 * assured it's being powered with suitable core voltage
501 clock_set_pll1(CONFIG_SYS_CLK_FREQ);
503 printf("Failed to set core voltage! Can't set CPU frequency\n");
507 #ifdef CONFIG_USB_GADGET
508 int g_dnl_board_usb_cable_connected(void)
510 return sunxi_usb_phy_vbus_detect(0);
514 #ifdef CONFIG_SERIAL_TAG
515 void get_board_serial(struct tag_serialnr *serialnr)
518 unsigned long long serial;
520 serial_string = getenv("serial#");
523 serial = simple_strtoull(serial_string, NULL, 16);
525 serialnr->high = (unsigned int) (serial >> 32);
526 serialnr->low = (unsigned int) (serial & 0xffffffff);
534 #if !defined(CONFIG_SPL_BUILD)
535 #include <asm/arch/spl.h>
538 * Check the SPL header for the "sunxi" variant. If found: parse values
539 * that might have been passed by the loader ("fel" utility), and update
540 * the environment accordingly.
542 static void parse_spl_header(const uint32_t spl_addr)
544 struct boot_file_head *spl = (void *)spl_addr;
545 if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) == 0) {
546 uint8_t spl_header_version = spl->spl_signature[3];
547 if (spl_header_version == SPL_HEADER_VERSION) {
548 if (spl->fel_script_address)
549 setenv_hex("fel_scriptaddr",
550 spl->fel_script_address);
553 printf("sunxi SPL version mismatch: expected %u, got %u\n",
554 SPL_HEADER_VERSION, spl_header_version);
559 #ifdef CONFIG_MISC_INIT_R
560 int misc_init_r(void)
562 char serial_string[17] = { 0 };
567 #if !defined(CONFIG_SPL_BUILD)
568 setenv("fel_booted", NULL);
569 setenv("fel_scriptaddr", NULL);
570 /* determine if we are running in FEL mode */
571 if (!is_boot0_magic(SPL_ADDR + 4)) { /* eGON.BT0 */
572 setenv("fel_booted", "1");
573 parse_spl_header(SPL_ADDR);
577 ret = sunxi_get_sid(sid);
578 if (ret == 0 && sid[0] != 0 && sid[3] != 0) {
579 if (!getenv("ethaddr")) {
580 /* Non OUI / registered MAC address */
582 mac_addr[1] = (sid[0] >> 0) & 0xff;
583 mac_addr[2] = (sid[3] >> 24) & 0xff;
584 mac_addr[3] = (sid[3] >> 16) & 0xff;
585 mac_addr[4] = (sid[3] >> 8) & 0xff;
586 mac_addr[5] = (sid[3] >> 0) & 0xff;
588 eth_setenv_enetaddr("ethaddr", mac_addr);
591 if (!getenv("serial#")) {
592 snprintf(serial_string, sizeof(serial_string),
593 "%08x%08x", sid[0], sid[3]);
595 setenv("serial#", serial_string);
599 #ifndef CONFIG_MACH_SUN9I
600 ret = sunxi_usb_phy_probe();
604 sunxi_musb_board_init();
610 int ft_board_setup(void *blob, bd_t *bd)
612 int __maybe_unused r;
614 #ifdef CONFIG_VIDEO_DT_SIMPLEFB
615 r = sunxi_simplefb_setup(blob);