1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
4 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
6 * (C) Copyright 2007-2011
7 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
8 * Tom Cubie <tangliang@allwinnertech.com>
10 * Some board init for the Allwinner A10-evb board.
22 #include <generic-phy.h>
23 #include <phy-sun4i-usb.h>
24 #include <asm/arch/clock.h>
25 #include <asm/arch/cpu.h>
26 #include <asm/arch/display.h>
27 #include <asm/arch/dram.h>
28 #include <asm/arch/gpio.h>
29 #include <asm/arch/mmc.h>
30 #include <asm/arch/spl.h>
31 #include <linux/delay.h>
32 #include <u-boot/crc.h>
34 #include <asm/armv7.h>
38 #include <u-boot/crc.h>
39 #include <env_internal.h>
40 #include <linux/libfdt.h>
45 #include <asm/setup.h>
47 #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
48 /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */
49 int soft_i2c_gpio_sda;
50 int soft_i2c_gpio_scl;
52 static int soft_i2c_board_init(void)
56 soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA);
57 if (soft_i2c_gpio_sda < 0) {
58 printf("Error invalid soft i2c sda pin: '%s', err %d\n",
59 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda);
60 return soft_i2c_gpio_sda;
62 ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda");
64 printf("Error requesting soft i2c sda pin: '%s', err %d\n",
65 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret);
69 soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL);
70 if (soft_i2c_gpio_scl < 0) {
71 printf("Error invalid soft i2c scl pin: '%s', err %d\n",
72 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl);
73 return soft_i2c_gpio_scl;
75 ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl");
77 printf("Error requesting soft i2c scl pin: '%s', err %d\n",
78 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret);
85 static int soft_i2c_board_init(void) { return 0; }
88 DECLARE_GLOBAL_DATA_PTR;
90 void i2c_init_board(void)
92 #ifdef CONFIG_I2C0_ENABLE
93 #if defined(CONFIG_MACH_SUN4I) || \
94 defined(CONFIG_MACH_SUN5I) || \
95 defined(CONFIG_MACH_SUN7I) || \
96 defined(CONFIG_MACH_SUN8I_R40)
97 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0);
98 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0);
99 clock_twi_onoff(0, 1);
100 #elif defined(CONFIG_MACH_SUN6I)
101 sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
102 sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
103 clock_twi_onoff(0, 1);
104 #elif defined(CONFIG_MACH_SUN8I)
105 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0);
106 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0);
107 clock_twi_onoff(0, 1);
108 #elif defined(CONFIG_MACH_SUN50I)
109 sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_GPH_TWI0);
110 sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_GPH_TWI0);
111 clock_twi_onoff(0, 1);
115 #ifdef CONFIG_I2C1_ENABLE
116 #if defined(CONFIG_MACH_SUN4I) || \
117 defined(CONFIG_MACH_SUN7I) || \
118 defined(CONFIG_MACH_SUN8I_R40)
119 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1);
120 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1);
121 clock_twi_onoff(1, 1);
122 #elif defined(CONFIG_MACH_SUN5I)
123 sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1);
124 sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1);
125 clock_twi_onoff(1, 1);
126 #elif defined(CONFIG_MACH_SUN6I)
127 sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1);
128 sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1);
129 clock_twi_onoff(1, 1);
130 #elif defined(CONFIG_MACH_SUN8I)
131 sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1);
132 sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1);
133 clock_twi_onoff(1, 1);
134 #elif defined(CONFIG_MACH_SUN50I)
135 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN50I_GPH_TWI1);
136 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN50I_GPH_TWI1);
137 clock_twi_onoff(1, 1);
141 #ifdef CONFIG_I2C2_ENABLE
142 #if defined(CONFIG_MACH_SUN4I) || \
143 defined(CONFIG_MACH_SUN7I) || \
144 defined(CONFIG_MACH_SUN8I_R40)
145 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2);
146 sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2);
147 clock_twi_onoff(2, 1);
148 #elif defined(CONFIG_MACH_SUN5I)
149 sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2);
150 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2);
151 clock_twi_onoff(2, 1);
152 #elif defined(CONFIG_MACH_SUN6I)
153 sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2);
154 sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2);
155 clock_twi_onoff(2, 1);
156 #elif defined(CONFIG_MACH_SUN8I)
157 sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2);
158 sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2);
159 clock_twi_onoff(2, 1);
160 #elif defined(CONFIG_MACH_SUN50I)
161 sunxi_gpio_set_cfgpin(SUNXI_GPE(14), SUN50I_GPE_TWI2);
162 sunxi_gpio_set_cfgpin(SUNXI_GPE(15), SUN50I_GPE_TWI2);
163 clock_twi_onoff(2, 1);
167 #ifdef CONFIG_I2C3_ENABLE
168 #if defined(CONFIG_MACH_SUN6I)
169 sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3);
170 sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3);
171 clock_twi_onoff(3, 1);
172 #elif defined(CONFIG_MACH_SUN7I) || \
173 defined(CONFIG_MACH_SUN8I_R40)
174 sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3);
175 sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3);
176 clock_twi_onoff(3, 1);
180 #ifdef CONFIG_I2C4_ENABLE
181 #if defined(CONFIG_MACH_SUN7I) || \
182 defined(CONFIG_MACH_SUN8I_R40)
183 sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4);
184 sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4);
185 clock_twi_onoff(4, 1);
189 #ifdef CONFIG_R_I2C_ENABLE
190 #ifdef CONFIG_MACH_SUN50I
191 clock_twi_onoff(5, 1);
192 sunxi_gpio_set_cfgpin(SUNXI_GPL(8), SUN50I_GPL_R_TWI);
193 sunxi_gpio_set_cfgpin(SUNXI_GPL(9), SUN50I_GPL_R_TWI);
195 clock_twi_onoff(5, 1);
196 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI);
197 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI);
202 #if defined(CONFIG_ENV_IS_IN_MMC) && defined(CONFIG_ENV_IS_IN_FAT)
203 enum env_location env_get_location(enum env_operation op, int prio)
219 static void mmc_pinmux_setup(int sdc);
222 /* add board specific code here */
225 __maybe_unused int id_pfr1, ret, satapwr_pin, macpwr_pin;
227 gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
230 asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
231 debug("id_pfr1: 0x%08x\n", id_pfr1);
232 /* Generic Timer Extension available? */
233 if ((id_pfr1 >> CPUID_ARM_GENTIMER_SHIFT) & 0xf) {
236 debug("Setting CNTFRQ\n");
239 * CNTFRQ is a secure register, so we will crash if we try to
240 * write this from the non-secure world (read is OK, though).
241 * In case some bootcode has already set the correct value,
242 * we avoid the risk of writing to it.
244 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq));
245 if (freq != COUNTER_FREQUENCY) {
246 debug("arch timer frequency is %d Hz, should be %d, fixing ...\n",
247 freq, COUNTER_FREQUENCY);
248 #ifdef CONFIG_NON_SECURE
249 printf("arch timer frequency is wrong, but cannot adjust it\n");
251 asm volatile("mcr p15, 0, %0, c14, c0, 0"
252 : : "r"(COUNTER_FREQUENCY));
256 #endif /* !CONFIG_ARM64 */
258 ret = axp_gpio_init();
262 #ifdef CONFIG_SATAPWR
263 satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR);
264 gpio_request(satapwr_pin, "satapwr");
265 gpio_direction_output(satapwr_pin, 1);
266 /* Give attached sata device time to power-up to avoid link timeouts */
270 macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR);
271 gpio_request(macpwr_pin, "macpwr");
272 gpio_direction_output(macpwr_pin, 1);
277 * Temporary workaround for enabling I2C clocks until proper sunxi DM
278 * clk, reset and pinctrl drivers land.
285 * Temporary workaround for enabling MMC clocks until a sunxi DM
286 * pinctrl driver lands.
288 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
289 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
290 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
292 #endif /* CONFIG_DM_MMC */
294 /* Uses dm gpio code so do this here and not in i2c_init_board() */
295 return soft_i2c_board_init();
299 * On older SoCs the SPL is actually at address zero, so using NULL as
300 * an error value does not work.
302 #define INVALID_SPL_HEADER ((void *)~0UL)
304 static struct boot_file_head * get_spl_header(uint8_t req_version)
306 struct boot_file_head *spl = (void *)(ulong)SPL_ADDR;
307 uint8_t spl_header_version = spl->spl_signature[3];
309 /* Is there really the SPL header (still) there? */
310 if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) != 0)
311 return INVALID_SPL_HEADER;
313 if (spl_header_version < req_version) {
314 printf("sunxi SPL version mismatch: expected %u, got %u\n",
315 req_version, spl_header_version);
316 return INVALID_SPL_HEADER;
324 struct boot_file_head *spl = get_spl_header(SPL_DRAM_HEADER_VERSION);
326 if (spl == INVALID_SPL_HEADER)
327 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0,
330 gd->ram_size = (phys_addr_t)spl->dram_size << 20;
332 if (gd->ram_size > CONFIG_SUNXI_DRAM_MAX_SIZE)
333 gd->ram_size = CONFIG_SUNXI_DRAM_MAX_SIZE;
338 #if defined(CONFIG_NAND_SUNXI)
339 static void nand_pinmux_setup(void)
343 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++)
344 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
346 #if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I
347 for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++)
348 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
350 /* sun4i / sun7i do have a PC23, but it is not used for nand,
351 * only sun7i has a PC24 */
352 #ifdef CONFIG_MACH_SUN7I
353 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND);
357 static void nand_clock_setup(void)
359 struct sunxi_ccm_reg *const ccm =
360 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
362 setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0));
363 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I || \
364 defined CONFIG_MACH_SUN9I || defined CONFIG_MACH_SUN50I
365 setbits_le32(&ccm->ahb_reset0_cfg, (1 << AHB_GATE_OFFSET_NAND0));
367 setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1);
370 void board_nand_init(void)
374 #ifndef CONFIG_SPL_BUILD
381 static void mmc_pinmux_setup(int sdc)
384 __maybe_unused int pins;
389 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
390 sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0);
391 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
392 sunxi_gpio_set_drv(pin, 2);
397 pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS);
399 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
400 defined(CONFIG_MACH_SUN8I_R40)
401 if (pins == SUNXI_GPIO_H) {
402 /* SDC1: PH22-PH-27 */
403 for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
404 sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1);
405 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
406 sunxi_gpio_set_drv(pin, 2);
410 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
411 sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1);
412 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
413 sunxi_gpio_set_drv(pin, 2);
416 #elif defined(CONFIG_MACH_SUN5I)
418 for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) {
419 sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1);
420 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
421 sunxi_gpio_set_drv(pin, 2);
423 #elif defined(CONFIG_MACH_SUN6I)
425 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
426 sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1);
427 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
428 sunxi_gpio_set_drv(pin, 2);
430 #elif defined(CONFIG_MACH_SUN8I)
431 if (pins == SUNXI_GPIO_D) {
433 for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) {
434 sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1);
435 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
436 sunxi_gpio_set_drv(pin, 2);
440 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
441 sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1);
442 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
443 sunxi_gpio_set_drv(pin, 2);
450 pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS);
452 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
454 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
455 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
456 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
457 sunxi_gpio_set_drv(pin, 2);
459 #elif defined(CONFIG_MACH_SUN5I)
460 if (pins == SUNXI_GPIO_E) {
462 for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) {
463 sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2);
464 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
465 sunxi_gpio_set_drv(pin, 2);
469 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
470 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
471 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
472 sunxi_gpio_set_drv(pin, 2);
475 #elif defined(CONFIG_MACH_SUN6I)
476 if (pins == SUNXI_GPIO_A) {
478 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
479 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2);
480 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
481 sunxi_gpio_set_drv(pin, 2);
484 /* SDC2: PC6-PC15, PC24 */
485 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
486 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
487 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
488 sunxi_gpio_set_drv(pin, 2);
491 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
492 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
493 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
495 #elif defined(CONFIG_MACH_SUN8I_R40)
496 /* SDC2: PC6-PC15, PC24 */
497 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
498 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
499 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
500 sunxi_gpio_set_drv(pin, 2);
503 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
504 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
505 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
506 #elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I)
507 /* SDC2: PC5-PC6, PC8-PC16 */
508 for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) {
509 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
510 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
511 sunxi_gpio_set_drv(pin, 2);
514 for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) {
515 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
516 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
517 sunxi_gpio_set_drv(pin, 2);
519 #elif defined(CONFIG_MACH_SUN50I_H6)
521 for (pin = SUNXI_GPC(4); pin <= SUNXI_GPC(14); pin++) {
522 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
523 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
524 sunxi_gpio_set_drv(pin, 2);
526 #elif defined(CONFIG_MACH_SUN9I)
528 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(16); pin++) {
529 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
530 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
531 sunxi_gpio_set_drv(pin, 2);
537 pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS);
539 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
540 defined(CONFIG_MACH_SUN8I_R40)
542 for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
543 sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3);
544 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
545 sunxi_gpio_set_drv(pin, 2);
547 #elif defined(CONFIG_MACH_SUN6I)
548 if (pins == SUNXI_GPIO_A) {
550 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
551 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3);
552 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
553 sunxi_gpio_set_drv(pin, 2);
556 /* SDC3: PC6-PC15, PC24 */
557 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
558 sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3);
559 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
560 sunxi_gpio_set_drv(pin, 2);
563 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3);
564 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
565 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
571 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc);
576 int board_mmc_init(bd_t *bis)
578 __maybe_unused struct mmc *mmc0, *mmc1;
580 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
581 mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
585 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
586 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
587 mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
596 #ifdef CONFIG_SPL_BUILD
598 static void sunxi_spl_store_dram_size(phys_addr_t dram_size)
600 struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
602 if (spl == INVALID_SPL_HEADER)
605 /* Promote the header version for U-Boot proper, if needed. */
606 if (spl->spl_signature[3] < SPL_DRAM_HEADER_VERSION)
607 spl->spl_signature[3] = SPL_DRAM_HEADER_VERSION;
609 spl->dram_size = dram_size >> 20;
612 void sunxi_board_init(void)
614 int power_failed = 0;
616 #ifdef CONFIG_SY8106A_POWER
617 power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT);
620 #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
621 defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
622 defined CONFIG_AXP818_POWER
623 power_failed = axp_init();
625 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
626 defined CONFIG_AXP818_POWER
627 power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT);
629 power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT);
630 power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT);
631 #if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER)
632 power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT);
634 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
635 defined CONFIG_AXP818_POWER
636 power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT);
639 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
640 defined CONFIG_AXP818_POWER
641 power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT);
643 power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT);
644 #if !defined(CONFIG_AXP152_POWER)
645 power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT);
647 #ifdef CONFIG_AXP209_POWER
648 power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT);
651 #if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \
652 defined(CONFIG_AXP818_POWER)
653 power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT);
654 power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT);
655 #if !defined CONFIG_AXP809_POWER
656 power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT);
657 power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT);
659 power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT);
660 power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT);
661 power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT);
664 #ifdef CONFIG_AXP818_POWER
665 power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT);
666 power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT);
667 power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT);
670 #if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
671 power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON));
675 gd->ram_size = sunxi_dram_init();
676 printf(" %d MiB\n", (int)(gd->ram_size >> 20));
680 sunxi_spl_store_dram_size(gd->ram_size);
683 * Only clock up the CPU to full speed if we are reasonably
684 * assured it's being powered with suitable core voltage
687 clock_set_pll1(CONFIG_SYS_CLK_FREQ);
689 printf("Failed to set core voltage! Can't set CPU frequency\n");
693 #ifdef CONFIG_USB_GADGET
694 int g_dnl_board_usb_cable_connected(void)
700 ret = uclass_get_device(UCLASS_USB_GADGET_GENERIC, 0, &dev);
702 pr_err("%s: Cannot find USB device\n", __func__);
706 ret = generic_phy_get_by_name(dev, "usb", &phy);
708 pr_err("failed to get %s USB PHY\n", dev->name);
712 ret = generic_phy_init(&phy);
714 pr_err("failed to init %s USB PHY\n", dev->name);
718 ret = sun4i_usb_phy_vbus_detect(&phy);
720 pr_err("A charger is plugged into the OTG\n");
728 #ifdef CONFIG_SERIAL_TAG
729 void get_board_serial(struct tag_serialnr *serialnr)
732 unsigned long long serial;
734 serial_string = env_get("serial#");
737 serial = simple_strtoull(serial_string, NULL, 16);
739 serialnr->high = (unsigned int) (serial >> 32);
740 serialnr->low = (unsigned int) (serial & 0xffffffff);
749 * Check the SPL header for the "sunxi" variant. If found: parse values
750 * that might have been passed by the loader ("fel" utility), and update
751 * the environment accordingly.
753 static void parse_spl_header(const uint32_t spl_addr)
755 struct boot_file_head *spl = get_spl_header(SPL_ENV_HEADER_VERSION);
757 if (spl == INVALID_SPL_HEADER)
760 if (!spl->fel_script_address)
763 if (spl->fel_uEnv_length != 0) {
765 * data is expected in uEnv.txt compatible format, so "env
766 * import -t" the string(s) at fel_script_address right away.
768 himport_r(&env_htab, (char *)(uintptr_t)spl->fel_script_address,
769 spl->fel_uEnv_length, '\n', H_NOCLEAR, 0, 0, NULL);
772 /* otherwise assume .scr format (mkimage-type script) */
773 env_set_hex("fel_scriptaddr", spl->fel_script_address);
777 * Note this function gets called multiple times.
778 * It must not make any changes to env variables which already exist.
780 static void setup_environment(const void *fdt)
782 char serial_string[17] = { 0 };
788 ret = sunxi_get_sid(sid);
789 if (ret == 0 && sid[0] != 0) {
791 * The single words 1 - 3 of the SID have quite a few bits
792 * which are the same on many models, so we take a crc32
793 * of all 3 words, to get a more unique value.
795 * Note we only do this on newer SoCs as we cannot change
796 * the algorithm on older SoCs since those have been using
797 * fixed mac-addresses based on only using word 3 for a
798 * long time and changing a fixed mac-address with an
799 * u-boot update is not good.
801 #if !defined(CONFIG_MACH_SUN4I) && !defined(CONFIG_MACH_SUN5I) && \
802 !defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_MACH_SUN7I) && \
803 !defined(CONFIG_MACH_SUN8I_A23) && !defined(CONFIG_MACH_SUN8I_A33)
804 sid[3] = crc32(0, (unsigned char *)&sid[1], 12);
807 /* Ensure the NIC specific bytes of the mac are not all 0 */
808 if ((sid[3] & 0xffffff) == 0)
811 for (i = 0; i < 4; i++) {
812 sprintf(ethaddr, "ethernet%d", i);
813 if (!fdt_get_alias(fdt, ethaddr))
817 strcpy(ethaddr, "ethaddr");
819 sprintf(ethaddr, "eth%daddr", i);
821 if (env_get(ethaddr))
824 /* Non OUI / registered MAC address */
825 mac_addr[0] = (i << 4) | 0x02;
826 mac_addr[1] = (sid[0] >> 0) & 0xff;
827 mac_addr[2] = (sid[3] >> 24) & 0xff;
828 mac_addr[3] = (sid[3] >> 16) & 0xff;
829 mac_addr[4] = (sid[3] >> 8) & 0xff;
830 mac_addr[5] = (sid[3] >> 0) & 0xff;
832 eth_env_set_enetaddr(ethaddr, mac_addr);
835 if (!env_get("serial#")) {
836 snprintf(serial_string, sizeof(serial_string),
837 "%08x%08x", sid[0], sid[3]);
839 env_set("serial#", serial_string);
844 int misc_init_r(void)
848 env_set("fel_booted", NULL);
849 env_set("fel_scriptaddr", NULL);
850 env_set("mmc_bootdev", NULL);
852 boot = sunxi_get_boot_device();
853 /* determine if we are running in FEL mode */
854 if (boot == BOOT_DEVICE_BOARD) {
855 env_set("fel_booted", "1");
856 parse_spl_header(SPL_ADDR);
857 /* or if we booted from MMC, and which one */
858 } else if (boot == BOOT_DEVICE_MMC1) {
859 env_set("mmc_bootdev", "0");
860 } else if (boot == BOOT_DEVICE_MMC2) {
861 env_set("mmc_bootdev", "1");
864 setup_environment(gd->fdt_blob);
866 #ifdef CONFIG_USB_ETHER
873 int ft_board_setup(void *blob, bd_t *bd)
875 int __maybe_unused r;
878 * Call setup_environment again in case the boot fdt has
879 * ethernet aliases the u-boot copy does not have.
881 setup_environment(blob);
883 #ifdef CONFIG_VIDEO_DT_SIMPLEFB
884 r = sunxi_simplefb_setup(blob);
891 #ifdef CONFIG_SPL_LOAD_FIT
892 int board_fit_config_name_match(const char *name)
894 struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
895 const char *cmp_str = (const char *)spl;
897 /* Check if there is a DT name stored in the SPL header and use that. */
898 if (spl != INVALID_SPL_HEADER && spl->dt_name_offset) {
899 cmp_str += spl->dt_name_offset;
901 #ifdef CONFIG_DEFAULT_DEVICE_TREE
902 cmp_str = CONFIG_DEFAULT_DEVICE_TREE;
908 #ifdef CONFIG_PINE64_DT_SELECTION
909 /* Differentiate the two Pine64 board DTs by their DRAM size. */
910 if (strstr(name, "-pine64") && strstr(cmp_str, "-pine64")) {
911 if ((gd->ram_size > 512 * 1024 * 1024))
912 return !strstr(name, "plus");
914 return !!strstr(name, "plus");
916 return strcmp(name, cmp_str);
919 return strcmp(name, cmp_str);